CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F1xx devices.
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#include "core_cm3.h"
#include "system_stm32f1xx.h"
#include <stdint.h>

Include dependency graph for stm32f107xc.h:

Go to the source code of this file.

Data Structures
struct	ADC_TypeDef
	Analog to Digital Converter More...

struct	ADC_Common_TypeDef

struct	BKP_TypeDef
	Backup Registers More...

struct	CAN_TxMailBox_TypeDef
	Controller Area Network TxMailBox. More...

struct	CAN_FIFOMailBox_TypeDef
	Controller Area Network FIFOMailBox. More...

struct	CAN_FilterRegister_TypeDef
	Controller Area Network FilterRegister. More...

struct	CAN_TypeDef
	Controller Area Network. More...

struct	CRC_TypeDef
	CRC calculation unit. More...

struct	DAC_TypeDef
	Digital to Analog Converter. More...

struct	DBGMCU_TypeDef
	Debug MCU. More...

struct	DMA_Channel_TypeDef
	DMA Controller. More...

struct	DMA_TypeDef

struct	ETH_TypeDef
	Ethernet MAC. More...

struct	EXTI_TypeDef
	External Interrupt/Event Controller. More...

struct	FLASH_TypeDef
	FLASH Registers. More...

struct	OB_TypeDef
	Option Bytes Registers. More...

struct	GPIO_TypeDef
	General Purpose I/O. More...

struct	AFIO_TypeDef
	Alternate Function I/O. More...

struct	I2C_TypeDef
	Inter Integrated Circuit Interface. More...

struct	IWDG_TypeDef
	Independent WATCHDOG. More...

struct	PWR_TypeDef
	Power Control. More...

struct	RCC_TypeDef
	Reset and Clock Control. More...

struct	RTC_TypeDef
	Real-Time Clock. More...

struct	SPI_TypeDef
	Serial Peripheral Interface. More...

struct	TIM_TypeDef
	TIM Timers. More...

struct	USART_TypeDef
	Universal Synchronous Asynchronous Receiver Transmitter. More...

struct	USB_OTG_GlobalTypeDef
	__USB_OTG_Core_register More...

struct	USB_OTG_DeviceTypeDef
	__device_Registers More...

struct	USB_OTG_INEndpointTypeDef
	__IN_Endpoint-Specific_Register More...

struct	USB_OTG_OUTEndpointTypeDef
	__OUT_Endpoint-Specific_Registers More...

struct	USB_OTG_HostTypeDef
	__Host_Mode_Register_Structures More...

struct	USB_OTG_HostChannelTypeDef
	__Host_Channel_Specific_Registers More...

struct	WWDG_TypeDef
	Window WATCHDOG. More...

Macros
#define	__CM3_REV 0x0200U
	Configuration of the Cortex-M3 Processor and Core Peripherals. More...

#define	__MPU_PRESENT 0U

#define	__NVIC_PRIO_BITS 4U

#define	__Vendor_SysTickConfig 0U

#define	FLASH_BASE 0x08000000UL

#define	FLASH_BANK1_END 0x0803FFFFUL

#define	SRAM_BASE 0x20000000UL

#define	PERIPH_BASE 0x40000000UL

#define	SRAM_BB_BASE 0x22000000UL

#define	PERIPH_BB_BASE 0x42000000UL

#define	APB1PERIPH_BASE PERIPH_BASE

#define	APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)

#define	AHBPERIPH_BASE (PERIPH_BASE + 0x00020000UL)

#define	TIM2_BASE (APB1PERIPH_BASE + 0x00000000UL)

#define	TIM3_BASE (APB1PERIPH_BASE + 0x00000400UL)

#define	TIM4_BASE (APB1PERIPH_BASE + 0x00000800UL)

#define	TIM5_BASE (APB1PERIPH_BASE + 0x00000C00UL)

#define	TIM6_BASE (APB1PERIPH_BASE + 0x00001000UL)

#define	TIM7_BASE (APB1PERIPH_BASE + 0x00001400UL)

#define	RTC_BASE (APB1PERIPH_BASE + 0x00002800UL)

#define	WWDG_BASE (APB1PERIPH_BASE + 0x00002C00UL)

#define	IWDG_BASE (APB1PERIPH_BASE + 0x00003000UL)

#define	SPI2_BASE (APB1PERIPH_BASE + 0x00003800UL)

#define	SPI3_BASE (APB1PERIPH_BASE + 0x00003C00UL)

#define	USART2_BASE (APB1PERIPH_BASE + 0x00004400UL)

#define	USART3_BASE (APB1PERIPH_BASE + 0x00004800UL)

#define	UART4_BASE (APB1PERIPH_BASE + 0x00004C00UL)

#define	UART5_BASE (APB1PERIPH_BASE + 0x00005000UL)

#define	I2C1_BASE (APB1PERIPH_BASE + 0x00005400UL)

#define	I2C2_BASE (APB1PERIPH_BASE + 0x00005800UL)

#define	CAN1_BASE (APB1PERIPH_BASE + 0x00006400UL)

#define	CAN2_BASE (APB1PERIPH_BASE + 0x00006800UL)

#define	BKP_BASE (APB1PERIPH_BASE + 0x00006C00UL)

#define	PWR_BASE (APB1PERIPH_BASE + 0x00007000UL)

#define	DAC_BASE (APB1PERIPH_BASE + 0x00007400UL)

#define	AFIO_BASE (APB2PERIPH_BASE + 0x00000000UL)

#define	EXTI_BASE (APB2PERIPH_BASE + 0x00000400UL)

#define	GPIOA_BASE (APB2PERIPH_BASE + 0x00000800UL)

#define	GPIOB_BASE (APB2PERIPH_BASE + 0x00000C00UL)

#define	GPIOC_BASE (APB2PERIPH_BASE + 0x00001000UL)

#define	GPIOD_BASE (APB2PERIPH_BASE + 0x00001400UL)

#define	GPIOE_BASE (APB2PERIPH_BASE + 0x00001800UL)

#define	ADC1_BASE (APB2PERIPH_BASE + 0x00002400UL)

#define	ADC2_BASE (APB2PERIPH_BASE + 0x00002800UL)

#define	TIM1_BASE (APB2PERIPH_BASE + 0x00002C00UL)

#define	SPI1_BASE (APB2PERIPH_BASE + 0x00003000UL)

#define	USART1_BASE (APB2PERIPH_BASE + 0x00003800UL)

#define	DMA1_BASE (AHBPERIPH_BASE + 0x00000000UL)

#define	DMA1_Channel1_BASE (AHBPERIPH_BASE + 0x00000008UL)

#define	DMA1_Channel2_BASE (AHBPERIPH_BASE + 0x0000001CUL)

#define	DMA1_Channel3_BASE (AHBPERIPH_BASE + 0x00000030UL)

#define	DMA1_Channel4_BASE (AHBPERIPH_BASE + 0x00000044UL)

#define	DMA1_Channel5_BASE (AHBPERIPH_BASE + 0x00000058UL)

#define	DMA1_Channel6_BASE (AHBPERIPH_BASE + 0x0000006CUL)

#define	DMA1_Channel7_BASE (AHBPERIPH_BASE + 0x00000080UL)

#define	DMA2_BASE (AHBPERIPH_BASE + 0x00000400UL)

#define	DMA2_Channel1_BASE (AHBPERIPH_BASE + 0x00000408UL)

#define	DMA2_Channel2_BASE (AHBPERIPH_BASE + 0x0000041CUL)

#define	DMA2_Channel3_BASE (AHBPERIPH_BASE + 0x00000430UL)

#define	DMA2_Channel4_BASE (AHBPERIPH_BASE + 0x00000444UL)

#define	DMA2_Channel5_BASE (AHBPERIPH_BASE + 0x00000458UL)

#define	RCC_BASE (AHBPERIPH_BASE + 0x00001000UL)

#define	CRC_BASE (AHBPERIPH_BASE + 0x00003000UL)

#define	FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000UL)

#define	FLASHSIZE_BASE 0x1FFFF7E0UL

#define	UID_BASE 0x1FFFF7E8UL

#define	OB_BASE 0x1FFFF800UL

#define	ETH_BASE (AHBPERIPH_BASE + 0x00008000UL)

#define	ETH_MAC_BASE (ETH_BASE)

#define	ETH_MMC_BASE (ETH_BASE + 0x00000100UL)

#define	ETH_PTP_BASE (ETH_BASE + 0x00000700UL)

#define	ETH_DMA_BASE (ETH_BASE + 0x00001000UL)

#define	DBGMCU_BASE 0xE0042000UL

#define	USB_OTG_FS_PERIPH_BASE 0x50000000UL

#define	USB_OTG_GLOBAL_BASE 0x00000000UL

#define	USB_OTG_DEVICE_BASE 0x00000800UL

#define	USB_OTG_IN_ENDPOINT_BASE 0x00000900UL

#define	USB_OTG_OUT_ENDPOINT_BASE 0x00000B00UL

#define	USB_OTG_EP_REG_SIZE 0x00000020UL

#define	USB_OTG_HOST_BASE 0x00000400UL

#define	USB_OTG_HOST_PORT_BASE 0x00000440UL

#define	USB_OTG_HOST_CHANNEL_BASE 0x00000500UL

#define	USB_OTG_HOST_CHANNEL_SIZE 0x00000020UL

#define	USB_OTG_PCGCCTL_BASE 0x00000E00UL

#define	USB_OTG_FIFO_BASE 0x00001000UL

#define	USB_OTG_FIFO_SIZE 0x00001000UL

#define	TIM2 ((TIM_TypeDef *)TIM2_BASE)

#define	TIM3 ((TIM_TypeDef *)TIM3_BASE)

#define	TIM4 ((TIM_TypeDef *)TIM4_BASE)

#define	TIM5 ((TIM_TypeDef *)TIM5_BASE)

#define	TIM6 ((TIM_TypeDef *)TIM6_BASE)

#define	TIM7 ((TIM_TypeDef *)TIM7_BASE)

#define	RTC ((RTC_TypeDef *)RTC_BASE)

#define	WWDG ((WWDG_TypeDef *)WWDG_BASE)

#define	IWDG ((IWDG_TypeDef *)IWDG_BASE)

#define	SPI2 ((SPI_TypeDef *)SPI2_BASE)

#define	SPI3 ((SPI_TypeDef *)SPI3_BASE)

#define	USART2 ((USART_TypeDef *)USART2_BASE)

#define	USART3 ((USART_TypeDef *)USART3_BASE)

#define	UART4 ((USART_TypeDef *)UART4_BASE)

#define	UART5 ((USART_TypeDef *)UART5_BASE)

#define	I2C1 ((I2C_TypeDef *)I2C1_BASE)

#define	I2C2 ((I2C_TypeDef *)I2C2_BASE)

#define	CAN1 ((CAN_TypeDef *)CAN1_BASE)

#define	CAN2 ((CAN_TypeDef *)CAN2_BASE)

#define	BKP ((BKP_TypeDef *)BKP_BASE)

#define	PWR ((PWR_TypeDef *)PWR_BASE)

#define	DAC1 ((DAC_TypeDef *)DAC_BASE)

#define	DAC ((DAC_TypeDef )DAC_BASE) / Kept for legacy purpose */

#define	AFIO ((AFIO_TypeDef *)AFIO_BASE)

#define	EXTI ((EXTI_TypeDef *)EXTI_BASE)

#define	GPIOA ((GPIO_TypeDef *)GPIOA_BASE)

#define	GPIOB ((GPIO_TypeDef *)GPIOB_BASE)

#define	GPIOC ((GPIO_TypeDef *)GPIOC_BASE)

#define	GPIOD ((GPIO_TypeDef *)GPIOD_BASE)

#define	GPIOE ((GPIO_TypeDef *)GPIOE_BASE)

#define	ADC1 ((ADC_TypeDef *)ADC1_BASE)

#define	ADC2 ((ADC_TypeDef *)ADC2_BASE)

#define	ADC12_COMMON ((ADC_Common_TypeDef *)ADC1_BASE)

#define	TIM1 ((TIM_TypeDef *)TIM1_BASE)

#define	SPI1 ((SPI_TypeDef *)SPI1_BASE)

#define	USART1 ((USART_TypeDef *)USART1_BASE)

#define	DMA1 ((DMA_TypeDef *)DMA1_BASE)

#define	DMA2 ((DMA_TypeDef *)DMA2_BASE)

#define	DMA1_Channel1 ((DMA_Channel_TypeDef *)DMA1_Channel1_BASE)

#define	DMA1_Channel2 ((DMA_Channel_TypeDef *)DMA1_Channel2_BASE)

#define	DMA1_Channel3 ((DMA_Channel_TypeDef *)DMA1_Channel3_BASE)

#define	DMA1_Channel4 ((DMA_Channel_TypeDef *)DMA1_Channel4_BASE)

#define	DMA1_Channel5 ((DMA_Channel_TypeDef *)DMA1_Channel5_BASE)

#define	DMA1_Channel6 ((DMA_Channel_TypeDef *)DMA1_Channel6_BASE)

#define	DMA1_Channel7 ((DMA_Channel_TypeDef *)DMA1_Channel7_BASE)

#define	DMA2_Channel1 ((DMA_Channel_TypeDef *)DMA2_Channel1_BASE)

#define	DMA2_Channel2 ((DMA_Channel_TypeDef *)DMA2_Channel2_BASE)

#define	DMA2_Channel3 ((DMA_Channel_TypeDef *)DMA2_Channel3_BASE)

#define	DMA2_Channel4 ((DMA_Channel_TypeDef *)DMA2_Channel4_BASE)

#define	DMA2_Channel5 ((DMA_Channel_TypeDef *)DMA2_Channel5_BASE)

#define	RCC ((RCC_TypeDef *)RCC_BASE)

#define	CRC ((CRC_TypeDef *)CRC_BASE)

#define	FLASH ((FLASH_TypeDef *)FLASH_R_BASE)

#define	OB ((OB_TypeDef *)OB_BASE)

#define	ETH ((ETH_TypeDef *) ETH_BASE)

#define	DBGMCU ((DBGMCU_TypeDef *)DBGMCU_BASE)

#define	USB_OTG_FS ((USB_OTG_GlobalTypeDef *)USB_OTG_FS_PERIPH_BASE)

#define	LSI_STARTUP_TIME 85U

#define	CRC_DR_DR_Pos (0U)

#define	CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos)

#define	CRC_DR_DR CRC_DR_DR_Msk

#define	CRC_IDR_IDR_Pos (0U)

#define	CRC_IDR_IDR_Msk (0xFFUL << CRC_IDR_IDR_Pos)

#define	CRC_IDR_IDR CRC_IDR_IDR_Msk

#define	CRC_CR_RESET_Pos (0U)

#define	CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos)

#define	CRC_CR_RESET CRC_CR_RESET_Msk

#define	PWR_CR_LPDS_Pos (0U)

#define	PWR_CR_LPDS_Msk (0x1UL << PWR_CR_LPDS_Pos)

#define	PWR_CR_LPDS PWR_CR_LPDS_Msk

#define	PWR_CR_PDDS_Pos (1U)

#define	PWR_CR_PDDS_Msk (0x1UL << PWR_CR_PDDS_Pos)

#define	PWR_CR_PDDS PWR_CR_PDDS_Msk

#define	PWR_CR_CWUF_Pos (2U)

#define	PWR_CR_CWUF_Msk (0x1UL << PWR_CR_CWUF_Pos)

#define	PWR_CR_CWUF PWR_CR_CWUF_Msk

#define	PWR_CR_CSBF_Pos (3U)

#define	PWR_CR_CSBF_Msk (0x1UL << PWR_CR_CSBF_Pos)

#define	PWR_CR_CSBF PWR_CR_CSBF_Msk

#define	PWR_CR_PVDE_Pos (4U)

#define	PWR_CR_PVDE_Msk (0x1UL << PWR_CR_PVDE_Pos)

#define	PWR_CR_PVDE PWR_CR_PVDE_Msk

#define	PWR_CR_PLS_Pos (5U)

#define	PWR_CR_PLS_Msk (0x7UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS PWR_CR_PLS_Msk

#define	PWR_CR_PLS_0 (0x1UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_1 (0x2UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_2 (0x4UL << PWR_CR_PLS_Pos)

#define	PWR_CR_PLS_LEV0 0x00000000U

#define	PWR_CR_PLS_LEV1 0x00000020U

#define	PWR_CR_PLS_LEV2 0x00000040U

#define	PWR_CR_PLS_LEV3 0x00000060U

#define	PWR_CR_PLS_LEV4 0x00000080U

#define	PWR_CR_PLS_LEV5 0x000000A0U

#define	PWR_CR_PLS_LEV6 0x000000C0U

#define	PWR_CR_PLS_LEV7 0x000000E0U

#define	PWR_CR_PLS_2V2 PWR_CR_PLS_LEV0

#define	PWR_CR_PLS_2V3 PWR_CR_PLS_LEV1

#define	PWR_CR_PLS_2V4 PWR_CR_PLS_LEV2

#define	PWR_CR_PLS_2V5 PWR_CR_PLS_LEV3

#define	PWR_CR_PLS_2V6 PWR_CR_PLS_LEV4

#define	PWR_CR_PLS_2V7 PWR_CR_PLS_LEV5

#define	PWR_CR_PLS_2V8 PWR_CR_PLS_LEV6

#define	PWR_CR_PLS_2V9 PWR_CR_PLS_LEV7

#define	PWR_CR_DBP_Pos (8U)

#define	PWR_CR_DBP_Msk (0x1UL << PWR_CR_DBP_Pos)

#define	PWR_CR_DBP PWR_CR_DBP_Msk

#define	PWR_CSR_WUF_Pos (0U)

#define	PWR_CSR_WUF_Msk (0x1UL << PWR_CSR_WUF_Pos)

#define	PWR_CSR_WUF PWR_CSR_WUF_Msk

#define	PWR_CSR_SBF_Pos (1U)

#define	PWR_CSR_SBF_Msk (0x1UL << PWR_CSR_SBF_Pos)

#define	PWR_CSR_SBF PWR_CSR_SBF_Msk

#define	PWR_CSR_PVDO_Pos (2U)

#define	PWR_CSR_PVDO_Msk (0x1UL << PWR_CSR_PVDO_Pos)

#define	PWR_CSR_PVDO PWR_CSR_PVDO_Msk

#define	PWR_CSR_EWUP_Pos (8U)

#define	PWR_CSR_EWUP_Msk (0x1UL << PWR_CSR_EWUP_Pos)

#define	PWR_CSR_EWUP PWR_CSR_EWUP_Msk

#define	BKP_DR1_D_Pos (0U)

#define	BKP_DR1_D_Msk (0xFFFFUL << BKP_DR1_D_Pos)

#define	BKP_DR1_D BKP_DR1_D_Msk

#define	BKP_DR2_D_Pos (0U)

#define	BKP_DR2_D_Msk (0xFFFFUL << BKP_DR2_D_Pos)

#define	BKP_DR2_D BKP_DR2_D_Msk

#define	BKP_DR3_D_Pos (0U)

#define	BKP_DR3_D_Msk (0xFFFFUL << BKP_DR3_D_Pos)

#define	BKP_DR3_D BKP_DR3_D_Msk

#define	BKP_DR4_D_Pos (0U)

#define	BKP_DR4_D_Msk (0xFFFFUL << BKP_DR4_D_Pos)

#define	BKP_DR4_D BKP_DR4_D_Msk

#define	BKP_DR5_D_Pos (0U)

#define	BKP_DR5_D_Msk (0xFFFFUL << BKP_DR5_D_Pos)

#define	BKP_DR5_D BKP_DR5_D_Msk

#define	BKP_DR6_D_Pos (0U)

#define	BKP_DR6_D_Msk (0xFFFFUL << BKP_DR6_D_Pos)

#define	BKP_DR6_D BKP_DR6_D_Msk

#define	BKP_DR7_D_Pos (0U)

#define	BKP_DR7_D_Msk (0xFFFFUL << BKP_DR7_D_Pos)

#define	BKP_DR7_D BKP_DR7_D_Msk

#define	BKP_DR8_D_Pos (0U)

#define	BKP_DR8_D_Msk (0xFFFFUL << BKP_DR8_D_Pos)

#define	BKP_DR8_D BKP_DR8_D_Msk

#define	BKP_DR9_D_Pos (0U)

#define	BKP_DR9_D_Msk (0xFFFFUL << BKP_DR9_D_Pos)

#define	BKP_DR9_D BKP_DR9_D_Msk

#define	BKP_DR10_D_Pos (0U)

#define	BKP_DR10_D_Msk (0xFFFFUL << BKP_DR10_D_Pos)

#define	BKP_DR10_D BKP_DR10_D_Msk

#define	BKP_DR11_D_Pos (0U)

#define	BKP_DR11_D_Msk (0xFFFFUL << BKP_DR11_D_Pos)

#define	BKP_DR11_D BKP_DR11_D_Msk

#define	BKP_DR12_D_Pos (0U)

#define	BKP_DR12_D_Msk (0xFFFFUL << BKP_DR12_D_Pos)

#define	BKP_DR12_D BKP_DR12_D_Msk

#define	BKP_DR13_D_Pos (0U)

#define	BKP_DR13_D_Msk (0xFFFFUL << BKP_DR13_D_Pos)

#define	BKP_DR13_D BKP_DR13_D_Msk

#define	BKP_DR14_D_Pos (0U)

#define	BKP_DR14_D_Msk (0xFFFFUL << BKP_DR14_D_Pos)

#define	BKP_DR14_D BKP_DR14_D_Msk

#define	BKP_DR15_D_Pos (0U)

#define	BKP_DR15_D_Msk (0xFFFFUL << BKP_DR15_D_Pos)

#define	BKP_DR15_D BKP_DR15_D_Msk

#define	BKP_DR16_D_Pos (0U)

#define	BKP_DR16_D_Msk (0xFFFFUL << BKP_DR16_D_Pos)

#define	BKP_DR16_D BKP_DR16_D_Msk

#define	BKP_DR17_D_Pos (0U)

#define	BKP_DR17_D_Msk (0xFFFFUL << BKP_DR17_D_Pos)

#define	BKP_DR17_D BKP_DR17_D_Msk

#define	BKP_DR18_D_Pos (0U)

#define	BKP_DR18_D_Msk (0xFFFFUL << BKP_DR18_D_Pos)

#define	BKP_DR18_D BKP_DR18_D_Msk

#define	BKP_DR19_D_Pos (0U)

#define	BKP_DR19_D_Msk (0xFFFFUL << BKP_DR19_D_Pos)

#define	BKP_DR19_D BKP_DR19_D_Msk

#define	BKP_DR20_D_Pos (0U)

#define	BKP_DR20_D_Msk (0xFFFFUL << BKP_DR20_D_Pos)

#define	BKP_DR20_D BKP_DR20_D_Msk

#define	BKP_DR21_D_Pos (0U)

#define	BKP_DR21_D_Msk (0xFFFFUL << BKP_DR21_D_Pos)

#define	BKP_DR21_D BKP_DR21_D_Msk

#define	BKP_DR22_D_Pos (0U)

#define	BKP_DR22_D_Msk (0xFFFFUL << BKP_DR22_D_Pos)

#define	BKP_DR22_D BKP_DR22_D_Msk

#define	BKP_DR23_D_Pos (0U)

#define	BKP_DR23_D_Msk (0xFFFFUL << BKP_DR23_D_Pos)

#define	BKP_DR23_D BKP_DR23_D_Msk

#define	BKP_DR24_D_Pos (0U)

#define	BKP_DR24_D_Msk (0xFFFFUL << BKP_DR24_D_Pos)

#define	BKP_DR24_D BKP_DR24_D_Msk

#define	BKP_DR25_D_Pos (0U)

#define	BKP_DR25_D_Msk (0xFFFFUL << BKP_DR25_D_Pos)

#define	BKP_DR25_D BKP_DR25_D_Msk

#define	BKP_DR26_D_Pos (0U)

#define	BKP_DR26_D_Msk (0xFFFFUL << BKP_DR26_D_Pos)

#define	BKP_DR26_D BKP_DR26_D_Msk

#define	BKP_DR27_D_Pos (0U)

#define	BKP_DR27_D_Msk (0xFFFFUL << BKP_DR27_D_Pos)

#define	BKP_DR27_D BKP_DR27_D_Msk

#define	BKP_DR28_D_Pos (0U)

#define	BKP_DR28_D_Msk (0xFFFFUL << BKP_DR28_D_Pos)

#define	BKP_DR28_D BKP_DR28_D_Msk

#define	BKP_DR29_D_Pos (0U)

#define	BKP_DR29_D_Msk (0xFFFFUL << BKP_DR29_D_Pos)

#define	BKP_DR29_D BKP_DR29_D_Msk

#define	BKP_DR30_D_Pos (0U)

#define	BKP_DR30_D_Msk (0xFFFFUL << BKP_DR30_D_Pos)

#define	BKP_DR30_D BKP_DR30_D_Msk

#define	BKP_DR31_D_Pos (0U)

#define	BKP_DR31_D_Msk (0xFFFFUL << BKP_DR31_D_Pos)

#define	BKP_DR31_D BKP_DR31_D_Msk

#define	BKP_DR32_D_Pos (0U)

#define	BKP_DR32_D_Msk (0xFFFFUL << BKP_DR32_D_Pos)

#define	BKP_DR32_D BKP_DR32_D_Msk

#define	BKP_DR33_D_Pos (0U)

#define	BKP_DR33_D_Msk (0xFFFFUL << BKP_DR33_D_Pos)

#define	BKP_DR33_D BKP_DR33_D_Msk

#define	BKP_DR34_D_Pos (0U)

#define	BKP_DR34_D_Msk (0xFFFFUL << BKP_DR34_D_Pos)

#define	BKP_DR34_D BKP_DR34_D_Msk

#define	BKP_DR35_D_Pos (0U)

#define	BKP_DR35_D_Msk (0xFFFFUL << BKP_DR35_D_Pos)

#define	BKP_DR35_D BKP_DR35_D_Msk

#define	BKP_DR36_D_Pos (0U)

#define	BKP_DR36_D_Msk (0xFFFFUL << BKP_DR36_D_Pos)

#define	BKP_DR36_D BKP_DR36_D_Msk

#define	BKP_DR37_D_Pos (0U)

#define	BKP_DR37_D_Msk (0xFFFFUL << BKP_DR37_D_Pos)

#define	BKP_DR37_D BKP_DR37_D_Msk

#define	BKP_DR38_D_Pos (0U)

#define	BKP_DR38_D_Msk (0xFFFFUL << BKP_DR38_D_Pos)

#define	BKP_DR38_D BKP_DR38_D_Msk

#define	BKP_DR39_D_Pos (0U)

#define	BKP_DR39_D_Msk (0xFFFFUL << BKP_DR39_D_Pos)

#define	BKP_DR39_D BKP_DR39_D_Msk

#define	BKP_DR40_D_Pos (0U)

#define	BKP_DR40_D_Msk (0xFFFFUL << BKP_DR40_D_Pos)

#define	BKP_DR40_D BKP_DR40_D_Msk

#define	BKP_DR41_D_Pos (0U)

#define	BKP_DR41_D_Msk (0xFFFFUL << BKP_DR41_D_Pos)

#define	BKP_DR41_D BKP_DR41_D_Msk

#define	BKP_DR42_D_Pos (0U)

#define	BKP_DR42_D_Msk (0xFFFFUL << BKP_DR42_D_Pos)

#define	BKP_DR42_D BKP_DR42_D_Msk

#define	RTC_BKP_NUMBER 42

#define	BKP_RTCCR_CAL_Pos (0U)

#define	BKP_RTCCR_CAL_Msk (0x7FUL << BKP_RTCCR_CAL_Pos)

#define	BKP_RTCCR_CAL BKP_RTCCR_CAL_Msk

#define	BKP_RTCCR_CCO_Pos (7U)

#define	BKP_RTCCR_CCO_Msk (0x1UL << BKP_RTCCR_CCO_Pos)

#define	BKP_RTCCR_CCO BKP_RTCCR_CCO_Msk

#define	BKP_RTCCR_ASOE_Pos (8U)

#define	BKP_RTCCR_ASOE_Msk (0x1UL << BKP_RTCCR_ASOE_Pos)

#define	BKP_RTCCR_ASOE BKP_RTCCR_ASOE_Msk

#define	BKP_RTCCR_ASOS_Pos (9U)

#define	BKP_RTCCR_ASOS_Msk (0x1UL << BKP_RTCCR_ASOS_Pos)

#define	BKP_RTCCR_ASOS BKP_RTCCR_ASOS_Msk

#define	BKP_CR_TPE_Pos (0U)

#define	BKP_CR_TPE_Msk (0x1UL << BKP_CR_TPE_Pos)

#define	BKP_CR_TPE BKP_CR_TPE_Msk

#define	BKP_CR_TPAL_Pos (1U)

#define	BKP_CR_TPAL_Msk (0x1UL << BKP_CR_TPAL_Pos)

#define	BKP_CR_TPAL BKP_CR_TPAL_Msk

#define	BKP_CSR_CTE_Pos (0U)

#define	BKP_CSR_CTE_Msk (0x1UL << BKP_CSR_CTE_Pos)

#define	BKP_CSR_CTE BKP_CSR_CTE_Msk

#define	BKP_CSR_CTI_Pos (1U)

#define	BKP_CSR_CTI_Msk (0x1UL << BKP_CSR_CTI_Pos)

#define	BKP_CSR_CTI BKP_CSR_CTI_Msk

#define	BKP_CSR_TPIE_Pos (2U)

#define	BKP_CSR_TPIE_Msk (0x1UL << BKP_CSR_TPIE_Pos)

#define	BKP_CSR_TPIE BKP_CSR_TPIE_Msk

#define	BKP_CSR_TEF_Pos (8U)

#define	BKP_CSR_TEF_Msk (0x1UL << BKP_CSR_TEF_Pos)

#define	BKP_CSR_TEF BKP_CSR_TEF_Msk

#define	BKP_CSR_TIF_Pos (9U)

#define	BKP_CSR_TIF_Msk (0x1UL << BKP_CSR_TIF_Pos)

#define	BKP_CSR_TIF BKP_CSR_TIF_Msk

#define	RCC_PLL2_SUPPORT

#define	RCC_PLLI2S_SUPPORT

#define	RCC_CR_HSION_Pos (0U)

#define	RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos)

#define	RCC_CR_HSION RCC_CR_HSION_Msk

#define	RCC_CR_HSIRDY_Pos (1U)

#define	RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos)

#define	RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk

#define	RCC_CR_HSITRIM_Pos (3U)

#define	RCC_CR_HSITRIM_Msk (0x1FUL << RCC_CR_HSITRIM_Pos)

#define	RCC_CR_HSITRIM RCC_CR_HSITRIM_Msk

#define	RCC_CR_HSICAL_Pos (8U)

#define	RCC_CR_HSICAL_Msk (0xFFUL << RCC_CR_HSICAL_Pos)

#define	RCC_CR_HSICAL RCC_CR_HSICAL_Msk

#define	RCC_CR_HSEON_Pos (16U)

#define	RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos)

#define	RCC_CR_HSEON RCC_CR_HSEON_Msk

#define	RCC_CR_HSERDY_Pos (17U)

#define	RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos)

#define	RCC_CR_HSERDY RCC_CR_HSERDY_Msk

#define	RCC_CR_HSEBYP_Pos (18U)

#define	RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos)

#define	RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk

#define	RCC_CR_CSSON_Pos (19U)

#define	RCC_CR_CSSON_Msk (0x1UL << RCC_CR_CSSON_Pos)

#define	RCC_CR_CSSON RCC_CR_CSSON_Msk

#define	RCC_CR_PLLON_Pos (24U)

#define	RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos)

#define	RCC_CR_PLLON RCC_CR_PLLON_Msk

#define	RCC_CR_PLLRDY_Pos (25U)

#define	RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos)

#define	RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk

#define	RCC_CR_PLL2ON_Pos (26U)

#define	RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos)

#define	RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk

#define	RCC_CR_PLL2RDY_Pos (27U)

#define	RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos)

#define	RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk

#define	RCC_CR_PLL3ON_Pos (28U)

#define	RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos)

#define	RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk

#define	RCC_CR_PLL3RDY_Pos (29U)

#define	RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos)

#define	RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk

#define	RCC_CFGR_SW_Pos (0U)

#define	RCC_CFGR_SW_Msk (0x3UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW RCC_CFGR_SW_Msk

#define	RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos)

#define	RCC_CFGR_SW_HSI 0x00000000U

#define	RCC_CFGR_SW_HSE 0x00000001U

#define	RCC_CFGR_SW_PLL 0x00000002U

#define	RCC_CFGR_SWS_Pos (2U)

#define	RCC_CFGR_SWS_Msk (0x3UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS RCC_CFGR_SWS_Msk

#define	RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos)

#define	RCC_CFGR_SWS_HSI 0x00000000U

#define	RCC_CFGR_SWS_HSE 0x00000004U

#define	RCC_CFGR_SWS_PLL 0x00000008U

#define	RCC_CFGR_HPRE_Pos (4U)

#define	RCC_CFGR_HPRE_Msk (0xFUL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE RCC_CFGR_HPRE_Msk

#define	RCC_CFGR_HPRE_0 (0x1UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_1 (0x2UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_2 (0x4UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_3 (0x8UL << RCC_CFGR_HPRE_Pos)

#define	RCC_CFGR_HPRE_DIV1 0x00000000U

#define	RCC_CFGR_HPRE_DIV2 0x00000080U

#define	RCC_CFGR_HPRE_DIV4 0x00000090U

#define	RCC_CFGR_HPRE_DIV8 0x000000A0U

#define	RCC_CFGR_HPRE_DIV16 0x000000B0U

#define	RCC_CFGR_HPRE_DIV64 0x000000C0U

#define	RCC_CFGR_HPRE_DIV128 0x000000D0U

#define	RCC_CFGR_HPRE_DIV256 0x000000E0U

#define	RCC_CFGR_HPRE_DIV512 0x000000F0U

#define	RCC_CFGR_PPRE1_Pos (8U)

#define	RCC_CFGR_PPRE1_Msk (0x7UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1 RCC_CFGR_PPRE1_Msk

#define	RCC_CFGR_PPRE1_0 (0x1UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_1 (0x2UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_2 (0x4UL << RCC_CFGR_PPRE1_Pos)

#define	RCC_CFGR_PPRE1_DIV1 0x00000000U

#define	RCC_CFGR_PPRE1_DIV2 0x00000400U

#define	RCC_CFGR_PPRE1_DIV4 0x00000500U

#define	RCC_CFGR_PPRE1_DIV8 0x00000600U

#define	RCC_CFGR_PPRE1_DIV16 0x00000700U

#define	RCC_CFGR_PPRE2_Pos (11U)

#define	RCC_CFGR_PPRE2_Msk (0x7UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2 RCC_CFGR_PPRE2_Msk

#define	RCC_CFGR_PPRE2_0 (0x1UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_1 (0x2UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_2 (0x4UL << RCC_CFGR_PPRE2_Pos)

#define	RCC_CFGR_PPRE2_DIV1 0x00000000U

#define	RCC_CFGR_PPRE2_DIV2 0x00002000U

#define	RCC_CFGR_PPRE2_DIV4 0x00002800U

#define	RCC_CFGR_PPRE2_DIV8 0x00003000U

#define	RCC_CFGR_PPRE2_DIV16 0x00003800U

#define	RCC_CFGR_ADCPRE_Pos (14U)

#define	RCC_CFGR_ADCPRE_Msk (0x3UL << RCC_CFGR_ADCPRE_Pos)

#define	RCC_CFGR_ADCPRE RCC_CFGR_ADCPRE_Msk

#define	RCC_CFGR_ADCPRE_0 (0x1UL << RCC_CFGR_ADCPRE_Pos)

#define	RCC_CFGR_ADCPRE_1 (0x2UL << RCC_CFGR_ADCPRE_Pos)

#define	RCC_CFGR_ADCPRE_DIV2 0x00000000U

#define	RCC_CFGR_ADCPRE_DIV4 0x00004000U

#define	RCC_CFGR_ADCPRE_DIV6 0x00008000U

#define	RCC_CFGR_ADCPRE_DIV8 0x0000C000U

#define	RCC_CFGR_PLLSRC_Pos (16U)

#define	RCC_CFGR_PLLSRC_Msk (0x1UL << RCC_CFGR_PLLSRC_Pos)

#define	RCC_CFGR_PLLSRC RCC_CFGR_PLLSRC_Msk

#define	RCC_CFGR_PLLXTPRE_Pos (17U)

#define	RCC_CFGR_PLLXTPRE_Msk (0x1UL << RCC_CFGR_PLLXTPRE_Pos)

#define	RCC_CFGR_PLLXTPRE RCC_CFGR_PLLXTPRE_Msk

#define	RCC_CFGR_PLLMULL_Pos (18U)

#define	RCC_CFGR_PLLMULL_Msk (0xFUL << RCC_CFGR_PLLMULL_Pos)

#define	RCC_CFGR_PLLMULL RCC_CFGR_PLLMULL_Msk

#define	RCC_CFGR_PLLMULL_0 (0x1UL << RCC_CFGR_PLLMULL_Pos)

#define	RCC_CFGR_PLLMULL_1 (0x2UL << RCC_CFGR_PLLMULL_Pos)

#define	RCC_CFGR_PLLMULL_2 (0x4UL << RCC_CFGR_PLLMULL_Pos)

#define	RCC_CFGR_PLLMULL_3 (0x8UL << RCC_CFGR_PLLMULL_Pos)

#define	RCC_CFGR_PLLXTPRE_PREDIV1 0x00000000U

#define	RCC_CFGR_PLLXTPRE_PREDIV1_DIV2 0x00020000U

#define	RCC_CFGR_PLLMULL4_Pos (19U)

#define	RCC_CFGR_PLLMULL4_Msk (0x1UL << RCC_CFGR_PLLMULL4_Pos)

#define	RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMULL4_Msk

#define	RCC_CFGR_PLLMULL5_Pos (18U)

#define	RCC_CFGR_PLLMULL5_Msk (0x3UL << RCC_CFGR_PLLMULL5_Pos)

#define	RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMULL5_Msk

#define	RCC_CFGR_PLLMULL6_Pos (20U)

#define	RCC_CFGR_PLLMULL6_Msk (0x1UL << RCC_CFGR_PLLMULL6_Pos)

#define	RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMULL6_Msk

#define	RCC_CFGR_PLLMULL7_Pos (18U)

#define	RCC_CFGR_PLLMULL7_Msk (0x5UL << RCC_CFGR_PLLMULL7_Pos)

#define	RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMULL7_Msk

#define	RCC_CFGR_PLLMULL8_Pos (19U)

#define	RCC_CFGR_PLLMULL8_Msk (0x3UL << RCC_CFGR_PLLMULL8_Pos)

#define	RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMULL8_Msk

#define	RCC_CFGR_PLLMULL9_Pos (18U)

#define	RCC_CFGR_PLLMULL9_Msk (0x7UL << RCC_CFGR_PLLMULL9_Pos)

#define	RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMULL9_Msk

#define	RCC_CFGR_PLLMULL6_5 0x00340000U

#define	RCC_CFGR_OTGFSPRE_Pos (22U)

#define	RCC_CFGR_OTGFSPRE_Msk (0x1UL << RCC_CFGR_OTGFSPRE_Pos)

#define	RCC_CFGR_OTGFSPRE RCC_CFGR_OTGFSPRE_Msk

#define	RCC_CFGR_MCO_Pos (24U)

#define	RCC_CFGR_MCO_Msk (0xFUL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO RCC_CFGR_MCO_Msk

#define	RCC_CFGR_MCO_0 (0x1UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_1 (0x2UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_2 (0x4UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_3 (0x8UL << RCC_CFGR_MCO_Pos)

#define	RCC_CFGR_MCO_NOCLOCK 0x00000000U

#define	RCC_CFGR_MCO_SYSCLK 0x04000000U

#define	RCC_CFGR_MCO_HSI 0x05000000U

#define	RCC_CFGR_MCO_HSE 0x06000000U

#define	RCC_CFGR_MCO_PLLCLK_DIV2 0x07000000U

#define	RCC_CFGR_MCO_PLL2CLK 0x08000000U

#define	RCC_CFGR_MCO_PLL3CLK_DIV2 0x09000000U

#define	RCC_CFGR_MCO_EXT_HSE 0x0A000000U

#define	RCC_CFGR_MCO_PLL3CLK 0x0B000000U

#define	RCC_CFGR_MCOSEL RCC_CFGR_MCO

#define	RCC_CFGR_MCOSEL_0 RCC_CFGR_MCO_0

#define	RCC_CFGR_MCOSEL_1 RCC_CFGR_MCO_1

#define	RCC_CFGR_MCOSEL_2 RCC_CFGR_MCO_2

#define	RCC_CFGR_MCOSEL_3 RCC_CFGR_MCO_3

#define	RCC_CFGR_MCOSEL_NOCLOCK RCC_CFGR_MCO_NOCLOCK

#define	RCC_CFGR_MCOSEL_SYSCLK RCC_CFGR_MCO_SYSCLK

#define	RCC_CFGR_MCOSEL_HSI RCC_CFGR_MCO_HSI

#define	RCC_CFGR_MCOSEL_HSE RCC_CFGR_MCO_HSE

#define	RCC_CFGR_MCOSEL_PLL_DIV2 RCC_CFGR_MCO_PLLCLK_DIV2

#define	RCC_CFGR_MCOSEL_PLL2 RCC_CFGR_MCO_PLL2CLK

#define	RCC_CFGR_MCOSEL_PLL3_DIV2 RCC_CFGR_MCO_PLL3CLK_DIV2

#define	RCC_CFGR_MCOSEL_EXT_HSE RCC_CFGR_MCO_EXT_HSE

#define	RCC_CFGR_MCOSEL_PLL3CLK RCC_CFGR_MCO_PLL3CLK

#define	RCC_CIR_LSIRDYF_Pos (0U)

#define	RCC_CIR_LSIRDYF_Msk (0x1UL << RCC_CIR_LSIRDYF_Pos)

#define	RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF_Msk

#define	RCC_CIR_LSERDYF_Pos (1U)

#define	RCC_CIR_LSERDYF_Msk (0x1UL << RCC_CIR_LSERDYF_Pos)

#define	RCC_CIR_LSERDYF RCC_CIR_LSERDYF_Msk

#define	RCC_CIR_HSIRDYF_Pos (2U)

#define	RCC_CIR_HSIRDYF_Msk (0x1UL << RCC_CIR_HSIRDYF_Pos)

#define	RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF_Msk

#define	RCC_CIR_HSERDYF_Pos (3U)

#define	RCC_CIR_HSERDYF_Msk (0x1UL << RCC_CIR_HSERDYF_Pos)

#define	RCC_CIR_HSERDYF RCC_CIR_HSERDYF_Msk

#define	RCC_CIR_PLLRDYF_Pos (4U)

#define	RCC_CIR_PLLRDYF_Msk (0x1UL << RCC_CIR_PLLRDYF_Pos)

#define	RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF_Msk

#define	RCC_CIR_CSSF_Pos (7U)

#define	RCC_CIR_CSSF_Msk (0x1UL << RCC_CIR_CSSF_Pos)

#define	RCC_CIR_CSSF RCC_CIR_CSSF_Msk

#define	RCC_CIR_LSIRDYIE_Pos (8U)

#define	RCC_CIR_LSIRDYIE_Msk (0x1UL << RCC_CIR_LSIRDYIE_Pos)

#define	RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE_Msk

#define	RCC_CIR_LSERDYIE_Pos (9U)

#define	RCC_CIR_LSERDYIE_Msk (0x1UL << RCC_CIR_LSERDYIE_Pos)

#define	RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE_Msk

#define	RCC_CIR_HSIRDYIE_Pos (10U)

#define	RCC_CIR_HSIRDYIE_Msk (0x1UL << RCC_CIR_HSIRDYIE_Pos)

#define	RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE_Msk

#define	RCC_CIR_HSERDYIE_Pos (11U)

#define	RCC_CIR_HSERDYIE_Msk (0x1UL << RCC_CIR_HSERDYIE_Pos)

#define	RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE_Msk

#define	RCC_CIR_PLLRDYIE_Pos (12U)

#define	RCC_CIR_PLLRDYIE_Msk (0x1UL << RCC_CIR_PLLRDYIE_Pos)

#define	RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE_Msk

#define	RCC_CIR_LSIRDYC_Pos (16U)

#define	RCC_CIR_LSIRDYC_Msk (0x1UL << RCC_CIR_LSIRDYC_Pos)

#define	RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC_Msk

#define	RCC_CIR_LSERDYC_Pos (17U)

#define	RCC_CIR_LSERDYC_Msk (0x1UL << RCC_CIR_LSERDYC_Pos)

#define	RCC_CIR_LSERDYC RCC_CIR_LSERDYC_Msk

#define	RCC_CIR_HSIRDYC_Pos (18U)

#define	RCC_CIR_HSIRDYC_Msk (0x1UL << RCC_CIR_HSIRDYC_Pos)

#define	RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC_Msk

#define	RCC_CIR_HSERDYC_Pos (19U)

#define	RCC_CIR_HSERDYC_Msk (0x1UL << RCC_CIR_HSERDYC_Pos)

#define	RCC_CIR_HSERDYC RCC_CIR_HSERDYC_Msk

#define	RCC_CIR_PLLRDYC_Pos (20U)

#define	RCC_CIR_PLLRDYC_Msk (0x1UL << RCC_CIR_PLLRDYC_Pos)

#define	RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC_Msk

#define	RCC_CIR_CSSC_Pos (23U)

#define	RCC_CIR_CSSC_Msk (0x1UL << RCC_CIR_CSSC_Pos)

#define	RCC_CIR_CSSC RCC_CIR_CSSC_Msk

#define	RCC_CIR_PLL2RDYF_Pos (5U)

#define	RCC_CIR_PLL2RDYF_Msk (0x1UL << RCC_CIR_PLL2RDYF_Pos)

#define	RCC_CIR_PLL2RDYF RCC_CIR_PLL2RDYF_Msk

#define	RCC_CIR_PLL3RDYF_Pos (6U)

#define	RCC_CIR_PLL3RDYF_Msk (0x1UL << RCC_CIR_PLL3RDYF_Pos)

#define	RCC_CIR_PLL3RDYF RCC_CIR_PLL3RDYF_Msk

#define	RCC_CIR_PLL2RDYIE_Pos (13U)

#define	RCC_CIR_PLL2RDYIE_Msk (0x1UL << RCC_CIR_PLL2RDYIE_Pos)

#define	RCC_CIR_PLL2RDYIE RCC_CIR_PLL2RDYIE_Msk

#define	RCC_CIR_PLL3RDYIE_Pos (14U)

#define	RCC_CIR_PLL3RDYIE_Msk (0x1UL << RCC_CIR_PLL3RDYIE_Pos)

#define	RCC_CIR_PLL3RDYIE RCC_CIR_PLL3RDYIE_Msk

#define	RCC_CIR_PLL2RDYC_Pos (21U)

#define	RCC_CIR_PLL2RDYC_Msk (0x1UL << RCC_CIR_PLL2RDYC_Pos)

#define	RCC_CIR_PLL2RDYC RCC_CIR_PLL2RDYC_Msk

#define	RCC_CIR_PLL3RDYC_Pos (22U)

#define	RCC_CIR_PLL3RDYC_Msk (0x1UL << RCC_CIR_PLL3RDYC_Pos)

#define	RCC_CIR_PLL3RDYC RCC_CIR_PLL3RDYC_Msk

#define	RCC_APB2RSTR_AFIORST_Pos (0U)

#define	RCC_APB2RSTR_AFIORST_Msk (0x1UL << RCC_APB2RSTR_AFIORST_Pos)

#define	RCC_APB2RSTR_AFIORST RCC_APB2RSTR_AFIORST_Msk

#define	RCC_APB2RSTR_IOPARST_Pos (2U)

#define	RCC_APB2RSTR_IOPARST_Msk (0x1UL << RCC_APB2RSTR_IOPARST_Pos)

#define	RCC_APB2RSTR_IOPARST RCC_APB2RSTR_IOPARST_Msk

#define	RCC_APB2RSTR_IOPBRST_Pos (3U)

#define	RCC_APB2RSTR_IOPBRST_Msk (0x1UL << RCC_APB2RSTR_IOPBRST_Pos)

#define	RCC_APB2RSTR_IOPBRST RCC_APB2RSTR_IOPBRST_Msk

#define	RCC_APB2RSTR_IOPCRST_Pos (4U)

#define	RCC_APB2RSTR_IOPCRST_Msk (0x1UL << RCC_APB2RSTR_IOPCRST_Pos)

#define	RCC_APB2RSTR_IOPCRST RCC_APB2RSTR_IOPCRST_Msk

#define	RCC_APB2RSTR_IOPDRST_Pos (5U)

#define	RCC_APB2RSTR_IOPDRST_Msk (0x1UL << RCC_APB2RSTR_IOPDRST_Pos)

#define	RCC_APB2RSTR_IOPDRST RCC_APB2RSTR_IOPDRST_Msk

#define	RCC_APB2RSTR_ADC1RST_Pos (9U)

#define	RCC_APB2RSTR_ADC1RST_Msk (0x1UL << RCC_APB2RSTR_ADC1RST_Pos)

#define	RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADC1RST_Msk

#define	RCC_APB2RSTR_ADC2RST_Pos (10U)

#define	RCC_APB2RSTR_ADC2RST_Msk (0x1UL << RCC_APB2RSTR_ADC2RST_Pos)

#define	RCC_APB2RSTR_ADC2RST RCC_APB2RSTR_ADC2RST_Msk

#define	RCC_APB2RSTR_TIM1RST_Pos (11U)

#define	RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos)

#define	RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk

#define	RCC_APB2RSTR_SPI1RST_Pos (12U)

#define	RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos)

#define	RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk

#define	RCC_APB2RSTR_USART1RST_Pos (14U)

#define	RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos)

#define	RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk

#define	RCC_APB2RSTR_IOPERST_Pos (6U)

#define	RCC_APB2RSTR_IOPERST_Msk (0x1UL << RCC_APB2RSTR_IOPERST_Pos)

#define	RCC_APB2RSTR_IOPERST RCC_APB2RSTR_IOPERST_Msk

#define	RCC_APB1RSTR_TIM2RST_Pos (0U)

#define	RCC_APB1RSTR_TIM2RST_Msk (0x1UL << RCC_APB1RSTR_TIM2RST_Pos)

#define	RCC_APB1RSTR_TIM2RST RCC_APB1RSTR_TIM2RST_Msk

#define	RCC_APB1RSTR_TIM3RST_Pos (1U)

#define	RCC_APB1RSTR_TIM3RST_Msk (0x1UL << RCC_APB1RSTR_TIM3RST_Pos)

#define	RCC_APB1RSTR_TIM3RST RCC_APB1RSTR_TIM3RST_Msk

#define	RCC_APB1RSTR_WWDGRST_Pos (11U)

#define	RCC_APB1RSTR_WWDGRST_Msk (0x1UL << RCC_APB1RSTR_WWDGRST_Pos)

#define	RCC_APB1RSTR_WWDGRST RCC_APB1RSTR_WWDGRST_Msk

#define	RCC_APB1RSTR_USART2RST_Pos (17U)

#define	RCC_APB1RSTR_USART2RST_Msk (0x1UL << RCC_APB1RSTR_USART2RST_Pos)

#define	RCC_APB1RSTR_USART2RST RCC_APB1RSTR_USART2RST_Msk

#define	RCC_APB1RSTR_I2C1RST_Pos (21U)

#define	RCC_APB1RSTR_I2C1RST_Msk (0x1UL << RCC_APB1RSTR_I2C1RST_Pos)

#define	RCC_APB1RSTR_I2C1RST RCC_APB1RSTR_I2C1RST_Msk

#define	RCC_APB1RSTR_CAN1RST_Pos (25U)

#define	RCC_APB1RSTR_CAN1RST_Msk (0x1UL << RCC_APB1RSTR_CAN1RST_Pos)

#define	RCC_APB1RSTR_CAN1RST RCC_APB1RSTR_CAN1RST_Msk

#define	RCC_APB1RSTR_BKPRST_Pos (27U)

#define	RCC_APB1RSTR_BKPRST_Msk (0x1UL << RCC_APB1RSTR_BKPRST_Pos)

#define	RCC_APB1RSTR_BKPRST RCC_APB1RSTR_BKPRST_Msk

#define	RCC_APB1RSTR_PWRRST_Pos (28U)

#define	RCC_APB1RSTR_PWRRST_Msk (0x1UL << RCC_APB1RSTR_PWRRST_Pos)

#define	RCC_APB1RSTR_PWRRST RCC_APB1RSTR_PWRRST_Msk

#define	RCC_APB1RSTR_TIM4RST_Pos (2U)

#define	RCC_APB1RSTR_TIM4RST_Msk (0x1UL << RCC_APB1RSTR_TIM4RST_Pos)

#define	RCC_APB1RSTR_TIM4RST RCC_APB1RSTR_TIM4RST_Msk

#define	RCC_APB1RSTR_SPI2RST_Pos (14U)

#define	RCC_APB1RSTR_SPI2RST_Msk (0x1UL << RCC_APB1RSTR_SPI2RST_Pos)

#define	RCC_APB1RSTR_SPI2RST RCC_APB1RSTR_SPI2RST_Msk

#define	RCC_APB1RSTR_USART3RST_Pos (18U)

#define	RCC_APB1RSTR_USART3RST_Msk (0x1UL << RCC_APB1RSTR_USART3RST_Pos)

#define	RCC_APB1RSTR_USART3RST RCC_APB1RSTR_USART3RST_Msk

#define	RCC_APB1RSTR_I2C2RST_Pos (22U)

#define	RCC_APB1RSTR_I2C2RST_Msk (0x1UL << RCC_APB1RSTR_I2C2RST_Pos)

#define	RCC_APB1RSTR_I2C2RST RCC_APB1RSTR_I2C2RST_Msk

#define	RCC_APB1RSTR_TIM5RST_Pos (3U)

#define	RCC_APB1RSTR_TIM5RST_Msk (0x1UL << RCC_APB1RSTR_TIM5RST_Pos)

#define	RCC_APB1RSTR_TIM5RST RCC_APB1RSTR_TIM5RST_Msk

#define	RCC_APB1RSTR_TIM6RST_Pos (4U)

#define	RCC_APB1RSTR_TIM6RST_Msk (0x1UL << RCC_APB1RSTR_TIM6RST_Pos)

#define	RCC_APB1RSTR_TIM6RST RCC_APB1RSTR_TIM6RST_Msk

#define	RCC_APB1RSTR_TIM7RST_Pos (5U)

#define	RCC_APB1RSTR_TIM7RST_Msk (0x1UL << RCC_APB1RSTR_TIM7RST_Pos)

#define	RCC_APB1RSTR_TIM7RST RCC_APB1RSTR_TIM7RST_Msk

#define	RCC_APB1RSTR_SPI3RST_Pos (15U)

#define	RCC_APB1RSTR_SPI3RST_Msk (0x1UL << RCC_APB1RSTR_SPI3RST_Pos)

#define	RCC_APB1RSTR_SPI3RST RCC_APB1RSTR_SPI3RST_Msk

#define	RCC_APB1RSTR_UART4RST_Pos (19U)

#define	RCC_APB1RSTR_UART4RST_Msk (0x1UL << RCC_APB1RSTR_UART4RST_Pos)

#define	RCC_APB1RSTR_UART4RST RCC_APB1RSTR_UART4RST_Msk

#define	RCC_APB1RSTR_UART5RST_Pos (20U)

#define	RCC_APB1RSTR_UART5RST_Msk (0x1UL << RCC_APB1RSTR_UART5RST_Pos)

#define	RCC_APB1RSTR_UART5RST RCC_APB1RSTR_UART5RST_Msk

#define	RCC_APB1RSTR_CAN2RST_Pos (26U)

#define	RCC_APB1RSTR_CAN2RST_Msk (0x1UL << RCC_APB1RSTR_CAN2RST_Pos)

#define	RCC_APB1RSTR_CAN2RST RCC_APB1RSTR_CAN2RST_Msk

#define	RCC_APB1RSTR_DACRST_Pos (29U)

#define	RCC_APB1RSTR_DACRST_Msk (0x1UL << RCC_APB1RSTR_DACRST_Pos)

#define	RCC_APB1RSTR_DACRST RCC_APB1RSTR_DACRST_Msk

#define	RCC_AHBENR_DMA1EN_Pos (0U)

#define	RCC_AHBENR_DMA1EN_Msk (0x1UL << RCC_AHBENR_DMA1EN_Pos)

#define	RCC_AHBENR_DMA1EN RCC_AHBENR_DMA1EN_Msk

#define	RCC_AHBENR_SRAMEN_Pos (2U)

#define	RCC_AHBENR_SRAMEN_Msk (0x1UL << RCC_AHBENR_SRAMEN_Pos)

#define	RCC_AHBENR_SRAMEN RCC_AHBENR_SRAMEN_Msk

#define	RCC_AHBENR_FLITFEN_Pos (4U)

#define	RCC_AHBENR_FLITFEN_Msk (0x1UL << RCC_AHBENR_FLITFEN_Pos)

#define	RCC_AHBENR_FLITFEN RCC_AHBENR_FLITFEN_Msk

#define	RCC_AHBENR_CRCEN_Pos (6U)

#define	RCC_AHBENR_CRCEN_Msk (0x1UL << RCC_AHBENR_CRCEN_Pos)

#define	RCC_AHBENR_CRCEN RCC_AHBENR_CRCEN_Msk

#define	RCC_AHBENR_DMA2EN_Pos (1U)

#define	RCC_AHBENR_DMA2EN_Msk (0x1UL << RCC_AHBENR_DMA2EN_Pos)

#define	RCC_AHBENR_DMA2EN RCC_AHBENR_DMA2EN_Msk

#define	RCC_AHBENR_OTGFSEN_Pos (12U)

#define	RCC_AHBENR_OTGFSEN_Msk (0x1UL << RCC_AHBENR_OTGFSEN_Pos)

#define	RCC_AHBENR_OTGFSEN RCC_AHBENR_OTGFSEN_Msk

#define	RCC_AHBENR_ETHMACEN_Pos (14U)

#define	RCC_AHBENR_ETHMACEN_Msk (0x1UL << RCC_AHBENR_ETHMACEN_Pos)

#define	RCC_AHBENR_ETHMACEN RCC_AHBENR_ETHMACEN_Msk

#define	RCC_AHBENR_ETHMACTXEN_Pos (15U)

#define	RCC_AHBENR_ETHMACTXEN_Msk (0x1UL << RCC_AHBENR_ETHMACTXEN_Pos)

#define	RCC_AHBENR_ETHMACTXEN RCC_AHBENR_ETHMACTXEN_Msk

#define	RCC_AHBENR_ETHMACRXEN_Pos (16U)

#define	RCC_AHBENR_ETHMACRXEN_Msk (0x1UL << RCC_AHBENR_ETHMACRXEN_Pos)

#define	RCC_AHBENR_ETHMACRXEN RCC_AHBENR_ETHMACRXEN_Msk

#define	RCC_APB2ENR_AFIOEN_Pos (0U)

#define	RCC_APB2ENR_AFIOEN_Msk (0x1UL << RCC_APB2ENR_AFIOEN_Pos)

#define	RCC_APB2ENR_AFIOEN RCC_APB2ENR_AFIOEN_Msk

#define	RCC_APB2ENR_IOPAEN_Pos (2U)

#define	RCC_APB2ENR_IOPAEN_Msk (0x1UL << RCC_APB2ENR_IOPAEN_Pos)

#define	RCC_APB2ENR_IOPAEN RCC_APB2ENR_IOPAEN_Msk

#define	RCC_APB2ENR_IOPBEN_Pos (3U)

#define	RCC_APB2ENR_IOPBEN_Msk (0x1UL << RCC_APB2ENR_IOPBEN_Pos)

#define	RCC_APB2ENR_IOPBEN RCC_APB2ENR_IOPBEN_Msk

#define	RCC_APB2ENR_IOPCEN_Pos (4U)

#define	RCC_APB2ENR_IOPCEN_Msk (0x1UL << RCC_APB2ENR_IOPCEN_Pos)

#define	RCC_APB2ENR_IOPCEN RCC_APB2ENR_IOPCEN_Msk

#define	RCC_APB2ENR_IOPDEN_Pos (5U)

#define	RCC_APB2ENR_IOPDEN_Msk (0x1UL << RCC_APB2ENR_IOPDEN_Pos)

#define	RCC_APB2ENR_IOPDEN RCC_APB2ENR_IOPDEN_Msk

#define	RCC_APB2ENR_ADC1EN_Pos (9U)

#define	RCC_APB2ENR_ADC1EN_Msk (0x1UL << RCC_APB2ENR_ADC1EN_Pos)

#define	RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADC1EN_Msk

#define	RCC_APB2ENR_ADC2EN_Pos (10U)

#define	RCC_APB2ENR_ADC2EN_Msk (0x1UL << RCC_APB2ENR_ADC2EN_Pos)

#define	RCC_APB2ENR_ADC2EN RCC_APB2ENR_ADC2EN_Msk

#define	RCC_APB2ENR_TIM1EN_Pos (11U)

#define	RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos)

#define	RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk

#define	RCC_APB2ENR_SPI1EN_Pos (12U)

#define	RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos)

#define	RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk

#define	RCC_APB2ENR_USART1EN_Pos (14U)

#define	RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos)

#define	RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk

#define	RCC_APB2ENR_IOPEEN_Pos (6U)

#define	RCC_APB2ENR_IOPEEN_Msk (0x1UL << RCC_APB2ENR_IOPEEN_Pos)

#define	RCC_APB2ENR_IOPEEN RCC_APB2ENR_IOPEEN_Msk

#define	RCC_APB1ENR_TIM2EN_Pos (0U)

#define	RCC_APB1ENR_TIM2EN_Msk (0x1UL << RCC_APB1ENR_TIM2EN_Pos)

#define	RCC_APB1ENR_TIM2EN RCC_APB1ENR_TIM2EN_Msk

#define	RCC_APB1ENR_TIM3EN_Pos (1U)

#define	RCC_APB1ENR_TIM3EN_Msk (0x1UL << RCC_APB1ENR_TIM3EN_Pos)

#define	RCC_APB1ENR_TIM3EN RCC_APB1ENR_TIM3EN_Msk

#define	RCC_APB1ENR_WWDGEN_Pos (11U)

#define	RCC_APB1ENR_WWDGEN_Msk (0x1UL << RCC_APB1ENR_WWDGEN_Pos)

#define	RCC_APB1ENR_WWDGEN RCC_APB1ENR_WWDGEN_Msk

#define	RCC_APB1ENR_USART2EN_Pos (17U)

#define	RCC_APB1ENR_USART2EN_Msk (0x1UL << RCC_APB1ENR_USART2EN_Pos)

#define	RCC_APB1ENR_USART2EN RCC_APB1ENR_USART2EN_Msk

#define	RCC_APB1ENR_I2C1EN_Pos (21U)

#define	RCC_APB1ENR_I2C1EN_Msk (0x1UL << RCC_APB1ENR_I2C1EN_Pos)

#define	RCC_APB1ENR_I2C1EN RCC_APB1ENR_I2C1EN_Msk

#define	RCC_APB1ENR_CAN1EN_Pos (25U)

#define	RCC_APB1ENR_CAN1EN_Msk (0x1UL << RCC_APB1ENR_CAN1EN_Pos)

#define	RCC_APB1ENR_CAN1EN RCC_APB1ENR_CAN1EN_Msk

#define	RCC_APB1ENR_BKPEN_Pos (27U)

#define	RCC_APB1ENR_BKPEN_Msk (0x1UL << RCC_APB1ENR_BKPEN_Pos)

#define	RCC_APB1ENR_BKPEN RCC_APB1ENR_BKPEN_Msk

#define	RCC_APB1ENR_PWREN_Pos (28U)

#define	RCC_APB1ENR_PWREN_Msk (0x1UL << RCC_APB1ENR_PWREN_Pos)

#define	RCC_APB1ENR_PWREN RCC_APB1ENR_PWREN_Msk

#define	RCC_APB1ENR_TIM4EN_Pos (2U)

#define	RCC_APB1ENR_TIM4EN_Msk (0x1UL << RCC_APB1ENR_TIM4EN_Pos)

#define	RCC_APB1ENR_TIM4EN RCC_APB1ENR_TIM4EN_Msk

#define	RCC_APB1ENR_SPI2EN_Pos (14U)

#define	RCC_APB1ENR_SPI2EN_Msk (0x1UL << RCC_APB1ENR_SPI2EN_Pos)

#define	RCC_APB1ENR_SPI2EN RCC_APB1ENR_SPI2EN_Msk

#define	RCC_APB1ENR_USART3EN_Pos (18U)

#define	RCC_APB1ENR_USART3EN_Msk (0x1UL << RCC_APB1ENR_USART3EN_Pos)

#define	RCC_APB1ENR_USART3EN RCC_APB1ENR_USART3EN_Msk

#define	RCC_APB1ENR_I2C2EN_Pos (22U)

#define	RCC_APB1ENR_I2C2EN_Msk (0x1UL << RCC_APB1ENR_I2C2EN_Pos)

#define	RCC_APB1ENR_I2C2EN RCC_APB1ENR_I2C2EN_Msk

#define	RCC_APB1ENR_TIM5EN_Pos (3U)

#define	RCC_APB1ENR_TIM5EN_Msk (0x1UL << RCC_APB1ENR_TIM5EN_Pos)

#define	RCC_APB1ENR_TIM5EN RCC_APB1ENR_TIM5EN_Msk

#define	RCC_APB1ENR_TIM6EN_Pos (4U)

#define	RCC_APB1ENR_TIM6EN_Msk (0x1UL << RCC_APB1ENR_TIM6EN_Pos)

#define	RCC_APB1ENR_TIM6EN RCC_APB1ENR_TIM6EN_Msk

#define	RCC_APB1ENR_TIM7EN_Pos (5U)

#define	RCC_APB1ENR_TIM7EN_Msk (0x1UL << RCC_APB1ENR_TIM7EN_Pos)

#define	RCC_APB1ENR_TIM7EN RCC_APB1ENR_TIM7EN_Msk

#define	RCC_APB1ENR_SPI3EN_Pos (15U)

#define	RCC_APB1ENR_SPI3EN_Msk (0x1UL << RCC_APB1ENR_SPI3EN_Pos)

#define	RCC_APB1ENR_SPI3EN RCC_APB1ENR_SPI3EN_Msk

#define	RCC_APB1ENR_UART4EN_Pos (19U)

#define	RCC_APB1ENR_UART4EN_Msk (0x1UL << RCC_APB1ENR_UART4EN_Pos)

#define	RCC_APB1ENR_UART4EN RCC_APB1ENR_UART4EN_Msk

#define	RCC_APB1ENR_UART5EN_Pos (20U)

#define	RCC_APB1ENR_UART5EN_Msk (0x1UL << RCC_APB1ENR_UART5EN_Pos)

#define	RCC_APB1ENR_UART5EN RCC_APB1ENR_UART5EN_Msk

#define	RCC_APB1ENR_CAN2EN_Pos (26U)

#define	RCC_APB1ENR_CAN2EN_Msk (0x1UL << RCC_APB1ENR_CAN2EN_Pos)

#define	RCC_APB1ENR_CAN2EN RCC_APB1ENR_CAN2EN_Msk

#define	RCC_APB1ENR_DACEN_Pos (29U)

#define	RCC_APB1ENR_DACEN_Msk (0x1UL << RCC_APB1ENR_DACEN_Pos)

#define	RCC_APB1ENR_DACEN RCC_APB1ENR_DACEN_Msk

#define	RCC_BDCR_LSEON_Pos (0U)

#define	RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos)

#define	RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk

#define	RCC_BDCR_LSERDY_Pos (1U)

#define	RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos)

#define	RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk

#define	RCC_BDCR_LSEBYP_Pos (2U)

#define	RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos)

#define	RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk

#define	RCC_BDCR_RTCSEL_Pos (8U)

#define	RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk

#define	RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos)

#define	RCC_BDCR_RTCSEL_NOCLOCK 0x00000000U

#define	RCC_BDCR_RTCSEL_LSE 0x00000100U

#define	RCC_BDCR_RTCSEL_LSI 0x00000200U

#define	RCC_BDCR_RTCSEL_HSE 0x00000300U

#define	RCC_BDCR_RTCEN_Pos (15U)

#define	RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos)

#define	RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk

#define	RCC_BDCR_BDRST_Pos (16U)

#define	RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos)

#define	RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk

#define	RCC_CSR_LSION_Pos (0U)

#define	RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos)

#define	RCC_CSR_LSION RCC_CSR_LSION_Msk

#define	RCC_CSR_LSIRDY_Pos (1U)

#define	RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos)

#define	RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk

#define	RCC_CSR_RMVF_Pos (24U)

#define	RCC_CSR_RMVF_Msk (0x1UL << RCC_CSR_RMVF_Pos)

#define	RCC_CSR_RMVF RCC_CSR_RMVF_Msk

#define	RCC_CSR_PINRSTF_Pos (26U)

#define	RCC_CSR_PINRSTF_Msk (0x1UL << RCC_CSR_PINRSTF_Pos)

#define	RCC_CSR_PINRSTF RCC_CSR_PINRSTF_Msk

#define	RCC_CSR_PORRSTF_Pos (27U)

#define	RCC_CSR_PORRSTF_Msk (0x1UL << RCC_CSR_PORRSTF_Pos)

#define	RCC_CSR_PORRSTF RCC_CSR_PORRSTF_Msk

#define	RCC_CSR_SFTRSTF_Pos (28U)

#define	RCC_CSR_SFTRSTF_Msk (0x1UL << RCC_CSR_SFTRSTF_Pos)

#define	RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF_Msk

#define	RCC_CSR_IWDGRSTF_Pos (29U)

#define	RCC_CSR_IWDGRSTF_Msk (0x1UL << RCC_CSR_IWDGRSTF_Pos)

#define	RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF_Msk

#define	RCC_CSR_WWDGRSTF_Pos (30U)

#define	RCC_CSR_WWDGRSTF_Msk (0x1UL << RCC_CSR_WWDGRSTF_Pos)

#define	RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF_Msk

#define	RCC_CSR_LPWRRSTF_Pos (31U)

#define	RCC_CSR_LPWRRSTF_Msk (0x1UL << RCC_CSR_LPWRRSTF_Pos)

#define	RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF_Msk

#define	RCC_AHBRSTR_OTGFSRST_Pos (12U)

#define	RCC_AHBRSTR_OTGFSRST_Msk (0x1UL << RCC_AHBRSTR_OTGFSRST_Pos)

#define	RCC_AHBRSTR_OTGFSRST RCC_AHBRSTR_OTGFSRST_Msk

#define	RCC_AHBRSTR_ETHMACRST_Pos (14U)

#define	RCC_AHBRSTR_ETHMACRST_Msk (0x1UL << RCC_AHBRSTR_ETHMACRST_Pos)

#define	RCC_AHBRSTR_ETHMACRST RCC_AHBRSTR_ETHMACRST_Msk

#define	RCC_CFGR2_PREDIV1_Pos (0U)

#define	RCC_CFGR2_PREDIV1_Msk (0xFUL << RCC_CFGR2_PREDIV1_Pos)

#define	RCC_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1_Msk

#define	RCC_CFGR2_PREDIV1_0 (0x1UL << RCC_CFGR2_PREDIV1_Pos)

#define	RCC_CFGR2_PREDIV1_1 (0x2UL << RCC_CFGR2_PREDIV1_Pos)

#define	RCC_CFGR2_PREDIV1_2 (0x4UL << RCC_CFGR2_PREDIV1_Pos)

#define	RCC_CFGR2_PREDIV1_3 (0x8UL << RCC_CFGR2_PREDIV1_Pos)

#define	RCC_CFGR2_PREDIV1_DIV1 0x00000000U

#define	RCC_CFGR2_PREDIV1_DIV2_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV2_Pos)

#define	RCC_CFGR2_PREDIV1_DIV2 RCC_CFGR2_PREDIV1_DIV2_Msk

#define	RCC_CFGR2_PREDIV1_DIV3_Pos (1U)

#define	RCC_CFGR2_PREDIV1_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV3_Pos)

#define	RCC_CFGR2_PREDIV1_DIV3 RCC_CFGR2_PREDIV1_DIV3_Msk

#define	RCC_CFGR2_PREDIV1_DIV4_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV4_Pos)

#define	RCC_CFGR2_PREDIV1_DIV4 RCC_CFGR2_PREDIV1_DIV4_Msk

#define	RCC_CFGR2_PREDIV1_DIV5_Pos (2U)

#define	RCC_CFGR2_PREDIV1_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV5_Pos)

#define	RCC_CFGR2_PREDIV1_DIV5 RCC_CFGR2_PREDIV1_DIV5_Msk

#define	RCC_CFGR2_PREDIV1_DIV6_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV6_Pos)

#define	RCC_CFGR2_PREDIV1_DIV6 RCC_CFGR2_PREDIV1_DIV6_Msk

#define	RCC_CFGR2_PREDIV1_DIV7_Pos (1U)

#define	RCC_CFGR2_PREDIV1_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV7_Pos)

#define	RCC_CFGR2_PREDIV1_DIV7 RCC_CFGR2_PREDIV1_DIV7_Msk

#define	RCC_CFGR2_PREDIV1_DIV8_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV8_Pos)

#define	RCC_CFGR2_PREDIV1_DIV8 RCC_CFGR2_PREDIV1_DIV8_Msk

#define	RCC_CFGR2_PREDIV1_DIV9_Pos (3U)

#define	RCC_CFGR2_PREDIV1_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV1_DIV9_Pos)

#define	RCC_CFGR2_PREDIV1_DIV9 RCC_CFGR2_PREDIV1_DIV9_Msk

#define	RCC_CFGR2_PREDIV1_DIV10_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV1_DIV10_Pos)

#define	RCC_CFGR2_PREDIV1_DIV10 RCC_CFGR2_PREDIV1_DIV10_Msk

#define	RCC_CFGR2_PREDIV1_DIV11_Pos (1U)

#define	RCC_CFGR2_PREDIV1_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV1_DIV11_Pos)

#define	RCC_CFGR2_PREDIV1_DIV11 RCC_CFGR2_PREDIV1_DIV11_Msk

#define	RCC_CFGR2_PREDIV1_DIV12_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV1_DIV12_Pos)

#define	RCC_CFGR2_PREDIV1_DIV12 RCC_CFGR2_PREDIV1_DIV12_Msk

#define	RCC_CFGR2_PREDIV1_DIV13_Pos (2U)

#define	RCC_CFGR2_PREDIV1_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV1_DIV13_Pos)

#define	RCC_CFGR2_PREDIV1_DIV13 RCC_CFGR2_PREDIV1_DIV13_Msk

#define	RCC_CFGR2_PREDIV1_DIV14_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV1_DIV14_Pos)

#define	RCC_CFGR2_PREDIV1_DIV14 RCC_CFGR2_PREDIV1_DIV14_Msk

#define	RCC_CFGR2_PREDIV1_DIV15_Pos (1U)

#define	RCC_CFGR2_PREDIV1_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV1_DIV15_Pos)

#define	RCC_CFGR2_PREDIV1_DIV15 RCC_CFGR2_PREDIV1_DIV15_Msk

#define	RCC_CFGR2_PREDIV1_DIV16_Pos (0U)

#define	RCC_CFGR2_PREDIV1_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV1_DIV16_Pos)

#define	RCC_CFGR2_PREDIV1_DIV16 RCC_CFGR2_PREDIV1_DIV16_Msk

#define	RCC_CFGR2_PREDIV2_Pos (4U)

#define	RCC_CFGR2_PREDIV2_Msk (0xFUL << RCC_CFGR2_PREDIV2_Pos)

#define	RCC_CFGR2_PREDIV2 RCC_CFGR2_PREDIV2_Msk

#define	RCC_CFGR2_PREDIV2_0 (0x1UL << RCC_CFGR2_PREDIV2_Pos)

#define	RCC_CFGR2_PREDIV2_1 (0x2UL << RCC_CFGR2_PREDIV2_Pos)

#define	RCC_CFGR2_PREDIV2_2 (0x4UL << RCC_CFGR2_PREDIV2_Pos)

#define	RCC_CFGR2_PREDIV2_3 (0x8UL << RCC_CFGR2_PREDIV2_Pos)

#define	RCC_CFGR2_PREDIV2_DIV1 0x00000000U

#define	RCC_CFGR2_PREDIV2_DIV2_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV2_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV2_Pos)

#define	RCC_CFGR2_PREDIV2_DIV2 RCC_CFGR2_PREDIV2_DIV2_Msk

#define	RCC_CFGR2_PREDIV2_DIV3_Pos (5U)

#define	RCC_CFGR2_PREDIV2_DIV3_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV3_Pos)

#define	RCC_CFGR2_PREDIV2_DIV3 RCC_CFGR2_PREDIV2_DIV3_Msk

#define	RCC_CFGR2_PREDIV2_DIV4_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV4_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV4_Pos)

#define	RCC_CFGR2_PREDIV2_DIV4 RCC_CFGR2_PREDIV2_DIV4_Msk

#define	RCC_CFGR2_PREDIV2_DIV5_Pos (6U)

#define	RCC_CFGR2_PREDIV2_DIV5_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV5_Pos)

#define	RCC_CFGR2_PREDIV2_DIV5 RCC_CFGR2_PREDIV2_DIV5_Msk

#define	RCC_CFGR2_PREDIV2_DIV6_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV6_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV6_Pos)

#define	RCC_CFGR2_PREDIV2_DIV6 RCC_CFGR2_PREDIV2_DIV6_Msk

#define	RCC_CFGR2_PREDIV2_DIV7_Pos (5U)

#define	RCC_CFGR2_PREDIV2_DIV7_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV7_Pos)

#define	RCC_CFGR2_PREDIV2_DIV7 RCC_CFGR2_PREDIV2_DIV7_Msk

#define	RCC_CFGR2_PREDIV2_DIV8_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV8_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV8_Pos)

#define	RCC_CFGR2_PREDIV2_DIV8 RCC_CFGR2_PREDIV2_DIV8_Msk

#define	RCC_CFGR2_PREDIV2_DIV9_Pos (7U)

#define	RCC_CFGR2_PREDIV2_DIV9_Msk (0x1UL << RCC_CFGR2_PREDIV2_DIV9_Pos)

#define	RCC_CFGR2_PREDIV2_DIV9 RCC_CFGR2_PREDIV2_DIV9_Msk

#define	RCC_CFGR2_PREDIV2_DIV10_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV10_Msk (0x9UL << RCC_CFGR2_PREDIV2_DIV10_Pos)

#define	RCC_CFGR2_PREDIV2_DIV10 RCC_CFGR2_PREDIV2_DIV10_Msk

#define	RCC_CFGR2_PREDIV2_DIV11_Pos (5U)

#define	RCC_CFGR2_PREDIV2_DIV11_Msk (0x5UL << RCC_CFGR2_PREDIV2_DIV11_Pos)

#define	RCC_CFGR2_PREDIV2_DIV11 RCC_CFGR2_PREDIV2_DIV11_Msk

#define	RCC_CFGR2_PREDIV2_DIV12_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV12_Msk (0xBUL << RCC_CFGR2_PREDIV2_DIV12_Pos)

#define	RCC_CFGR2_PREDIV2_DIV12 RCC_CFGR2_PREDIV2_DIV12_Msk

#define	RCC_CFGR2_PREDIV2_DIV13_Pos (6U)

#define	RCC_CFGR2_PREDIV2_DIV13_Msk (0x3UL << RCC_CFGR2_PREDIV2_DIV13_Pos)

#define	RCC_CFGR2_PREDIV2_DIV13 RCC_CFGR2_PREDIV2_DIV13_Msk

#define	RCC_CFGR2_PREDIV2_DIV14_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV14_Msk (0xDUL << RCC_CFGR2_PREDIV2_DIV14_Pos)

#define	RCC_CFGR2_PREDIV2_DIV14 RCC_CFGR2_PREDIV2_DIV14_Msk

#define	RCC_CFGR2_PREDIV2_DIV15_Pos (5U)

#define	RCC_CFGR2_PREDIV2_DIV15_Msk (0x7UL << RCC_CFGR2_PREDIV2_DIV15_Pos)

#define	RCC_CFGR2_PREDIV2_DIV15 RCC_CFGR2_PREDIV2_DIV15_Msk

#define	RCC_CFGR2_PREDIV2_DIV16_Pos (4U)

#define	RCC_CFGR2_PREDIV2_DIV16_Msk (0xFUL << RCC_CFGR2_PREDIV2_DIV16_Pos)

#define	RCC_CFGR2_PREDIV2_DIV16 RCC_CFGR2_PREDIV2_DIV16_Msk

#define	RCC_CFGR2_PLL2MUL_Pos (8U)

#define	RCC_CFGR2_PLL2MUL_Msk (0xFUL << RCC_CFGR2_PLL2MUL_Pos)

#define	RCC_CFGR2_PLL2MUL RCC_CFGR2_PLL2MUL_Msk

#define	RCC_CFGR2_PLL2MUL_0 (0x1UL << RCC_CFGR2_PLL2MUL_Pos)

#define	RCC_CFGR2_PLL2MUL_1 (0x2UL << RCC_CFGR2_PLL2MUL_Pos)

#define	RCC_CFGR2_PLL2MUL_2 (0x4UL << RCC_CFGR2_PLL2MUL_Pos)

#define	RCC_CFGR2_PLL2MUL_3 (0x8UL << RCC_CFGR2_PLL2MUL_Pos)

#define	RCC_CFGR2_PLL2MUL8_Pos (9U)

#define	RCC_CFGR2_PLL2MUL8_Msk (0x3UL << RCC_CFGR2_PLL2MUL8_Pos)

#define	RCC_CFGR2_PLL2MUL8 RCC_CFGR2_PLL2MUL8_Msk

#define	RCC_CFGR2_PLL2MUL9_Pos (8U)

#define	RCC_CFGR2_PLL2MUL9_Msk (0x7UL << RCC_CFGR2_PLL2MUL9_Pos)

#define	RCC_CFGR2_PLL2MUL9 RCC_CFGR2_PLL2MUL9_Msk

#define	RCC_CFGR2_PLL2MUL10_Pos (11U)

#define	RCC_CFGR2_PLL2MUL10_Msk (0x1UL << RCC_CFGR2_PLL2MUL10_Pos)

#define	RCC_CFGR2_PLL2MUL10 RCC_CFGR2_PLL2MUL10_Msk

#define	RCC_CFGR2_PLL2MUL11_Pos (8U)

#define	RCC_CFGR2_PLL2MUL11_Msk (0x9UL << RCC_CFGR2_PLL2MUL11_Pos)

#define	RCC_CFGR2_PLL2MUL11 RCC_CFGR2_PLL2MUL11_Msk

#define	RCC_CFGR2_PLL2MUL12_Pos (9U)

#define	RCC_CFGR2_PLL2MUL12_Msk (0x5UL << RCC_CFGR2_PLL2MUL12_Pos)

#define	RCC_CFGR2_PLL2MUL12 RCC_CFGR2_PLL2MUL12_Msk

#define	RCC_CFGR2_PLL2MUL13_Pos (8U)

#define	RCC_CFGR2_PLL2MUL13_Msk (0xBUL << RCC_CFGR2_PLL2MUL13_Pos)

#define	RCC_CFGR2_PLL2MUL13 RCC_CFGR2_PLL2MUL13_Msk

#define	RCC_CFGR2_PLL2MUL14_Pos (10U)

#define	RCC_CFGR2_PLL2MUL14_Msk (0x3UL << RCC_CFGR2_PLL2MUL14_Pos)

#define	RCC_CFGR2_PLL2MUL14 RCC_CFGR2_PLL2MUL14_Msk

#define	RCC_CFGR2_PLL2MUL16_Pos (9U)

#define	RCC_CFGR2_PLL2MUL16_Msk (0x7UL << RCC_CFGR2_PLL2MUL16_Pos)

#define	RCC_CFGR2_PLL2MUL16 RCC_CFGR2_PLL2MUL16_Msk

#define	RCC_CFGR2_PLL2MUL20_Pos (8U)

#define	RCC_CFGR2_PLL2MUL20_Msk (0xFUL << RCC_CFGR2_PLL2MUL20_Pos)

#define	RCC_CFGR2_PLL2MUL20 RCC_CFGR2_PLL2MUL20_Msk

#define	RCC_CFGR2_PLL3MUL_Pos (12U)

#define	RCC_CFGR2_PLL3MUL_Msk (0xFUL << RCC_CFGR2_PLL3MUL_Pos)

#define	RCC_CFGR2_PLL3MUL RCC_CFGR2_PLL3MUL_Msk

#define	RCC_CFGR2_PLL3MUL_0 (0x1UL << RCC_CFGR2_PLL3MUL_Pos)

#define	RCC_CFGR2_PLL3MUL_1 (0x2UL << RCC_CFGR2_PLL3MUL_Pos)

#define	RCC_CFGR2_PLL3MUL_2 (0x4UL << RCC_CFGR2_PLL3MUL_Pos)

#define	RCC_CFGR2_PLL3MUL_3 (0x8UL << RCC_CFGR2_PLL3MUL_Pos)

#define	RCC_CFGR2_PLL3MUL8_Pos (13U)

#define	RCC_CFGR2_PLL3MUL8_Msk (0x3UL << RCC_CFGR2_PLL3MUL8_Pos)

#define	RCC_CFGR2_PLL3MUL8 RCC_CFGR2_PLL3MUL8_Msk

#define	RCC_CFGR2_PLL3MUL9_Pos (12U)

#define	RCC_CFGR2_PLL3MUL9_Msk (0x7UL << RCC_CFGR2_PLL3MUL9_Pos)

#define	RCC_CFGR2_PLL3MUL9 RCC_CFGR2_PLL3MUL9_Msk

#define	RCC_CFGR2_PLL3MUL10_Pos (15U)

#define	RCC_CFGR2_PLL3MUL10_Msk (0x1UL << RCC_CFGR2_PLL3MUL10_Pos)

#define	RCC_CFGR2_PLL3MUL10 RCC_CFGR2_PLL3MUL10_Msk

#define	RCC_CFGR2_PLL3MUL11_Pos (12U)

#define	RCC_CFGR2_PLL3MUL11_Msk (0x9UL << RCC_CFGR2_PLL3MUL11_Pos)

#define	RCC_CFGR2_PLL3MUL11 RCC_CFGR2_PLL3MUL11_Msk

#define	RCC_CFGR2_PLL3MUL12_Pos (13U)

#define	RCC_CFGR2_PLL3MUL12_Msk (0x5UL << RCC_CFGR2_PLL3MUL12_Pos)

#define	RCC_CFGR2_PLL3MUL12 RCC_CFGR2_PLL3MUL12_Msk

#define	RCC_CFGR2_PLL3MUL13_Pos (12U)

#define	RCC_CFGR2_PLL3MUL13_Msk (0xBUL << RCC_CFGR2_PLL3MUL13_Pos)

#define	RCC_CFGR2_PLL3MUL13 RCC_CFGR2_PLL3MUL13_Msk

#define	RCC_CFGR2_PLL3MUL14_Pos (14U)

#define	RCC_CFGR2_PLL3MUL14_Msk (0x3UL << RCC_CFGR2_PLL3MUL14_Pos)

#define	RCC_CFGR2_PLL3MUL14 RCC_CFGR2_PLL3MUL14_Msk

#define	RCC_CFGR2_PLL3MUL16_Pos (13U)

#define	RCC_CFGR2_PLL3MUL16_Msk (0x7UL << RCC_CFGR2_PLL3MUL16_Pos)

#define	RCC_CFGR2_PLL3MUL16 RCC_CFGR2_PLL3MUL16_Msk

#define	RCC_CFGR2_PLL3MUL20_Pos (12U)

#define	RCC_CFGR2_PLL3MUL20_Msk (0xFUL << RCC_CFGR2_PLL3MUL20_Pos)

#define	RCC_CFGR2_PLL3MUL20 RCC_CFGR2_PLL3MUL20_Msk

#define	RCC_CFGR2_PREDIV1SRC_Pos (16U)

#define	RCC_CFGR2_PREDIV1SRC_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_Pos)

#define	RCC_CFGR2_PREDIV1SRC RCC_CFGR2_PREDIV1SRC_Msk

#define	RCC_CFGR2_PREDIV1SRC_PLL2_Pos (16U)

#define	RCC_CFGR2_PREDIV1SRC_PLL2_Msk (0x1UL << RCC_CFGR2_PREDIV1SRC_PLL2_Pos)

#define	RCC_CFGR2_PREDIV1SRC_PLL2 RCC_CFGR2_PREDIV1SRC_PLL2_Msk

#define	RCC_CFGR2_PREDIV1SRC_HSE 0x00000000U

#define	RCC_CFGR2_I2S2SRC_Pos (17U)

#define	RCC_CFGR2_I2S2SRC_Msk (0x1UL << RCC_CFGR2_I2S2SRC_Pos)

#define	RCC_CFGR2_I2S2SRC RCC_CFGR2_I2S2SRC_Msk

#define	RCC_CFGR2_I2S3SRC_Pos (18U)

#define	RCC_CFGR2_I2S3SRC_Msk (0x1UL << RCC_CFGR2_I2S3SRC_Pos)

#define	RCC_CFGR2_I2S3SRC RCC_CFGR2_I2S3SRC_Msk

#define	GPIO_CRL_MODE_Pos (0U)

#define	GPIO_CRL_MODE_Msk (0x33333333UL << GPIO_CRL_MODE_Pos)

#define	GPIO_CRL_MODE GPIO_CRL_MODE_Msk

#define	GPIO_CRL_MODE0_Pos (0U)

#define	GPIO_CRL_MODE0_Msk (0x3UL << GPIO_CRL_MODE0_Pos)

#define	GPIO_CRL_MODE0 GPIO_CRL_MODE0_Msk

#define	GPIO_CRL_MODE0_0 (0x1UL << GPIO_CRL_MODE0_Pos)

#define	GPIO_CRL_MODE0_1 (0x2UL << GPIO_CRL_MODE0_Pos)

#define	GPIO_CRL_MODE1_Pos (4U)

#define	GPIO_CRL_MODE1_Msk (0x3UL << GPIO_CRL_MODE1_Pos)

#define	GPIO_CRL_MODE1 GPIO_CRL_MODE1_Msk

#define	GPIO_CRL_MODE1_0 (0x1UL << GPIO_CRL_MODE1_Pos)

#define	GPIO_CRL_MODE1_1 (0x2UL << GPIO_CRL_MODE1_Pos)

#define	GPIO_CRL_MODE2_Pos (8U)

#define	GPIO_CRL_MODE2_Msk (0x3UL << GPIO_CRL_MODE2_Pos)

#define	GPIO_CRL_MODE2 GPIO_CRL_MODE2_Msk

#define	GPIO_CRL_MODE2_0 (0x1UL << GPIO_CRL_MODE2_Pos)

#define	GPIO_CRL_MODE2_1 (0x2UL << GPIO_CRL_MODE2_Pos)

#define	GPIO_CRL_MODE3_Pos (12U)

#define	GPIO_CRL_MODE3_Msk (0x3UL << GPIO_CRL_MODE3_Pos)

#define	GPIO_CRL_MODE3 GPIO_CRL_MODE3_Msk

#define	GPIO_CRL_MODE3_0 (0x1UL << GPIO_CRL_MODE3_Pos)

#define	GPIO_CRL_MODE3_1 (0x2UL << GPIO_CRL_MODE3_Pos)

#define	GPIO_CRL_MODE4_Pos (16U)

#define	GPIO_CRL_MODE4_Msk (0x3UL << GPIO_CRL_MODE4_Pos)

#define	GPIO_CRL_MODE4 GPIO_CRL_MODE4_Msk

#define	GPIO_CRL_MODE4_0 (0x1UL << GPIO_CRL_MODE4_Pos)

#define	GPIO_CRL_MODE4_1 (0x2UL << GPIO_CRL_MODE4_Pos)

#define	GPIO_CRL_MODE5_Pos (20U)

#define	GPIO_CRL_MODE5_Msk (0x3UL << GPIO_CRL_MODE5_Pos)

#define	GPIO_CRL_MODE5 GPIO_CRL_MODE5_Msk

#define	GPIO_CRL_MODE5_0 (0x1UL << GPIO_CRL_MODE5_Pos)

#define	GPIO_CRL_MODE5_1 (0x2UL << GPIO_CRL_MODE5_Pos)

#define	GPIO_CRL_MODE6_Pos (24U)

#define	GPIO_CRL_MODE6_Msk (0x3UL << GPIO_CRL_MODE6_Pos)

#define	GPIO_CRL_MODE6 GPIO_CRL_MODE6_Msk

#define	GPIO_CRL_MODE6_0 (0x1UL << GPIO_CRL_MODE6_Pos)

#define	GPIO_CRL_MODE6_1 (0x2UL << GPIO_CRL_MODE6_Pos)

#define	GPIO_CRL_MODE7_Pos (28U)

#define	GPIO_CRL_MODE7_Msk (0x3UL << GPIO_CRL_MODE7_Pos)

#define	GPIO_CRL_MODE7 GPIO_CRL_MODE7_Msk

#define	GPIO_CRL_MODE7_0 (0x1UL << GPIO_CRL_MODE7_Pos)

#define	GPIO_CRL_MODE7_1 (0x2UL << GPIO_CRL_MODE7_Pos)

#define	GPIO_CRL_CNF_Pos (2U)

#define	GPIO_CRL_CNF_Msk (0x33333333UL << GPIO_CRL_CNF_Pos)

#define	GPIO_CRL_CNF GPIO_CRL_CNF_Msk

#define	GPIO_CRL_CNF0_Pos (2U)

#define	GPIO_CRL_CNF0_Msk (0x3UL << GPIO_CRL_CNF0_Pos)

#define	GPIO_CRL_CNF0 GPIO_CRL_CNF0_Msk

#define	GPIO_CRL_CNF0_0 (0x1UL << GPIO_CRL_CNF0_Pos)

#define	GPIO_CRL_CNF0_1 (0x2UL << GPIO_CRL_CNF0_Pos)

#define	GPIO_CRL_CNF1_Pos (6U)

#define	GPIO_CRL_CNF1_Msk (0x3UL << GPIO_CRL_CNF1_Pos)

#define	GPIO_CRL_CNF1 GPIO_CRL_CNF1_Msk

#define	GPIO_CRL_CNF1_0 (0x1UL << GPIO_CRL_CNF1_Pos)

#define	GPIO_CRL_CNF1_1 (0x2UL << GPIO_CRL_CNF1_Pos)

#define	GPIO_CRL_CNF2_Pos (10U)

#define	GPIO_CRL_CNF2_Msk (0x3UL << GPIO_CRL_CNF2_Pos)

#define	GPIO_CRL_CNF2 GPIO_CRL_CNF2_Msk

#define	GPIO_CRL_CNF2_0 (0x1UL << GPIO_CRL_CNF2_Pos)

#define	GPIO_CRL_CNF2_1 (0x2UL << GPIO_CRL_CNF2_Pos)

#define	GPIO_CRL_CNF3_Pos (14U)

#define	GPIO_CRL_CNF3_Msk (0x3UL << GPIO_CRL_CNF3_Pos)

#define	GPIO_CRL_CNF3 GPIO_CRL_CNF3_Msk

#define	GPIO_CRL_CNF3_0 (0x1UL << GPIO_CRL_CNF3_Pos)

#define	GPIO_CRL_CNF3_1 (0x2UL << GPIO_CRL_CNF3_Pos)

#define	GPIO_CRL_CNF4_Pos (18U)

#define	GPIO_CRL_CNF4_Msk (0x3UL << GPIO_CRL_CNF4_Pos)

#define	GPIO_CRL_CNF4 GPIO_CRL_CNF4_Msk

#define	GPIO_CRL_CNF4_0 (0x1UL << GPIO_CRL_CNF4_Pos)

#define	GPIO_CRL_CNF4_1 (0x2UL << GPIO_CRL_CNF4_Pos)

#define	GPIO_CRL_CNF5_Pos (22U)

#define	GPIO_CRL_CNF5_Msk (0x3UL << GPIO_CRL_CNF5_Pos)

#define	GPIO_CRL_CNF5 GPIO_CRL_CNF5_Msk

#define	GPIO_CRL_CNF5_0 (0x1UL << GPIO_CRL_CNF5_Pos)

#define	GPIO_CRL_CNF5_1 (0x2UL << GPIO_CRL_CNF5_Pos)

#define	GPIO_CRL_CNF6_Pos (26U)

#define	GPIO_CRL_CNF6_Msk (0x3UL << GPIO_CRL_CNF6_Pos)

#define	GPIO_CRL_CNF6 GPIO_CRL_CNF6_Msk

#define	GPIO_CRL_CNF6_0 (0x1UL << GPIO_CRL_CNF6_Pos)

#define	GPIO_CRL_CNF6_1 (0x2UL << GPIO_CRL_CNF6_Pos)

#define	GPIO_CRL_CNF7_Pos (30U)

#define	GPIO_CRL_CNF7_Msk (0x3UL << GPIO_CRL_CNF7_Pos)

#define	GPIO_CRL_CNF7 GPIO_CRL_CNF7_Msk

#define	GPIO_CRL_CNF7_0 (0x1UL << GPIO_CRL_CNF7_Pos)

#define	GPIO_CRL_CNF7_1 (0x2UL << GPIO_CRL_CNF7_Pos)

#define	GPIO_CRH_MODE_Pos (0U)

#define	GPIO_CRH_MODE_Msk (0x33333333UL << GPIO_CRH_MODE_Pos)

#define	GPIO_CRH_MODE GPIO_CRH_MODE_Msk

#define	GPIO_CRH_MODE8_Pos (0U)

#define	GPIO_CRH_MODE8_Msk (0x3UL << GPIO_CRH_MODE8_Pos)

#define	GPIO_CRH_MODE8 GPIO_CRH_MODE8_Msk

#define	GPIO_CRH_MODE8_0 (0x1UL << GPIO_CRH_MODE8_Pos)

#define	GPIO_CRH_MODE8_1 (0x2UL << GPIO_CRH_MODE8_Pos)

#define	GPIO_CRH_MODE9_Pos (4U)

#define	GPIO_CRH_MODE9_Msk (0x3UL << GPIO_CRH_MODE9_Pos)

#define	GPIO_CRH_MODE9 GPIO_CRH_MODE9_Msk

#define	GPIO_CRH_MODE9_0 (0x1UL << GPIO_CRH_MODE9_Pos)

#define	GPIO_CRH_MODE9_1 (0x2UL << GPIO_CRH_MODE9_Pos)

#define	GPIO_CRH_MODE10_Pos (8U)

#define	GPIO_CRH_MODE10_Msk (0x3UL << GPIO_CRH_MODE10_Pos)

#define	GPIO_CRH_MODE10 GPIO_CRH_MODE10_Msk

#define	GPIO_CRH_MODE10_0 (0x1UL << GPIO_CRH_MODE10_Pos)

#define	GPIO_CRH_MODE10_1 (0x2UL << GPIO_CRH_MODE10_Pos)

#define	GPIO_CRH_MODE11_Pos (12U)

#define	GPIO_CRH_MODE11_Msk (0x3UL << GPIO_CRH_MODE11_Pos)

#define	GPIO_CRH_MODE11 GPIO_CRH_MODE11_Msk

#define	GPIO_CRH_MODE11_0 (0x1UL << GPIO_CRH_MODE11_Pos)

#define	GPIO_CRH_MODE11_1 (0x2UL << GPIO_CRH_MODE11_Pos)

#define	GPIO_CRH_MODE12_Pos (16U)

#define	GPIO_CRH_MODE12_Msk (0x3UL << GPIO_CRH_MODE12_Pos)

#define	GPIO_CRH_MODE12 GPIO_CRH_MODE12_Msk

#define	GPIO_CRH_MODE12_0 (0x1UL << GPIO_CRH_MODE12_Pos)

#define	GPIO_CRH_MODE12_1 (0x2UL << GPIO_CRH_MODE12_Pos)

#define	GPIO_CRH_MODE13_Pos (20U)

#define	GPIO_CRH_MODE13_Msk (0x3UL << GPIO_CRH_MODE13_Pos)

#define	GPIO_CRH_MODE13 GPIO_CRH_MODE13_Msk

#define	GPIO_CRH_MODE13_0 (0x1UL << GPIO_CRH_MODE13_Pos)

#define	GPIO_CRH_MODE13_1 (0x2UL << GPIO_CRH_MODE13_Pos)

#define	GPIO_CRH_MODE14_Pos (24U)

#define	GPIO_CRH_MODE14_Msk (0x3UL << GPIO_CRH_MODE14_Pos)

#define	GPIO_CRH_MODE14 GPIO_CRH_MODE14_Msk

#define	GPIO_CRH_MODE14_0 (0x1UL << GPIO_CRH_MODE14_Pos)

#define	GPIO_CRH_MODE14_1 (0x2UL << GPIO_CRH_MODE14_Pos)

#define	GPIO_CRH_MODE15_Pos (28U)

#define	GPIO_CRH_MODE15_Msk (0x3UL << GPIO_CRH_MODE15_Pos)

#define	GPIO_CRH_MODE15 GPIO_CRH_MODE15_Msk

#define	GPIO_CRH_MODE15_0 (0x1UL << GPIO_CRH_MODE15_Pos)

#define	GPIO_CRH_MODE15_1 (0x2UL << GPIO_CRH_MODE15_Pos)

#define	GPIO_CRH_CNF_Pos (2U)

#define	GPIO_CRH_CNF_Msk (0x33333333UL << GPIO_CRH_CNF_Pos)

#define	GPIO_CRH_CNF GPIO_CRH_CNF_Msk

#define	GPIO_CRH_CNF8_Pos (2U)

#define	GPIO_CRH_CNF8_Msk (0x3UL << GPIO_CRH_CNF8_Pos)

#define	GPIO_CRH_CNF8 GPIO_CRH_CNF8_Msk

#define	GPIO_CRH_CNF8_0 (0x1UL << GPIO_CRH_CNF8_Pos)

#define	GPIO_CRH_CNF8_1 (0x2UL << GPIO_CRH_CNF8_Pos)

#define	GPIO_CRH_CNF9_Pos (6U)

#define	GPIO_CRH_CNF9_Msk (0x3UL << GPIO_CRH_CNF9_Pos)

#define	GPIO_CRH_CNF9 GPIO_CRH_CNF9_Msk

#define	GPIO_CRH_CNF9_0 (0x1UL << GPIO_CRH_CNF9_Pos)

#define	GPIO_CRH_CNF9_1 (0x2UL << GPIO_CRH_CNF9_Pos)

#define	GPIO_CRH_CNF10_Pos (10U)

#define	GPIO_CRH_CNF10_Msk (0x3UL << GPIO_CRH_CNF10_Pos)

#define	GPIO_CRH_CNF10 GPIO_CRH_CNF10_Msk

#define	GPIO_CRH_CNF10_0 (0x1UL << GPIO_CRH_CNF10_Pos)

#define	GPIO_CRH_CNF10_1 (0x2UL << GPIO_CRH_CNF10_Pos)

#define	GPIO_CRH_CNF11_Pos (14U)

#define	GPIO_CRH_CNF11_Msk (0x3UL << GPIO_CRH_CNF11_Pos)

#define	GPIO_CRH_CNF11 GPIO_CRH_CNF11_Msk

#define	GPIO_CRH_CNF11_0 (0x1UL << GPIO_CRH_CNF11_Pos)

#define	GPIO_CRH_CNF11_1 (0x2UL << GPIO_CRH_CNF11_Pos)

#define	GPIO_CRH_CNF12_Pos (18U)

#define	GPIO_CRH_CNF12_Msk (0x3UL << GPIO_CRH_CNF12_Pos)

#define	GPIO_CRH_CNF12 GPIO_CRH_CNF12_Msk

#define	GPIO_CRH_CNF12_0 (0x1UL << GPIO_CRH_CNF12_Pos)

#define	GPIO_CRH_CNF12_1 (0x2UL << GPIO_CRH_CNF12_Pos)

#define	GPIO_CRH_CNF13_Pos (22U)

#define	GPIO_CRH_CNF13_Msk (0x3UL << GPIO_CRH_CNF13_Pos)

#define	GPIO_CRH_CNF13 GPIO_CRH_CNF13_Msk

#define	GPIO_CRH_CNF13_0 (0x1UL << GPIO_CRH_CNF13_Pos)

#define	GPIO_CRH_CNF13_1 (0x2UL << GPIO_CRH_CNF13_Pos)

#define	GPIO_CRH_CNF14_Pos (26U)

#define	GPIO_CRH_CNF14_Msk (0x3UL << GPIO_CRH_CNF14_Pos)

#define	GPIO_CRH_CNF14 GPIO_CRH_CNF14_Msk

#define	GPIO_CRH_CNF14_0 (0x1UL << GPIO_CRH_CNF14_Pos)

#define	GPIO_CRH_CNF14_1 (0x2UL << GPIO_CRH_CNF14_Pos)

#define	GPIO_CRH_CNF15_Pos (30U)

#define	GPIO_CRH_CNF15_Msk (0x3UL << GPIO_CRH_CNF15_Pos)

#define	GPIO_CRH_CNF15 GPIO_CRH_CNF15_Msk

#define	GPIO_CRH_CNF15_0 (0x1UL << GPIO_CRH_CNF15_Pos)

#define	GPIO_CRH_CNF15_1 (0x2UL << GPIO_CRH_CNF15_Pos)

#define	GPIO_IDR_IDR0_Pos (0U)

#define	GPIO_IDR_IDR0_Msk (0x1UL << GPIO_IDR_IDR0_Pos)

#define	GPIO_IDR_IDR0 GPIO_IDR_IDR0_Msk

#define	GPIO_IDR_IDR1_Pos (1U)

#define	GPIO_IDR_IDR1_Msk (0x1UL << GPIO_IDR_IDR1_Pos)

#define	GPIO_IDR_IDR1 GPIO_IDR_IDR1_Msk

#define	GPIO_IDR_IDR2_Pos (2U)

#define	GPIO_IDR_IDR2_Msk (0x1UL << GPIO_IDR_IDR2_Pos)

#define	GPIO_IDR_IDR2 GPIO_IDR_IDR2_Msk

#define	GPIO_IDR_IDR3_Pos (3U)

#define	GPIO_IDR_IDR3_Msk (0x1UL << GPIO_IDR_IDR3_Pos)

#define	GPIO_IDR_IDR3 GPIO_IDR_IDR3_Msk

#define	GPIO_IDR_IDR4_Pos (4U)

#define	GPIO_IDR_IDR4_Msk (0x1UL << GPIO_IDR_IDR4_Pos)

#define	GPIO_IDR_IDR4 GPIO_IDR_IDR4_Msk

#define	GPIO_IDR_IDR5_Pos (5U)

#define	GPIO_IDR_IDR5_Msk (0x1UL << GPIO_IDR_IDR5_Pos)

#define	GPIO_IDR_IDR5 GPIO_IDR_IDR5_Msk

#define	GPIO_IDR_IDR6_Pos (6U)

#define	GPIO_IDR_IDR6_Msk (0x1UL << GPIO_IDR_IDR6_Pos)

#define	GPIO_IDR_IDR6 GPIO_IDR_IDR6_Msk

#define	GPIO_IDR_IDR7_Pos (7U)

#define	GPIO_IDR_IDR7_Msk (0x1UL << GPIO_IDR_IDR7_Pos)

#define	GPIO_IDR_IDR7 GPIO_IDR_IDR7_Msk

#define	GPIO_IDR_IDR8_Pos (8U)

#define	GPIO_IDR_IDR8_Msk (0x1UL << GPIO_IDR_IDR8_Pos)

#define	GPIO_IDR_IDR8 GPIO_IDR_IDR8_Msk

#define	GPIO_IDR_IDR9_Pos (9U)

#define	GPIO_IDR_IDR9_Msk (0x1UL << GPIO_IDR_IDR9_Pos)

#define	GPIO_IDR_IDR9 GPIO_IDR_IDR9_Msk

#define	GPIO_IDR_IDR10_Pos (10U)

#define	GPIO_IDR_IDR10_Msk (0x1UL << GPIO_IDR_IDR10_Pos)

#define	GPIO_IDR_IDR10 GPIO_IDR_IDR10_Msk

#define	GPIO_IDR_IDR11_Pos (11U)

#define	GPIO_IDR_IDR11_Msk (0x1UL << GPIO_IDR_IDR11_Pos)

#define	GPIO_IDR_IDR11 GPIO_IDR_IDR11_Msk

#define	GPIO_IDR_IDR12_Pos (12U)

#define	GPIO_IDR_IDR12_Msk (0x1UL << GPIO_IDR_IDR12_Pos)

#define	GPIO_IDR_IDR12 GPIO_IDR_IDR12_Msk

#define	GPIO_IDR_IDR13_Pos (13U)

#define	GPIO_IDR_IDR13_Msk (0x1UL << GPIO_IDR_IDR13_Pos)

#define	GPIO_IDR_IDR13 GPIO_IDR_IDR13_Msk

#define	GPIO_IDR_IDR14_Pos (14U)

#define	GPIO_IDR_IDR14_Msk (0x1UL << GPIO_IDR_IDR14_Pos)

#define	GPIO_IDR_IDR14 GPIO_IDR_IDR14_Msk

#define	GPIO_IDR_IDR15_Pos (15U)

#define	GPIO_IDR_IDR15_Msk (0x1UL << GPIO_IDR_IDR15_Pos)

#define	GPIO_IDR_IDR15 GPIO_IDR_IDR15_Msk

#define	GPIO_ODR_ODR0_Pos (0U)

#define	GPIO_ODR_ODR0_Msk (0x1UL << GPIO_ODR_ODR0_Pos)

#define	GPIO_ODR_ODR0 GPIO_ODR_ODR0_Msk

#define	GPIO_ODR_ODR1_Pos (1U)

#define	GPIO_ODR_ODR1_Msk (0x1UL << GPIO_ODR_ODR1_Pos)

#define	GPIO_ODR_ODR1 GPIO_ODR_ODR1_Msk

#define	GPIO_ODR_ODR2_Pos (2U)

#define	GPIO_ODR_ODR2_Msk (0x1UL << GPIO_ODR_ODR2_Pos)

#define	GPIO_ODR_ODR2 GPIO_ODR_ODR2_Msk

#define	GPIO_ODR_ODR3_Pos (3U)

#define	GPIO_ODR_ODR3_Msk (0x1UL << GPIO_ODR_ODR3_Pos)

#define	GPIO_ODR_ODR3 GPIO_ODR_ODR3_Msk

#define	GPIO_ODR_ODR4_Pos (4U)

#define	GPIO_ODR_ODR4_Msk (0x1UL << GPIO_ODR_ODR4_Pos)

#define	GPIO_ODR_ODR4 GPIO_ODR_ODR4_Msk

#define	GPIO_ODR_ODR5_Pos (5U)

#define	GPIO_ODR_ODR5_Msk (0x1UL << GPIO_ODR_ODR5_Pos)

#define	GPIO_ODR_ODR5 GPIO_ODR_ODR5_Msk

#define	GPIO_ODR_ODR6_Pos (6U)

#define	GPIO_ODR_ODR6_Msk (0x1UL << GPIO_ODR_ODR6_Pos)

#define	GPIO_ODR_ODR6 GPIO_ODR_ODR6_Msk

#define	GPIO_ODR_ODR7_Pos (7U)

#define	GPIO_ODR_ODR7_Msk (0x1UL << GPIO_ODR_ODR7_Pos)

#define	GPIO_ODR_ODR7 GPIO_ODR_ODR7_Msk

#define	GPIO_ODR_ODR8_Pos (8U)

#define	GPIO_ODR_ODR8_Msk (0x1UL << GPIO_ODR_ODR8_Pos)

#define	GPIO_ODR_ODR8 GPIO_ODR_ODR8_Msk

#define	GPIO_ODR_ODR9_Pos (9U)

#define	GPIO_ODR_ODR9_Msk (0x1UL << GPIO_ODR_ODR9_Pos)

#define	GPIO_ODR_ODR9 GPIO_ODR_ODR9_Msk

#define	GPIO_ODR_ODR10_Pos (10U)

#define	GPIO_ODR_ODR10_Msk (0x1UL << GPIO_ODR_ODR10_Pos)

#define	GPIO_ODR_ODR10 GPIO_ODR_ODR10_Msk

#define	GPIO_ODR_ODR11_Pos (11U)

#define	GPIO_ODR_ODR11_Msk (0x1UL << GPIO_ODR_ODR11_Pos)

#define	GPIO_ODR_ODR11 GPIO_ODR_ODR11_Msk

#define	GPIO_ODR_ODR12_Pos (12U)

#define	GPIO_ODR_ODR12_Msk (0x1UL << GPIO_ODR_ODR12_Pos)

#define	GPIO_ODR_ODR12 GPIO_ODR_ODR12_Msk

#define	GPIO_ODR_ODR13_Pos (13U)

#define	GPIO_ODR_ODR13_Msk (0x1UL << GPIO_ODR_ODR13_Pos)

#define	GPIO_ODR_ODR13 GPIO_ODR_ODR13_Msk

#define	GPIO_ODR_ODR14_Pos (14U)

#define	GPIO_ODR_ODR14_Msk (0x1UL << GPIO_ODR_ODR14_Pos)

#define	GPIO_ODR_ODR14 GPIO_ODR_ODR14_Msk

#define	GPIO_ODR_ODR15_Pos (15U)

#define	GPIO_ODR_ODR15_Msk (0x1UL << GPIO_ODR_ODR15_Pos)

#define	GPIO_ODR_ODR15 GPIO_ODR_ODR15_Msk

#define	GPIO_BSRR_BS0_Pos (0U)

#define	GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos)

#define	GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk

#define	GPIO_BSRR_BS1_Pos (1U)

#define	GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos)

#define	GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk

#define	GPIO_BSRR_BS2_Pos (2U)

#define	GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos)

#define	GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk

#define	GPIO_BSRR_BS3_Pos (3U)

#define	GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos)

#define	GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk

#define	GPIO_BSRR_BS4_Pos (4U)

#define	GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos)

#define	GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk

#define	GPIO_BSRR_BS5_Pos (5U)

#define	GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos)

#define	GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk

#define	GPIO_BSRR_BS6_Pos (6U)

#define	GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos)

#define	GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk

#define	GPIO_BSRR_BS7_Pos (7U)

#define	GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos)

#define	GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk

#define	GPIO_BSRR_BS8_Pos (8U)

#define	GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos)

#define	GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk

#define	GPIO_BSRR_BS9_Pos (9U)

#define	GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos)

#define	GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk

#define	GPIO_BSRR_BS10_Pos (10U)

#define	GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos)

#define	GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk

#define	GPIO_BSRR_BS11_Pos (11U)

#define	GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos)

#define	GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk

#define	GPIO_BSRR_BS12_Pos (12U)

#define	GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos)

#define	GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk

#define	GPIO_BSRR_BS13_Pos (13U)

#define	GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos)

#define	GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk

#define	GPIO_BSRR_BS14_Pos (14U)

#define	GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos)

#define	GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk

#define	GPIO_BSRR_BS15_Pos (15U)

#define	GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos)

#define	GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk

#define	GPIO_BSRR_BR0_Pos (16U)

#define	GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos)

#define	GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk

#define	GPIO_BSRR_BR1_Pos (17U)

#define	GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos)

#define	GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk

#define	GPIO_BSRR_BR2_Pos (18U)

#define	GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos)

#define	GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk

#define	GPIO_BSRR_BR3_Pos (19U)

#define	GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos)

#define	GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk

#define	GPIO_BSRR_BR4_Pos (20U)

#define	GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos)

#define	GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk

#define	GPIO_BSRR_BR5_Pos (21U)

#define	GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos)

#define	GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk

#define	GPIO_BSRR_BR6_Pos (22U)

#define	GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos)

#define	GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk

#define	GPIO_BSRR_BR7_Pos (23U)

#define	GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos)

#define	GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk

#define	GPIO_BSRR_BR8_Pos (24U)

#define	GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos)

#define	GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk

#define	GPIO_BSRR_BR9_Pos (25U)

#define	GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos)

#define	GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk

#define	GPIO_BSRR_BR10_Pos (26U)

#define	GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos)

#define	GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk

#define	GPIO_BSRR_BR11_Pos (27U)

#define	GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos)

#define	GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk

#define	GPIO_BSRR_BR12_Pos (28U)

#define	GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos)

#define	GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk

#define	GPIO_BSRR_BR13_Pos (29U)

#define	GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos)

#define	GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk

#define	GPIO_BSRR_BR14_Pos (30U)

#define	GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos)

#define	GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk

#define	GPIO_BSRR_BR15_Pos (31U)

#define	GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos)

#define	GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk

#define	GPIO_BRR_BR0_Pos (0U)

#define	GPIO_BRR_BR0_Msk (0x1UL << GPIO_BRR_BR0_Pos)

#define	GPIO_BRR_BR0 GPIO_BRR_BR0_Msk

#define	GPIO_BRR_BR1_Pos (1U)

#define	GPIO_BRR_BR1_Msk (0x1UL << GPIO_BRR_BR1_Pos)

#define	GPIO_BRR_BR1 GPIO_BRR_BR1_Msk

#define	GPIO_BRR_BR2_Pos (2U)

#define	GPIO_BRR_BR2_Msk (0x1UL << GPIO_BRR_BR2_Pos)

#define	GPIO_BRR_BR2 GPIO_BRR_BR2_Msk

#define	GPIO_BRR_BR3_Pos (3U)

#define	GPIO_BRR_BR3_Msk (0x1UL << GPIO_BRR_BR3_Pos)

#define	GPIO_BRR_BR3 GPIO_BRR_BR3_Msk

#define	GPIO_BRR_BR4_Pos (4U)

#define	GPIO_BRR_BR4_Msk (0x1UL << GPIO_BRR_BR4_Pos)

#define	GPIO_BRR_BR4 GPIO_BRR_BR4_Msk

#define	GPIO_BRR_BR5_Pos (5U)

#define	GPIO_BRR_BR5_Msk (0x1UL << GPIO_BRR_BR5_Pos)

#define	GPIO_BRR_BR5 GPIO_BRR_BR5_Msk

#define	GPIO_BRR_BR6_Pos (6U)

#define	GPIO_BRR_BR6_Msk (0x1UL << GPIO_BRR_BR6_Pos)

#define	GPIO_BRR_BR6 GPIO_BRR_BR6_Msk

#define	GPIO_BRR_BR7_Pos (7U)

#define	GPIO_BRR_BR7_Msk (0x1UL << GPIO_BRR_BR7_Pos)

#define	GPIO_BRR_BR7 GPIO_BRR_BR7_Msk

#define	GPIO_BRR_BR8_Pos (8U)

#define	GPIO_BRR_BR8_Msk (0x1UL << GPIO_BRR_BR8_Pos)

#define	GPIO_BRR_BR8 GPIO_BRR_BR8_Msk

#define	GPIO_BRR_BR9_Pos (9U)

#define	GPIO_BRR_BR9_Msk (0x1UL << GPIO_BRR_BR9_Pos)

#define	GPIO_BRR_BR9 GPIO_BRR_BR9_Msk

#define	GPIO_BRR_BR10_Pos (10U)

#define	GPIO_BRR_BR10_Msk (0x1UL << GPIO_BRR_BR10_Pos)

#define	GPIO_BRR_BR10 GPIO_BRR_BR10_Msk

#define	GPIO_BRR_BR11_Pos (11U)

#define	GPIO_BRR_BR11_Msk (0x1UL << GPIO_BRR_BR11_Pos)

#define	GPIO_BRR_BR11 GPIO_BRR_BR11_Msk

#define	GPIO_BRR_BR12_Pos (12U)

#define	GPIO_BRR_BR12_Msk (0x1UL << GPIO_BRR_BR12_Pos)

#define	GPIO_BRR_BR12 GPIO_BRR_BR12_Msk

#define	GPIO_BRR_BR13_Pos (13U)

#define	GPIO_BRR_BR13_Msk (0x1UL << GPIO_BRR_BR13_Pos)

#define	GPIO_BRR_BR13 GPIO_BRR_BR13_Msk

#define	GPIO_BRR_BR14_Pos (14U)

#define	GPIO_BRR_BR14_Msk (0x1UL << GPIO_BRR_BR14_Pos)

#define	GPIO_BRR_BR14 GPIO_BRR_BR14_Msk

#define	GPIO_BRR_BR15_Pos (15U)

#define	GPIO_BRR_BR15_Msk (0x1UL << GPIO_BRR_BR15_Pos)

#define	GPIO_BRR_BR15 GPIO_BRR_BR15_Msk

#define	GPIO_LCKR_LCK0_Pos (0U)

#define	GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos)

#define	GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk

#define	GPIO_LCKR_LCK1_Pos (1U)

#define	GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos)

#define	GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk

#define	GPIO_LCKR_LCK2_Pos (2U)

#define	GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos)

#define	GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk

#define	GPIO_LCKR_LCK3_Pos (3U)

#define	GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos)

#define	GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk

#define	GPIO_LCKR_LCK4_Pos (4U)

#define	GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos)

#define	GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk

#define	GPIO_LCKR_LCK5_Pos (5U)

#define	GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos)

#define	GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk

#define	GPIO_LCKR_LCK6_Pos (6U)

#define	GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos)

#define	GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk

#define	GPIO_LCKR_LCK7_Pos (7U)

#define	GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos)

#define	GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk

#define	GPIO_LCKR_LCK8_Pos (8U)

#define	GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos)

#define	GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk

#define	GPIO_LCKR_LCK9_Pos (9U)

#define	GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos)

#define	GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk

#define	GPIO_LCKR_LCK10_Pos (10U)

#define	GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos)

#define	GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk

#define	GPIO_LCKR_LCK11_Pos (11U)

#define	GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos)

#define	GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk

#define	GPIO_LCKR_LCK12_Pos (12U)

#define	GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos)

#define	GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk

#define	GPIO_LCKR_LCK13_Pos (13U)

#define	GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos)

#define	GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk

#define	GPIO_LCKR_LCK14_Pos (14U)

#define	GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos)

#define	GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk

#define	GPIO_LCKR_LCK15_Pos (15U)

#define	GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos)

#define	GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk

#define	GPIO_LCKR_LCKK_Pos (16U)

#define	GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos)

#define	GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk

#define	AFIO_EVCR_PIN_Pos (0U)

#define	AFIO_EVCR_PIN_Msk (0xFUL << AFIO_EVCR_PIN_Pos)

#define	AFIO_EVCR_PIN AFIO_EVCR_PIN_Msk

#define	AFIO_EVCR_PIN_0 (0x1UL << AFIO_EVCR_PIN_Pos)

#define	AFIO_EVCR_PIN_1 (0x2UL << AFIO_EVCR_PIN_Pos)

#define	AFIO_EVCR_PIN_2 (0x4UL << AFIO_EVCR_PIN_Pos)

#define	AFIO_EVCR_PIN_3 (0x8UL << AFIO_EVCR_PIN_Pos)

#define	AFIO_EVCR_PIN_PX0 0x00000000U

#define	AFIO_EVCR_PIN_PX1_Pos (0U)

#define	AFIO_EVCR_PIN_PX1_Msk (0x1UL << AFIO_EVCR_PIN_PX1_Pos)

#define	AFIO_EVCR_PIN_PX1 AFIO_EVCR_PIN_PX1_Msk

#define	AFIO_EVCR_PIN_PX2_Pos (1U)

#define	AFIO_EVCR_PIN_PX2_Msk (0x1UL << AFIO_EVCR_PIN_PX2_Pos)

#define	AFIO_EVCR_PIN_PX2 AFIO_EVCR_PIN_PX2_Msk

#define	AFIO_EVCR_PIN_PX3_Pos (0U)

#define	AFIO_EVCR_PIN_PX3_Msk (0x3UL << AFIO_EVCR_PIN_PX3_Pos)

#define	AFIO_EVCR_PIN_PX3 AFIO_EVCR_PIN_PX3_Msk

#define	AFIO_EVCR_PIN_PX4_Pos (2U)

#define	AFIO_EVCR_PIN_PX4_Msk (0x1UL << AFIO_EVCR_PIN_PX4_Pos)

#define	AFIO_EVCR_PIN_PX4 AFIO_EVCR_PIN_PX4_Msk

#define	AFIO_EVCR_PIN_PX5_Pos (0U)

#define	AFIO_EVCR_PIN_PX5_Msk (0x5UL << AFIO_EVCR_PIN_PX5_Pos)

#define	AFIO_EVCR_PIN_PX5 AFIO_EVCR_PIN_PX5_Msk

#define	AFIO_EVCR_PIN_PX6_Pos (1U)

#define	AFIO_EVCR_PIN_PX6_Msk (0x3UL << AFIO_EVCR_PIN_PX6_Pos)

#define	AFIO_EVCR_PIN_PX6 AFIO_EVCR_PIN_PX6_Msk

#define	AFIO_EVCR_PIN_PX7_Pos (0U)

#define	AFIO_EVCR_PIN_PX7_Msk (0x7UL << AFIO_EVCR_PIN_PX7_Pos)

#define	AFIO_EVCR_PIN_PX7 AFIO_EVCR_PIN_PX7_Msk

#define	AFIO_EVCR_PIN_PX8_Pos (3U)

#define	AFIO_EVCR_PIN_PX8_Msk (0x1UL << AFIO_EVCR_PIN_PX8_Pos)

#define	AFIO_EVCR_PIN_PX8 AFIO_EVCR_PIN_PX8_Msk

#define	AFIO_EVCR_PIN_PX9_Pos (0U)

#define	AFIO_EVCR_PIN_PX9_Msk (0x9UL << AFIO_EVCR_PIN_PX9_Pos)

#define	AFIO_EVCR_PIN_PX9 AFIO_EVCR_PIN_PX9_Msk

#define	AFIO_EVCR_PIN_PX10_Pos (1U)

#define	AFIO_EVCR_PIN_PX10_Msk (0x5UL << AFIO_EVCR_PIN_PX10_Pos)

#define	AFIO_EVCR_PIN_PX10 AFIO_EVCR_PIN_PX10_Msk

#define	AFIO_EVCR_PIN_PX11_Pos (0U)

#define	AFIO_EVCR_PIN_PX11_Msk (0xBUL << AFIO_EVCR_PIN_PX11_Pos)

#define	AFIO_EVCR_PIN_PX11 AFIO_EVCR_PIN_PX11_Msk

#define	AFIO_EVCR_PIN_PX12_Pos (2U)

#define	AFIO_EVCR_PIN_PX12_Msk (0x3UL << AFIO_EVCR_PIN_PX12_Pos)

#define	AFIO_EVCR_PIN_PX12 AFIO_EVCR_PIN_PX12_Msk

#define	AFIO_EVCR_PIN_PX13_Pos (0U)

#define	AFIO_EVCR_PIN_PX13_Msk (0xDUL << AFIO_EVCR_PIN_PX13_Pos)

#define	AFIO_EVCR_PIN_PX13 AFIO_EVCR_PIN_PX13_Msk

#define	AFIO_EVCR_PIN_PX14_Pos (1U)

#define	AFIO_EVCR_PIN_PX14_Msk (0x7UL << AFIO_EVCR_PIN_PX14_Pos)

#define	AFIO_EVCR_PIN_PX14 AFIO_EVCR_PIN_PX14_Msk

#define	AFIO_EVCR_PIN_PX15_Pos (0U)

#define	AFIO_EVCR_PIN_PX15_Msk (0xFUL << AFIO_EVCR_PIN_PX15_Pos)

#define	AFIO_EVCR_PIN_PX15 AFIO_EVCR_PIN_PX15_Msk

#define	AFIO_EVCR_PORT_Pos (4U)

#define	AFIO_EVCR_PORT_Msk (0x7UL << AFIO_EVCR_PORT_Pos)

#define	AFIO_EVCR_PORT AFIO_EVCR_PORT_Msk

#define	AFIO_EVCR_PORT_0 (0x1UL << AFIO_EVCR_PORT_Pos)

#define	AFIO_EVCR_PORT_1 (0x2UL << AFIO_EVCR_PORT_Pos)

#define	AFIO_EVCR_PORT_2 (0x4UL << AFIO_EVCR_PORT_Pos)

#define	AFIO_EVCR_PORT_PA 0x00000000

#define	AFIO_EVCR_PORT_PB_Pos (4U)

#define	AFIO_EVCR_PORT_PB_Msk (0x1UL << AFIO_EVCR_PORT_PB_Pos)

#define	AFIO_EVCR_PORT_PB AFIO_EVCR_PORT_PB_Msk

#define	AFIO_EVCR_PORT_PC_Pos (5U)

#define	AFIO_EVCR_PORT_PC_Msk (0x1UL << AFIO_EVCR_PORT_PC_Pos)

#define	AFIO_EVCR_PORT_PC AFIO_EVCR_PORT_PC_Msk

#define	AFIO_EVCR_PORT_PD_Pos (4U)

#define	AFIO_EVCR_PORT_PD_Msk (0x3UL << AFIO_EVCR_PORT_PD_Pos)

#define	AFIO_EVCR_PORT_PD AFIO_EVCR_PORT_PD_Msk

#define	AFIO_EVCR_PORT_PE_Pos (6U)

#define	AFIO_EVCR_PORT_PE_Msk (0x1UL << AFIO_EVCR_PORT_PE_Pos)

#define	AFIO_EVCR_PORT_PE AFIO_EVCR_PORT_PE_Msk

#define	AFIO_EVCR_EVOE_Pos (7U)

#define	AFIO_EVCR_EVOE_Msk (0x1UL << AFIO_EVCR_EVOE_Pos)

#define	AFIO_EVCR_EVOE AFIO_EVCR_EVOE_Msk

#define	AFIO_MAPR_SPI1_REMAP_Pos (0U)

#define	AFIO_MAPR_SPI1_REMAP_Msk (0x1UL << AFIO_MAPR_SPI1_REMAP_Pos)

#define	AFIO_MAPR_SPI1_REMAP AFIO_MAPR_SPI1_REMAP_Msk

#define	AFIO_MAPR_I2C1_REMAP_Pos (1U)

#define	AFIO_MAPR_I2C1_REMAP_Msk (0x1UL << AFIO_MAPR_I2C1_REMAP_Pos)

#define	AFIO_MAPR_I2C1_REMAP AFIO_MAPR_I2C1_REMAP_Msk

#define	AFIO_MAPR_USART1_REMAP_Pos (2U)

#define	AFIO_MAPR_USART1_REMAP_Msk (0x1UL << AFIO_MAPR_USART1_REMAP_Pos)

#define	AFIO_MAPR_USART1_REMAP AFIO_MAPR_USART1_REMAP_Msk

#define	AFIO_MAPR_USART2_REMAP_Pos (3U)

#define	AFIO_MAPR_USART2_REMAP_Msk (0x1UL << AFIO_MAPR_USART2_REMAP_Pos)

#define	AFIO_MAPR_USART2_REMAP AFIO_MAPR_USART2_REMAP_Msk

#define	AFIO_MAPR_USART3_REMAP_Pos (4U)

#define	AFIO_MAPR_USART3_REMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_Pos)

#define	AFIO_MAPR_USART3_REMAP AFIO_MAPR_USART3_REMAP_Msk

#define	AFIO_MAPR_USART3_REMAP_0 (0x1UL << AFIO_MAPR_USART3_REMAP_Pos)

#define	AFIO_MAPR_USART3_REMAP_1 (0x2UL << AFIO_MAPR_USART3_REMAP_Pos)

#define	AFIO_MAPR_USART3_REMAP_NOREMAP 0x00000000U

#define	AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos (4U)

#define	AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Pos)

#define	AFIO_MAPR_USART3_REMAP_PARTIALREMAP AFIO_MAPR_USART3_REMAP_PARTIALREMAP_Msk

#define	AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos (4U)

#define	AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_USART3_REMAP_FULLREMAP_Pos)

#define	AFIO_MAPR_USART3_REMAP_FULLREMAP AFIO_MAPR_USART3_REMAP_FULLREMAP_Msk

#define	AFIO_MAPR_TIM1_REMAP_Pos (6U)

#define	AFIO_MAPR_TIM1_REMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_Pos)

#define	AFIO_MAPR_TIM1_REMAP AFIO_MAPR_TIM1_REMAP_Msk

#define	AFIO_MAPR_TIM1_REMAP_0 (0x1UL << AFIO_MAPR_TIM1_REMAP_Pos)

#define	AFIO_MAPR_TIM1_REMAP_1 (0x2UL << AFIO_MAPR_TIM1_REMAP_Pos)

#define	AFIO_MAPR_TIM1_REMAP_NOREMAP 0x00000000U

#define	AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos (6U)

#define	AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Pos)

#define	AFIO_MAPR_TIM1_REMAP_PARTIALREMAP AFIO_MAPR_TIM1_REMAP_PARTIALREMAP_Msk

#define	AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos (6U)

#define	AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM1_REMAP_FULLREMAP_Pos)

#define	AFIO_MAPR_TIM1_REMAP_FULLREMAP AFIO_MAPR_TIM1_REMAP_FULLREMAP_Msk

#define	AFIO_MAPR_TIM2_REMAP_Pos (8U)

#define	AFIO_MAPR_TIM2_REMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_Pos)

#define	AFIO_MAPR_TIM2_REMAP AFIO_MAPR_TIM2_REMAP_Msk

#define	AFIO_MAPR_TIM2_REMAP_0 (0x1UL << AFIO_MAPR_TIM2_REMAP_Pos)

#define	AFIO_MAPR_TIM2_REMAP_1 (0x2UL << AFIO_MAPR_TIM2_REMAP_Pos)

#define	AFIO_MAPR_TIM2_REMAP_NOREMAP 0x00000000U

#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos (8U)

#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Pos)

#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP1_Msk

#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos (9U)

#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk (0x1UL << AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Pos)

#define	AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2 AFIO_MAPR_TIM2_REMAP_PARTIALREMAP2_Msk

#define	AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos (8U)

#define	AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM2_REMAP_FULLREMAP_Pos)

#define	AFIO_MAPR_TIM2_REMAP_FULLREMAP AFIO_MAPR_TIM2_REMAP_FULLREMAP_Msk

#define	AFIO_MAPR_TIM3_REMAP_Pos (10U)

#define	AFIO_MAPR_TIM3_REMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_Pos)

#define	AFIO_MAPR_TIM3_REMAP AFIO_MAPR_TIM3_REMAP_Msk

#define	AFIO_MAPR_TIM3_REMAP_0 (0x1UL << AFIO_MAPR_TIM3_REMAP_Pos)

#define	AFIO_MAPR_TIM3_REMAP_1 (0x2UL << AFIO_MAPR_TIM3_REMAP_Pos)

#define	AFIO_MAPR_TIM3_REMAP_NOREMAP 0x00000000U

#define	AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos (11U)

#define	AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk (0x1UL << AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Pos)

#define	AFIO_MAPR_TIM3_REMAP_PARTIALREMAP AFIO_MAPR_TIM3_REMAP_PARTIALREMAP_Msk

#define	AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos (10U)

#define	AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk (0x3UL << AFIO_MAPR_TIM3_REMAP_FULLREMAP_Pos)

#define	AFIO_MAPR_TIM3_REMAP_FULLREMAP AFIO_MAPR_TIM3_REMAP_FULLREMAP_Msk

#define	AFIO_MAPR_TIM4_REMAP_Pos (12U)

#define	AFIO_MAPR_TIM4_REMAP_Msk (0x1UL << AFIO_MAPR_TIM4_REMAP_Pos)

#define	AFIO_MAPR_TIM4_REMAP AFIO_MAPR_TIM4_REMAP_Msk

#define	AFIO_MAPR_CAN_REMAP_Pos (13U)

#define	AFIO_MAPR_CAN_REMAP_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_Pos)

#define	AFIO_MAPR_CAN_REMAP AFIO_MAPR_CAN_REMAP_Msk

#define	AFIO_MAPR_CAN_REMAP_0 (0x1UL << AFIO_MAPR_CAN_REMAP_Pos)

#define	AFIO_MAPR_CAN_REMAP_1 (0x2UL << AFIO_MAPR_CAN_REMAP_Pos)

#define	AFIO_MAPR_CAN_REMAP_REMAP1 0x00000000U

#define	AFIO_MAPR_CAN_REMAP_REMAP2_Pos (14U)

#define	AFIO_MAPR_CAN_REMAP_REMAP2_Msk (0x1UL << AFIO_MAPR_CAN_REMAP_REMAP2_Pos)

#define	AFIO_MAPR_CAN_REMAP_REMAP2 AFIO_MAPR_CAN_REMAP_REMAP2_Msk

#define	AFIO_MAPR_CAN_REMAP_REMAP3_Pos (13U)

#define	AFIO_MAPR_CAN_REMAP_REMAP3_Msk (0x3UL << AFIO_MAPR_CAN_REMAP_REMAP3_Pos)

#define	AFIO_MAPR_CAN_REMAP_REMAP3 AFIO_MAPR_CAN_REMAP_REMAP3_Msk

#define	AFIO_MAPR_PD01_REMAP_Pos (15U)

#define	AFIO_MAPR_PD01_REMAP_Msk (0x1UL << AFIO_MAPR_PD01_REMAP_Pos)

#define	AFIO_MAPR_PD01_REMAP AFIO_MAPR_PD01_REMAP_Msk

#define	AFIO_MAPR_TIM5CH4_IREMAP_Pos (16U)

#define	AFIO_MAPR_TIM5CH4_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM5CH4_IREMAP_Pos)

#define	AFIO_MAPR_TIM5CH4_IREMAP AFIO_MAPR_TIM5CH4_IREMAP_Msk

#define	AFIO_MAPR_SWJ_CFG_Pos (24U)

#define	AFIO_MAPR_SWJ_CFG_Msk (0x7UL << AFIO_MAPR_SWJ_CFG_Pos)

#define	AFIO_MAPR_SWJ_CFG AFIO_MAPR_SWJ_CFG_Msk

#define	AFIO_MAPR_SWJ_CFG_0 (0x1UL << AFIO_MAPR_SWJ_CFG_Pos)

#define	AFIO_MAPR_SWJ_CFG_1 (0x2UL << AFIO_MAPR_SWJ_CFG_Pos)

#define	AFIO_MAPR_SWJ_CFG_2 (0x4UL << AFIO_MAPR_SWJ_CFG_Pos)

#define	AFIO_MAPR_SWJ_CFG_RESET 0x00000000U

#define	AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos (24U)

#define	AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_NOJNTRST_Pos)

#define	AFIO_MAPR_SWJ_CFG_NOJNTRST AFIO_MAPR_SWJ_CFG_NOJNTRST_Msk

#define	AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos (25U)

#define	AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Pos)

#define	AFIO_MAPR_SWJ_CFG_JTAGDISABLE AFIO_MAPR_SWJ_CFG_JTAGDISABLE_Msk

#define	AFIO_MAPR_SWJ_CFG_DISABLE_Pos (26U)

#define	AFIO_MAPR_SWJ_CFG_DISABLE_Msk (0x1UL << AFIO_MAPR_SWJ_CFG_DISABLE_Pos)

#define	AFIO_MAPR_SWJ_CFG_DISABLE AFIO_MAPR_SWJ_CFG_DISABLE_Msk

#define	AFIO_MAPR_ETH_REMAP_Pos (21U)

#define	AFIO_MAPR_ETH_REMAP_Msk (0x1UL << AFIO_MAPR_ETH_REMAP_Pos)

#define	AFIO_MAPR_ETH_REMAP AFIO_MAPR_ETH_REMAP_Msk

#define	AFIO_MAPR_CAN2_REMAP_Pos (22U)

#define	AFIO_MAPR_CAN2_REMAP_Msk (0x1UL << AFIO_MAPR_CAN2_REMAP_Pos)

#define	AFIO_MAPR_CAN2_REMAP AFIO_MAPR_CAN2_REMAP_Msk

#define	AFIO_MAPR_MII_RMII_SEL_Pos (23U)

#define	AFIO_MAPR_MII_RMII_SEL_Msk (0x1UL << AFIO_MAPR_MII_RMII_SEL_Pos)

#define	AFIO_MAPR_MII_RMII_SEL AFIO_MAPR_MII_RMII_SEL_Msk

#define	AFIO_MAPR_SPI3_REMAP_Pos (28U)

#define	AFIO_MAPR_SPI3_REMAP_Msk (0x1UL << AFIO_MAPR_SPI3_REMAP_Pos)

#define	AFIO_MAPR_SPI3_REMAP AFIO_MAPR_SPI3_REMAP_Msk

#define	AFIO_MAPR_TIM2ITR1_IREMAP_Pos (29U)

#define	AFIO_MAPR_TIM2ITR1_IREMAP_Msk (0x1UL << AFIO_MAPR_TIM2ITR1_IREMAP_Pos)

#define	AFIO_MAPR_TIM2ITR1_IREMAP AFIO_MAPR_TIM2ITR1_IREMAP_Msk

#define	AFIO_MAPR_PTP_PPS_REMAP_Pos (30U)

#define	AFIO_MAPR_PTP_PPS_REMAP_Msk (0x1UL << AFIO_MAPR_PTP_PPS_REMAP_Pos)

#define	AFIO_MAPR_PTP_PPS_REMAP AFIO_MAPR_PTP_PPS_REMAP_Msk

#define	AFIO_EXTICR1_EXTI0_Pos (0U)

#define	AFIO_EXTICR1_EXTI0_Msk (0xFUL << AFIO_EXTICR1_EXTI0_Pos)

#define	AFIO_EXTICR1_EXTI0 AFIO_EXTICR1_EXTI0_Msk

#define	AFIO_EXTICR1_EXTI1_Pos (4U)

#define	AFIO_EXTICR1_EXTI1_Msk (0xFUL << AFIO_EXTICR1_EXTI1_Pos)

#define	AFIO_EXTICR1_EXTI1 AFIO_EXTICR1_EXTI1_Msk

#define	AFIO_EXTICR1_EXTI2_Pos (8U)

#define	AFIO_EXTICR1_EXTI2_Msk (0xFUL << AFIO_EXTICR1_EXTI2_Pos)

#define	AFIO_EXTICR1_EXTI2 AFIO_EXTICR1_EXTI2_Msk

#define	AFIO_EXTICR1_EXTI3_Pos (12U)

#define	AFIO_EXTICR1_EXTI3_Msk (0xFUL << AFIO_EXTICR1_EXTI3_Pos)

#define	AFIO_EXTICR1_EXTI3 AFIO_EXTICR1_EXTI3_Msk

#define	AFIO_EXTICR1_EXTI0_PA 0x00000000U

#define	AFIO_EXTICR1_EXTI0_PB_Pos (0U)

#define	AFIO_EXTICR1_EXTI0_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PB_Pos)

#define	AFIO_EXTICR1_EXTI0_PB AFIO_EXTICR1_EXTI0_PB_Msk

#define	AFIO_EXTICR1_EXTI0_PC_Pos (1U)

#define	AFIO_EXTICR1_EXTI0_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PC_Pos)

#define	AFIO_EXTICR1_EXTI0_PC AFIO_EXTICR1_EXTI0_PC_Msk

#define	AFIO_EXTICR1_EXTI0_PD_Pos (0U)

#define	AFIO_EXTICR1_EXTI0_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PD_Pos)

#define	AFIO_EXTICR1_EXTI0_PD AFIO_EXTICR1_EXTI0_PD_Msk

#define	AFIO_EXTICR1_EXTI0_PE_Pos (2U)

#define	AFIO_EXTICR1_EXTI0_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI0_PE_Pos)

#define	AFIO_EXTICR1_EXTI0_PE AFIO_EXTICR1_EXTI0_PE_Msk

#define	AFIO_EXTICR1_EXTI0_PF_Pos (0U)

#define	AFIO_EXTICR1_EXTI0_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI0_PF_Pos)

#define	AFIO_EXTICR1_EXTI0_PF AFIO_EXTICR1_EXTI0_PF_Msk

#define	AFIO_EXTICR1_EXTI0_PG_Pos (1U)

#define	AFIO_EXTICR1_EXTI0_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI0_PG_Pos)

#define	AFIO_EXTICR1_EXTI0_PG AFIO_EXTICR1_EXTI0_PG_Msk

#define	AFIO_EXTICR1_EXTI1_PA 0x00000000U

#define	AFIO_EXTICR1_EXTI1_PB_Pos (4U)

#define	AFIO_EXTICR1_EXTI1_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PB_Pos)

#define	AFIO_EXTICR1_EXTI1_PB AFIO_EXTICR1_EXTI1_PB_Msk

#define	AFIO_EXTICR1_EXTI1_PC_Pos (5U)

#define	AFIO_EXTICR1_EXTI1_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PC_Pos)

#define	AFIO_EXTICR1_EXTI1_PC AFIO_EXTICR1_EXTI1_PC_Msk

#define	AFIO_EXTICR1_EXTI1_PD_Pos (4U)

#define	AFIO_EXTICR1_EXTI1_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PD_Pos)

#define	AFIO_EXTICR1_EXTI1_PD AFIO_EXTICR1_EXTI1_PD_Msk

#define	AFIO_EXTICR1_EXTI1_PE_Pos (6U)

#define	AFIO_EXTICR1_EXTI1_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI1_PE_Pos)

#define	AFIO_EXTICR1_EXTI1_PE AFIO_EXTICR1_EXTI1_PE_Msk

#define	AFIO_EXTICR1_EXTI1_PF_Pos (4U)

#define	AFIO_EXTICR1_EXTI1_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI1_PF_Pos)

#define	AFIO_EXTICR1_EXTI1_PF AFIO_EXTICR1_EXTI1_PF_Msk

#define	AFIO_EXTICR1_EXTI1_PG_Pos (5U)

#define	AFIO_EXTICR1_EXTI1_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI1_PG_Pos)

#define	AFIO_EXTICR1_EXTI1_PG AFIO_EXTICR1_EXTI1_PG_Msk

#define	AFIO_EXTICR1_EXTI2_PA 0x00000000U

#define	AFIO_EXTICR1_EXTI2_PB_Pos (8U)

#define	AFIO_EXTICR1_EXTI2_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PB_Pos)

#define	AFIO_EXTICR1_EXTI2_PB AFIO_EXTICR1_EXTI2_PB_Msk

#define	AFIO_EXTICR1_EXTI2_PC_Pos (9U)

#define	AFIO_EXTICR1_EXTI2_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PC_Pos)

#define	AFIO_EXTICR1_EXTI2_PC AFIO_EXTICR1_EXTI2_PC_Msk

#define	AFIO_EXTICR1_EXTI2_PD_Pos (8U)

#define	AFIO_EXTICR1_EXTI2_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PD_Pos)

#define	AFIO_EXTICR1_EXTI2_PD AFIO_EXTICR1_EXTI2_PD_Msk

#define	AFIO_EXTICR1_EXTI2_PE_Pos (10U)

#define	AFIO_EXTICR1_EXTI2_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI2_PE_Pos)

#define	AFIO_EXTICR1_EXTI2_PE AFIO_EXTICR1_EXTI2_PE_Msk

#define	AFIO_EXTICR1_EXTI2_PF_Pos (8U)

#define	AFIO_EXTICR1_EXTI2_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI2_PF_Pos)

#define	AFIO_EXTICR1_EXTI2_PF AFIO_EXTICR1_EXTI2_PF_Msk

#define	AFIO_EXTICR1_EXTI2_PG_Pos (9U)

#define	AFIO_EXTICR1_EXTI2_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI2_PG_Pos)

#define	AFIO_EXTICR1_EXTI2_PG AFIO_EXTICR1_EXTI2_PG_Msk

#define	AFIO_EXTICR1_EXTI3_PA 0x00000000U

#define	AFIO_EXTICR1_EXTI3_PB_Pos (12U)

#define	AFIO_EXTICR1_EXTI3_PB_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PB_Pos)

#define	AFIO_EXTICR1_EXTI3_PB AFIO_EXTICR1_EXTI3_PB_Msk

#define	AFIO_EXTICR1_EXTI3_PC_Pos (13U)

#define	AFIO_EXTICR1_EXTI3_PC_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PC_Pos)

#define	AFIO_EXTICR1_EXTI3_PC AFIO_EXTICR1_EXTI3_PC_Msk

#define	AFIO_EXTICR1_EXTI3_PD_Pos (12U)

#define	AFIO_EXTICR1_EXTI3_PD_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PD_Pos)

#define	AFIO_EXTICR1_EXTI3_PD AFIO_EXTICR1_EXTI3_PD_Msk

#define	AFIO_EXTICR1_EXTI3_PE_Pos (14U)

#define	AFIO_EXTICR1_EXTI3_PE_Msk (0x1UL << AFIO_EXTICR1_EXTI3_PE_Pos)

#define	AFIO_EXTICR1_EXTI3_PE AFIO_EXTICR1_EXTI3_PE_Msk

#define	AFIO_EXTICR1_EXTI3_PF_Pos (12U)

#define	AFIO_EXTICR1_EXTI3_PF_Msk (0x5UL << AFIO_EXTICR1_EXTI3_PF_Pos)

#define	AFIO_EXTICR1_EXTI3_PF AFIO_EXTICR1_EXTI3_PF_Msk

#define	AFIO_EXTICR1_EXTI3_PG_Pos (13U)

#define	AFIO_EXTICR1_EXTI3_PG_Msk (0x3UL << AFIO_EXTICR1_EXTI3_PG_Pos)

#define	AFIO_EXTICR1_EXTI3_PG AFIO_EXTICR1_EXTI3_PG_Msk

#define	AFIO_EXTICR2_EXTI4_Pos (0U)

#define	AFIO_EXTICR2_EXTI4_Msk (0xFUL << AFIO_EXTICR2_EXTI4_Pos)

#define	AFIO_EXTICR2_EXTI4 AFIO_EXTICR2_EXTI4_Msk

#define	AFIO_EXTICR2_EXTI5_Pos (4U)

#define	AFIO_EXTICR2_EXTI5_Msk (0xFUL << AFIO_EXTICR2_EXTI5_Pos)

#define	AFIO_EXTICR2_EXTI5 AFIO_EXTICR2_EXTI5_Msk

#define	AFIO_EXTICR2_EXTI6_Pos (8U)

#define	AFIO_EXTICR2_EXTI6_Msk (0xFUL << AFIO_EXTICR2_EXTI6_Pos)

#define	AFIO_EXTICR2_EXTI6 AFIO_EXTICR2_EXTI6_Msk

#define	AFIO_EXTICR2_EXTI7_Pos (12U)

#define	AFIO_EXTICR2_EXTI7_Msk (0xFUL << AFIO_EXTICR2_EXTI7_Pos)

#define	AFIO_EXTICR2_EXTI7 AFIO_EXTICR2_EXTI7_Msk

#define	AFIO_EXTICR2_EXTI4_PA 0x00000000U

#define	AFIO_EXTICR2_EXTI4_PB_Pos (0U)

#define	AFIO_EXTICR2_EXTI4_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PB_Pos)

#define	AFIO_EXTICR2_EXTI4_PB AFIO_EXTICR2_EXTI4_PB_Msk

#define	AFIO_EXTICR2_EXTI4_PC_Pos (1U)

#define	AFIO_EXTICR2_EXTI4_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PC_Pos)

#define	AFIO_EXTICR2_EXTI4_PC AFIO_EXTICR2_EXTI4_PC_Msk

#define	AFIO_EXTICR2_EXTI4_PD_Pos (0U)

#define	AFIO_EXTICR2_EXTI4_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PD_Pos)

#define	AFIO_EXTICR2_EXTI4_PD AFIO_EXTICR2_EXTI4_PD_Msk

#define	AFIO_EXTICR2_EXTI4_PE_Pos (2U)

#define	AFIO_EXTICR2_EXTI4_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI4_PE_Pos)

#define	AFIO_EXTICR2_EXTI4_PE AFIO_EXTICR2_EXTI4_PE_Msk

#define	AFIO_EXTICR2_EXTI4_PF_Pos (0U)

#define	AFIO_EXTICR2_EXTI4_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI4_PF_Pos)

#define	AFIO_EXTICR2_EXTI4_PF AFIO_EXTICR2_EXTI4_PF_Msk

#define	AFIO_EXTICR2_EXTI4_PG_Pos (1U)

#define	AFIO_EXTICR2_EXTI4_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI4_PG_Pos)

#define	AFIO_EXTICR2_EXTI4_PG AFIO_EXTICR2_EXTI4_PG_Msk

#define	AFIO_EXTICR2_EXTI5_PA 0x00000000U

#define	AFIO_EXTICR2_EXTI5_PB_Pos (4U)

#define	AFIO_EXTICR2_EXTI5_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PB_Pos)

#define	AFIO_EXTICR2_EXTI5_PB AFIO_EXTICR2_EXTI5_PB_Msk

#define	AFIO_EXTICR2_EXTI5_PC_Pos (5U)

#define	AFIO_EXTICR2_EXTI5_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PC_Pos)

#define	AFIO_EXTICR2_EXTI5_PC AFIO_EXTICR2_EXTI5_PC_Msk

#define	AFIO_EXTICR2_EXTI5_PD_Pos (4U)

#define	AFIO_EXTICR2_EXTI5_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PD_Pos)

#define	AFIO_EXTICR2_EXTI5_PD AFIO_EXTICR2_EXTI5_PD_Msk

#define	AFIO_EXTICR2_EXTI5_PE_Pos (6U)

#define	AFIO_EXTICR2_EXTI5_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI5_PE_Pos)

#define	AFIO_EXTICR2_EXTI5_PE AFIO_EXTICR2_EXTI5_PE_Msk

#define	AFIO_EXTICR2_EXTI5_PF_Pos (4U)

#define	AFIO_EXTICR2_EXTI5_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI5_PF_Pos)

#define	AFIO_EXTICR2_EXTI5_PF AFIO_EXTICR2_EXTI5_PF_Msk

#define	AFIO_EXTICR2_EXTI5_PG_Pos (5U)

#define	AFIO_EXTICR2_EXTI5_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI5_PG_Pos)

#define	AFIO_EXTICR2_EXTI5_PG AFIO_EXTICR2_EXTI5_PG_Msk

#define	AFIO_EXTICR2_EXTI6_PA 0x00000000U

#define	AFIO_EXTICR2_EXTI6_PB_Pos (8U)

#define	AFIO_EXTICR2_EXTI6_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PB_Pos)

#define	AFIO_EXTICR2_EXTI6_PB AFIO_EXTICR2_EXTI6_PB_Msk

#define	AFIO_EXTICR2_EXTI6_PC_Pos (9U)

#define	AFIO_EXTICR2_EXTI6_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PC_Pos)

#define	AFIO_EXTICR2_EXTI6_PC AFIO_EXTICR2_EXTI6_PC_Msk

#define	AFIO_EXTICR2_EXTI6_PD_Pos (8U)

#define	AFIO_EXTICR2_EXTI6_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PD_Pos)

#define	AFIO_EXTICR2_EXTI6_PD AFIO_EXTICR2_EXTI6_PD_Msk

#define	AFIO_EXTICR2_EXTI6_PE_Pos (10U)

#define	AFIO_EXTICR2_EXTI6_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI6_PE_Pos)

#define	AFIO_EXTICR2_EXTI6_PE AFIO_EXTICR2_EXTI6_PE_Msk

#define	AFIO_EXTICR2_EXTI6_PF_Pos (8U)

#define	AFIO_EXTICR2_EXTI6_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI6_PF_Pos)

#define	AFIO_EXTICR2_EXTI6_PF AFIO_EXTICR2_EXTI6_PF_Msk

#define	AFIO_EXTICR2_EXTI6_PG_Pos (9U)

#define	AFIO_EXTICR2_EXTI6_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI6_PG_Pos)

#define	AFIO_EXTICR2_EXTI6_PG AFIO_EXTICR2_EXTI6_PG_Msk

#define	AFIO_EXTICR2_EXTI7_PA 0x00000000U

#define	AFIO_EXTICR2_EXTI7_PB_Pos (12U)

#define	AFIO_EXTICR2_EXTI7_PB_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PB_Pos)

#define	AFIO_EXTICR2_EXTI7_PB AFIO_EXTICR2_EXTI7_PB_Msk

#define	AFIO_EXTICR2_EXTI7_PC_Pos (13U)

#define	AFIO_EXTICR2_EXTI7_PC_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PC_Pos)

#define	AFIO_EXTICR2_EXTI7_PC AFIO_EXTICR2_EXTI7_PC_Msk

#define	AFIO_EXTICR2_EXTI7_PD_Pos (12U)

#define	AFIO_EXTICR2_EXTI7_PD_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PD_Pos)

#define	AFIO_EXTICR2_EXTI7_PD AFIO_EXTICR2_EXTI7_PD_Msk

#define	AFIO_EXTICR2_EXTI7_PE_Pos (14U)

#define	AFIO_EXTICR2_EXTI7_PE_Msk (0x1UL << AFIO_EXTICR2_EXTI7_PE_Pos)

#define	AFIO_EXTICR2_EXTI7_PE AFIO_EXTICR2_EXTI7_PE_Msk

#define	AFIO_EXTICR2_EXTI7_PF_Pos (12U)

#define	AFIO_EXTICR2_EXTI7_PF_Msk (0x5UL << AFIO_EXTICR2_EXTI7_PF_Pos)

#define	AFIO_EXTICR2_EXTI7_PF AFIO_EXTICR2_EXTI7_PF_Msk

#define	AFIO_EXTICR2_EXTI7_PG_Pos (13U)

#define	AFIO_EXTICR2_EXTI7_PG_Msk (0x3UL << AFIO_EXTICR2_EXTI7_PG_Pos)

#define	AFIO_EXTICR2_EXTI7_PG AFIO_EXTICR2_EXTI7_PG_Msk

#define	AFIO_EXTICR3_EXTI8_Pos (0U)

#define	AFIO_EXTICR3_EXTI8_Msk (0xFUL << AFIO_EXTICR3_EXTI8_Pos)

#define	AFIO_EXTICR3_EXTI8 AFIO_EXTICR3_EXTI8_Msk

#define	AFIO_EXTICR3_EXTI9_Pos (4U)

#define	AFIO_EXTICR3_EXTI9_Msk (0xFUL << AFIO_EXTICR3_EXTI9_Pos)

#define	AFIO_EXTICR3_EXTI9 AFIO_EXTICR3_EXTI9_Msk

#define	AFIO_EXTICR3_EXTI10_Pos (8U)

#define	AFIO_EXTICR3_EXTI10_Msk (0xFUL << AFIO_EXTICR3_EXTI10_Pos)

#define	AFIO_EXTICR3_EXTI10 AFIO_EXTICR3_EXTI10_Msk

#define	AFIO_EXTICR3_EXTI11_Pos (12U)

#define	AFIO_EXTICR3_EXTI11_Msk (0xFUL << AFIO_EXTICR3_EXTI11_Pos)

#define	AFIO_EXTICR3_EXTI11 AFIO_EXTICR3_EXTI11_Msk

#define	AFIO_EXTICR3_EXTI8_PA 0x00000000U

#define	AFIO_EXTICR3_EXTI8_PB_Pos (0U)

#define	AFIO_EXTICR3_EXTI8_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PB_Pos)

#define	AFIO_EXTICR3_EXTI8_PB AFIO_EXTICR3_EXTI8_PB_Msk

#define	AFIO_EXTICR3_EXTI8_PC_Pos (1U)

#define	AFIO_EXTICR3_EXTI8_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PC_Pos)

#define	AFIO_EXTICR3_EXTI8_PC AFIO_EXTICR3_EXTI8_PC_Msk

#define	AFIO_EXTICR3_EXTI8_PD_Pos (0U)

#define	AFIO_EXTICR3_EXTI8_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PD_Pos)

#define	AFIO_EXTICR3_EXTI8_PD AFIO_EXTICR3_EXTI8_PD_Msk

#define	AFIO_EXTICR3_EXTI8_PE_Pos (2U)

#define	AFIO_EXTICR3_EXTI8_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI8_PE_Pos)

#define	AFIO_EXTICR3_EXTI8_PE AFIO_EXTICR3_EXTI8_PE_Msk

#define	AFIO_EXTICR3_EXTI8_PF_Pos (0U)

#define	AFIO_EXTICR3_EXTI8_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI8_PF_Pos)

#define	AFIO_EXTICR3_EXTI8_PF AFIO_EXTICR3_EXTI8_PF_Msk

#define	AFIO_EXTICR3_EXTI8_PG_Pos (1U)

#define	AFIO_EXTICR3_EXTI8_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI8_PG_Pos)

#define	AFIO_EXTICR3_EXTI8_PG AFIO_EXTICR3_EXTI8_PG_Msk

#define	AFIO_EXTICR3_EXTI9_PA 0x00000000U

#define	AFIO_EXTICR3_EXTI9_PB_Pos (4U)

#define	AFIO_EXTICR3_EXTI9_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PB_Pos)

#define	AFIO_EXTICR3_EXTI9_PB AFIO_EXTICR3_EXTI9_PB_Msk

#define	AFIO_EXTICR3_EXTI9_PC_Pos (5U)

#define	AFIO_EXTICR3_EXTI9_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PC_Pos)

#define	AFIO_EXTICR3_EXTI9_PC AFIO_EXTICR3_EXTI9_PC_Msk

#define	AFIO_EXTICR3_EXTI9_PD_Pos (4U)

#define	AFIO_EXTICR3_EXTI9_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PD_Pos)

#define	AFIO_EXTICR3_EXTI9_PD AFIO_EXTICR3_EXTI9_PD_Msk

#define	AFIO_EXTICR3_EXTI9_PE_Pos (6U)

#define	AFIO_EXTICR3_EXTI9_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI9_PE_Pos)

#define	AFIO_EXTICR3_EXTI9_PE AFIO_EXTICR3_EXTI9_PE_Msk

#define	AFIO_EXTICR3_EXTI9_PF_Pos (4U)

#define	AFIO_EXTICR3_EXTI9_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI9_PF_Pos)

#define	AFIO_EXTICR3_EXTI9_PF AFIO_EXTICR3_EXTI9_PF_Msk

#define	AFIO_EXTICR3_EXTI9_PG_Pos (5U)

#define	AFIO_EXTICR3_EXTI9_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI9_PG_Pos)

#define	AFIO_EXTICR3_EXTI9_PG AFIO_EXTICR3_EXTI9_PG_Msk

#define	AFIO_EXTICR3_EXTI10_PA 0x00000000U

#define	AFIO_EXTICR3_EXTI10_PB_Pos (8U)

#define	AFIO_EXTICR3_EXTI10_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PB_Pos)

#define	AFIO_EXTICR3_EXTI10_PB AFIO_EXTICR3_EXTI10_PB_Msk

#define	AFIO_EXTICR3_EXTI10_PC_Pos (9U)

#define	AFIO_EXTICR3_EXTI10_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PC_Pos)

#define	AFIO_EXTICR3_EXTI10_PC AFIO_EXTICR3_EXTI10_PC_Msk

#define	AFIO_EXTICR3_EXTI10_PD_Pos (8U)

#define	AFIO_EXTICR3_EXTI10_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PD_Pos)

#define	AFIO_EXTICR3_EXTI10_PD AFIO_EXTICR3_EXTI10_PD_Msk

#define	AFIO_EXTICR3_EXTI10_PE_Pos (10U)

#define	AFIO_EXTICR3_EXTI10_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI10_PE_Pos)

#define	AFIO_EXTICR3_EXTI10_PE AFIO_EXTICR3_EXTI10_PE_Msk

#define	AFIO_EXTICR3_EXTI10_PF_Pos (8U)

#define	AFIO_EXTICR3_EXTI10_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI10_PF_Pos)

#define	AFIO_EXTICR3_EXTI10_PF AFIO_EXTICR3_EXTI10_PF_Msk

#define	AFIO_EXTICR3_EXTI10_PG_Pos (9U)

#define	AFIO_EXTICR3_EXTI10_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI10_PG_Pos)

#define	AFIO_EXTICR3_EXTI10_PG AFIO_EXTICR3_EXTI10_PG_Msk

#define	AFIO_EXTICR3_EXTI11_PA 0x00000000U

#define	AFIO_EXTICR3_EXTI11_PB_Pos (12U)

#define	AFIO_EXTICR3_EXTI11_PB_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PB_Pos)

#define	AFIO_EXTICR3_EXTI11_PB AFIO_EXTICR3_EXTI11_PB_Msk

#define	AFIO_EXTICR3_EXTI11_PC_Pos (13U)

#define	AFIO_EXTICR3_EXTI11_PC_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PC_Pos)

#define	AFIO_EXTICR3_EXTI11_PC AFIO_EXTICR3_EXTI11_PC_Msk

#define	AFIO_EXTICR3_EXTI11_PD_Pos (12U)

#define	AFIO_EXTICR3_EXTI11_PD_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PD_Pos)

#define	AFIO_EXTICR3_EXTI11_PD AFIO_EXTICR3_EXTI11_PD_Msk

#define	AFIO_EXTICR3_EXTI11_PE_Pos (14U)

#define	AFIO_EXTICR3_EXTI11_PE_Msk (0x1UL << AFIO_EXTICR3_EXTI11_PE_Pos)

#define	AFIO_EXTICR3_EXTI11_PE AFIO_EXTICR3_EXTI11_PE_Msk

#define	AFIO_EXTICR3_EXTI11_PF_Pos (12U)

#define	AFIO_EXTICR3_EXTI11_PF_Msk (0x5UL << AFIO_EXTICR3_EXTI11_PF_Pos)

#define	AFIO_EXTICR3_EXTI11_PF AFIO_EXTICR3_EXTI11_PF_Msk

#define	AFIO_EXTICR3_EXTI11_PG_Pos (13U)

#define	AFIO_EXTICR3_EXTI11_PG_Msk (0x3UL << AFIO_EXTICR3_EXTI11_PG_Pos)

#define	AFIO_EXTICR3_EXTI11_PG AFIO_EXTICR3_EXTI11_PG_Msk

#define	AFIO_EXTICR4_EXTI12_Pos (0U)

#define	AFIO_EXTICR4_EXTI12_Msk (0xFUL << AFIO_EXTICR4_EXTI12_Pos)

#define	AFIO_EXTICR4_EXTI12 AFIO_EXTICR4_EXTI12_Msk

#define	AFIO_EXTICR4_EXTI13_Pos (4U)

#define	AFIO_EXTICR4_EXTI13_Msk (0xFUL << AFIO_EXTICR4_EXTI13_Pos)

#define	AFIO_EXTICR4_EXTI13 AFIO_EXTICR4_EXTI13_Msk

#define	AFIO_EXTICR4_EXTI14_Pos (8U)

#define	AFIO_EXTICR4_EXTI14_Msk (0xFUL << AFIO_EXTICR4_EXTI14_Pos)

#define	AFIO_EXTICR4_EXTI14 AFIO_EXTICR4_EXTI14_Msk

#define	AFIO_EXTICR4_EXTI15_Pos (12U)

#define	AFIO_EXTICR4_EXTI15_Msk (0xFUL << AFIO_EXTICR4_EXTI15_Pos)

#define	AFIO_EXTICR4_EXTI15 AFIO_EXTICR4_EXTI15_Msk

#define	AFIO_EXTICR4_EXTI12_PA 0x00000000U

#define	AFIO_EXTICR4_EXTI12_PB_Pos (0U)

#define	AFIO_EXTICR4_EXTI12_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PB_Pos)

#define	AFIO_EXTICR4_EXTI12_PB AFIO_EXTICR4_EXTI12_PB_Msk

#define	AFIO_EXTICR4_EXTI12_PC_Pos (1U)

#define	AFIO_EXTICR4_EXTI12_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PC_Pos)

#define	AFIO_EXTICR4_EXTI12_PC AFIO_EXTICR4_EXTI12_PC_Msk

#define	AFIO_EXTICR4_EXTI12_PD_Pos (0U)

#define	AFIO_EXTICR4_EXTI12_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PD_Pos)

#define	AFIO_EXTICR4_EXTI12_PD AFIO_EXTICR4_EXTI12_PD_Msk

#define	AFIO_EXTICR4_EXTI12_PE_Pos (2U)

#define	AFIO_EXTICR4_EXTI12_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI12_PE_Pos)

#define	AFIO_EXTICR4_EXTI12_PE AFIO_EXTICR4_EXTI12_PE_Msk

#define	AFIO_EXTICR4_EXTI12_PF_Pos (0U)

#define	AFIO_EXTICR4_EXTI12_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI12_PF_Pos)

#define	AFIO_EXTICR4_EXTI12_PF AFIO_EXTICR4_EXTI12_PF_Msk

#define	AFIO_EXTICR4_EXTI12_PG_Pos (1U)

#define	AFIO_EXTICR4_EXTI12_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI12_PG_Pos)

#define	AFIO_EXTICR4_EXTI12_PG AFIO_EXTICR4_EXTI12_PG_Msk

#define	AFIO_EXTICR4_EXTI13_PA 0x00000000U

#define	AFIO_EXTICR4_EXTI13_PB_Pos (4U)

#define	AFIO_EXTICR4_EXTI13_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PB_Pos)

#define	AFIO_EXTICR4_EXTI13_PB AFIO_EXTICR4_EXTI13_PB_Msk

#define	AFIO_EXTICR4_EXTI13_PC_Pos (5U)

#define	AFIO_EXTICR4_EXTI13_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PC_Pos)

#define	AFIO_EXTICR4_EXTI13_PC AFIO_EXTICR4_EXTI13_PC_Msk

#define	AFIO_EXTICR4_EXTI13_PD_Pos (4U)

#define	AFIO_EXTICR4_EXTI13_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PD_Pos)

#define	AFIO_EXTICR4_EXTI13_PD AFIO_EXTICR4_EXTI13_PD_Msk

#define	AFIO_EXTICR4_EXTI13_PE_Pos (6U)

#define	AFIO_EXTICR4_EXTI13_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI13_PE_Pos)

#define	AFIO_EXTICR4_EXTI13_PE AFIO_EXTICR4_EXTI13_PE_Msk

#define	AFIO_EXTICR4_EXTI13_PF_Pos (4U)

#define	AFIO_EXTICR4_EXTI13_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI13_PF_Pos)

#define	AFIO_EXTICR4_EXTI13_PF AFIO_EXTICR4_EXTI13_PF_Msk

#define	AFIO_EXTICR4_EXTI13_PG_Pos (5U)

#define	AFIO_EXTICR4_EXTI13_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI13_PG_Pos)

#define	AFIO_EXTICR4_EXTI13_PG AFIO_EXTICR4_EXTI13_PG_Msk

#define	AFIO_EXTICR4_EXTI14_PA 0x00000000U

#define	AFIO_EXTICR4_EXTI14_PB_Pos (8U)

#define	AFIO_EXTICR4_EXTI14_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PB_Pos)

#define	AFIO_EXTICR4_EXTI14_PB AFIO_EXTICR4_EXTI14_PB_Msk

#define	AFIO_EXTICR4_EXTI14_PC_Pos (9U)

#define	AFIO_EXTICR4_EXTI14_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PC_Pos)

#define	AFIO_EXTICR4_EXTI14_PC AFIO_EXTICR4_EXTI14_PC_Msk

#define	AFIO_EXTICR4_EXTI14_PD_Pos (8U)

#define	AFIO_EXTICR4_EXTI14_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PD_Pos)

#define	AFIO_EXTICR4_EXTI14_PD AFIO_EXTICR4_EXTI14_PD_Msk

#define	AFIO_EXTICR4_EXTI14_PE_Pos (10U)

#define	AFIO_EXTICR4_EXTI14_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI14_PE_Pos)

#define	AFIO_EXTICR4_EXTI14_PE AFIO_EXTICR4_EXTI14_PE_Msk

#define	AFIO_EXTICR4_EXTI14_PF_Pos (8U)

#define	AFIO_EXTICR4_EXTI14_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI14_PF_Pos)

#define	AFIO_EXTICR4_EXTI14_PF AFIO_EXTICR4_EXTI14_PF_Msk

#define	AFIO_EXTICR4_EXTI14_PG_Pos (9U)

#define	AFIO_EXTICR4_EXTI14_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI14_PG_Pos)

#define	AFIO_EXTICR4_EXTI14_PG AFIO_EXTICR4_EXTI14_PG_Msk

#define	AFIO_EXTICR4_EXTI15_PA 0x00000000U

#define	AFIO_EXTICR4_EXTI15_PB_Pos (12U)

#define	AFIO_EXTICR4_EXTI15_PB_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PB_Pos)

#define	AFIO_EXTICR4_EXTI15_PB AFIO_EXTICR4_EXTI15_PB_Msk

#define	AFIO_EXTICR4_EXTI15_PC_Pos (13U)

#define	AFIO_EXTICR4_EXTI15_PC_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PC_Pos)

#define	AFIO_EXTICR4_EXTI15_PC AFIO_EXTICR4_EXTI15_PC_Msk

#define	AFIO_EXTICR4_EXTI15_PD_Pos (12U)

#define	AFIO_EXTICR4_EXTI15_PD_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PD_Pos)

#define	AFIO_EXTICR4_EXTI15_PD AFIO_EXTICR4_EXTI15_PD_Msk

#define	AFIO_EXTICR4_EXTI15_PE_Pos (14U)

#define	AFIO_EXTICR4_EXTI15_PE_Msk (0x1UL << AFIO_EXTICR4_EXTI15_PE_Pos)

#define	AFIO_EXTICR4_EXTI15_PE AFIO_EXTICR4_EXTI15_PE_Msk

#define	AFIO_EXTICR4_EXTI15_PF_Pos (12U)

#define	AFIO_EXTICR4_EXTI15_PF_Msk (0x5UL << AFIO_EXTICR4_EXTI15_PF_Pos)

#define	AFIO_EXTICR4_EXTI15_PF AFIO_EXTICR4_EXTI15_PF_Msk

#define	AFIO_EXTICR4_EXTI15_PG_Pos (13U)

#define	AFIO_EXTICR4_EXTI15_PG_Msk (0x3UL << AFIO_EXTICR4_EXTI15_PG_Pos)

#define	AFIO_EXTICR4_EXTI15_PG AFIO_EXTICR4_EXTI15_PG_Msk

#define	EXTI_IMR_MR0_Pos (0U)

#define	EXTI_IMR_MR0_Msk (0x1UL << EXTI_IMR_MR0_Pos)

#define	EXTI_IMR_MR0 EXTI_IMR_MR0_Msk

#define	EXTI_IMR_MR1_Pos (1U)

#define	EXTI_IMR_MR1_Msk (0x1UL << EXTI_IMR_MR1_Pos)

#define	EXTI_IMR_MR1 EXTI_IMR_MR1_Msk

#define	EXTI_IMR_MR2_Pos (2U)

#define	EXTI_IMR_MR2_Msk (0x1UL << EXTI_IMR_MR2_Pos)

#define	EXTI_IMR_MR2 EXTI_IMR_MR2_Msk

#define	EXTI_IMR_MR3_Pos (3U)

#define	EXTI_IMR_MR3_Msk (0x1UL << EXTI_IMR_MR3_Pos)

#define	EXTI_IMR_MR3 EXTI_IMR_MR3_Msk

#define	EXTI_IMR_MR4_Pos (4U)

#define	EXTI_IMR_MR4_Msk (0x1UL << EXTI_IMR_MR4_Pos)

#define	EXTI_IMR_MR4 EXTI_IMR_MR4_Msk

#define	EXTI_IMR_MR5_Pos (5U)

#define	EXTI_IMR_MR5_Msk (0x1UL << EXTI_IMR_MR5_Pos)

#define	EXTI_IMR_MR5 EXTI_IMR_MR5_Msk

#define	EXTI_IMR_MR6_Pos (6U)

#define	EXTI_IMR_MR6_Msk (0x1UL << EXTI_IMR_MR6_Pos)

#define	EXTI_IMR_MR6 EXTI_IMR_MR6_Msk

#define	EXTI_IMR_MR7_Pos (7U)

#define	EXTI_IMR_MR7_Msk (0x1UL << EXTI_IMR_MR7_Pos)

#define	EXTI_IMR_MR7 EXTI_IMR_MR7_Msk

#define	EXTI_IMR_MR8_Pos (8U)

#define	EXTI_IMR_MR8_Msk (0x1UL << EXTI_IMR_MR8_Pos)

#define	EXTI_IMR_MR8 EXTI_IMR_MR8_Msk

#define	EXTI_IMR_MR9_Pos (9U)

#define	EXTI_IMR_MR9_Msk (0x1UL << EXTI_IMR_MR9_Pos)

#define	EXTI_IMR_MR9 EXTI_IMR_MR9_Msk

#define	EXTI_IMR_MR10_Pos (10U)

#define	EXTI_IMR_MR10_Msk (0x1UL << EXTI_IMR_MR10_Pos)

#define	EXTI_IMR_MR10 EXTI_IMR_MR10_Msk

#define	EXTI_IMR_MR11_Pos (11U)

#define	EXTI_IMR_MR11_Msk (0x1UL << EXTI_IMR_MR11_Pos)

#define	EXTI_IMR_MR11 EXTI_IMR_MR11_Msk

#define	EXTI_IMR_MR12_Pos (12U)

#define	EXTI_IMR_MR12_Msk (0x1UL << EXTI_IMR_MR12_Pos)

#define	EXTI_IMR_MR12 EXTI_IMR_MR12_Msk

#define	EXTI_IMR_MR13_Pos (13U)

#define	EXTI_IMR_MR13_Msk (0x1UL << EXTI_IMR_MR13_Pos)

#define	EXTI_IMR_MR13 EXTI_IMR_MR13_Msk

#define	EXTI_IMR_MR14_Pos (14U)

#define	EXTI_IMR_MR14_Msk (0x1UL << EXTI_IMR_MR14_Pos)

#define	EXTI_IMR_MR14 EXTI_IMR_MR14_Msk

#define	EXTI_IMR_MR15_Pos (15U)

#define	EXTI_IMR_MR15_Msk (0x1UL << EXTI_IMR_MR15_Pos)

#define	EXTI_IMR_MR15 EXTI_IMR_MR15_Msk

#define	EXTI_IMR_MR16_Pos (16U)

#define	EXTI_IMR_MR16_Msk (0x1UL << EXTI_IMR_MR16_Pos)

#define	EXTI_IMR_MR16 EXTI_IMR_MR16_Msk

#define	EXTI_IMR_MR17_Pos (17U)

#define	EXTI_IMR_MR17_Msk (0x1UL << EXTI_IMR_MR17_Pos)

#define	EXTI_IMR_MR17 EXTI_IMR_MR17_Msk

#define	EXTI_IMR_MR18_Pos (18U)

#define	EXTI_IMR_MR18_Msk (0x1UL << EXTI_IMR_MR18_Pos)

#define	EXTI_IMR_MR18 EXTI_IMR_MR18_Msk

#define	EXTI_IMR_MR19_Pos (19U)

#define	EXTI_IMR_MR19_Msk (0x1UL << EXTI_IMR_MR19_Pos)

#define	EXTI_IMR_MR19 EXTI_IMR_MR19_Msk

#define	EXTI_IMR_IM0 EXTI_IMR_MR0

#define	EXTI_IMR_IM1 EXTI_IMR_MR1

#define	EXTI_IMR_IM2 EXTI_IMR_MR2

#define	EXTI_IMR_IM3 EXTI_IMR_MR3

#define	EXTI_IMR_IM4 EXTI_IMR_MR4

#define	EXTI_IMR_IM5 EXTI_IMR_MR5

#define	EXTI_IMR_IM6 EXTI_IMR_MR6

#define	EXTI_IMR_IM7 EXTI_IMR_MR7

#define	EXTI_IMR_IM8 EXTI_IMR_MR8

#define	EXTI_IMR_IM9 EXTI_IMR_MR9

#define	EXTI_IMR_IM10 EXTI_IMR_MR10

#define	EXTI_IMR_IM11 EXTI_IMR_MR11

#define	EXTI_IMR_IM12 EXTI_IMR_MR12

#define	EXTI_IMR_IM13 EXTI_IMR_MR13

#define	EXTI_IMR_IM14 EXTI_IMR_MR14

#define	EXTI_IMR_IM15 EXTI_IMR_MR15

#define	EXTI_IMR_IM16 EXTI_IMR_MR16

#define	EXTI_IMR_IM17 EXTI_IMR_MR17

#define	EXTI_IMR_IM18 EXTI_IMR_MR18

#define	EXTI_IMR_IM19 EXTI_IMR_MR19

#define	EXTI_IMR_IM 0x000FFFFFU

#define	EXTI_EMR_MR0_Pos (0U)

#define	EXTI_EMR_MR0_Msk (0x1UL << EXTI_EMR_MR0_Pos)

#define	EXTI_EMR_MR0 EXTI_EMR_MR0_Msk

#define	EXTI_EMR_MR1_Pos (1U)

#define	EXTI_EMR_MR1_Msk (0x1UL << EXTI_EMR_MR1_Pos)

#define	EXTI_EMR_MR1 EXTI_EMR_MR1_Msk

#define	EXTI_EMR_MR2_Pos (2U)

#define	EXTI_EMR_MR2_Msk (0x1UL << EXTI_EMR_MR2_Pos)

#define	EXTI_EMR_MR2 EXTI_EMR_MR2_Msk

#define	EXTI_EMR_MR3_Pos (3U)

#define	EXTI_EMR_MR3_Msk (0x1UL << EXTI_EMR_MR3_Pos)

#define	EXTI_EMR_MR3 EXTI_EMR_MR3_Msk

#define	EXTI_EMR_MR4_Pos (4U)

#define	EXTI_EMR_MR4_Msk (0x1UL << EXTI_EMR_MR4_Pos)

#define	EXTI_EMR_MR4 EXTI_EMR_MR4_Msk

#define	EXTI_EMR_MR5_Pos (5U)

#define	EXTI_EMR_MR5_Msk (0x1UL << EXTI_EMR_MR5_Pos)

#define	EXTI_EMR_MR5 EXTI_EMR_MR5_Msk

#define	EXTI_EMR_MR6_Pos (6U)

#define	EXTI_EMR_MR6_Msk (0x1UL << EXTI_EMR_MR6_Pos)

#define	EXTI_EMR_MR6 EXTI_EMR_MR6_Msk

#define	EXTI_EMR_MR7_Pos (7U)

#define	EXTI_EMR_MR7_Msk (0x1UL << EXTI_EMR_MR7_Pos)

#define	EXTI_EMR_MR7 EXTI_EMR_MR7_Msk

#define	EXTI_EMR_MR8_Pos (8U)

#define	EXTI_EMR_MR8_Msk (0x1UL << EXTI_EMR_MR8_Pos)

#define	EXTI_EMR_MR8 EXTI_EMR_MR8_Msk

#define	EXTI_EMR_MR9_Pos (9U)

#define	EXTI_EMR_MR9_Msk (0x1UL << EXTI_EMR_MR9_Pos)

#define	EXTI_EMR_MR9 EXTI_EMR_MR9_Msk

#define	EXTI_EMR_MR10_Pos (10U)

#define	EXTI_EMR_MR10_Msk (0x1UL << EXTI_EMR_MR10_Pos)

#define	EXTI_EMR_MR10 EXTI_EMR_MR10_Msk

#define	EXTI_EMR_MR11_Pos (11U)

#define	EXTI_EMR_MR11_Msk (0x1UL << EXTI_EMR_MR11_Pos)

#define	EXTI_EMR_MR11 EXTI_EMR_MR11_Msk

#define	EXTI_EMR_MR12_Pos (12U)

#define	EXTI_EMR_MR12_Msk (0x1UL << EXTI_EMR_MR12_Pos)

#define	EXTI_EMR_MR12 EXTI_EMR_MR12_Msk

#define	EXTI_EMR_MR13_Pos (13U)

#define	EXTI_EMR_MR13_Msk (0x1UL << EXTI_EMR_MR13_Pos)

#define	EXTI_EMR_MR13 EXTI_EMR_MR13_Msk

#define	EXTI_EMR_MR14_Pos (14U)

#define	EXTI_EMR_MR14_Msk (0x1UL << EXTI_EMR_MR14_Pos)

#define	EXTI_EMR_MR14 EXTI_EMR_MR14_Msk

#define	EXTI_EMR_MR15_Pos (15U)

#define	EXTI_EMR_MR15_Msk (0x1UL << EXTI_EMR_MR15_Pos)

#define	EXTI_EMR_MR15 EXTI_EMR_MR15_Msk

#define	EXTI_EMR_MR16_Pos (16U)

#define	EXTI_EMR_MR16_Msk (0x1UL << EXTI_EMR_MR16_Pos)

#define	EXTI_EMR_MR16 EXTI_EMR_MR16_Msk

#define	EXTI_EMR_MR17_Pos (17U)

#define	EXTI_EMR_MR17_Msk (0x1UL << EXTI_EMR_MR17_Pos)

#define	EXTI_EMR_MR17 EXTI_EMR_MR17_Msk

#define	EXTI_EMR_MR18_Pos (18U)

#define	EXTI_EMR_MR18_Msk (0x1UL << EXTI_EMR_MR18_Pos)

#define	EXTI_EMR_MR18 EXTI_EMR_MR18_Msk

#define	EXTI_EMR_MR19_Pos (19U)

#define	EXTI_EMR_MR19_Msk (0x1UL << EXTI_EMR_MR19_Pos)

#define	EXTI_EMR_MR19 EXTI_EMR_MR19_Msk

#define	EXTI_EMR_EM0 EXTI_EMR_MR0

#define	EXTI_EMR_EM1 EXTI_EMR_MR1

#define	EXTI_EMR_EM2 EXTI_EMR_MR2

#define	EXTI_EMR_EM3 EXTI_EMR_MR3

#define	EXTI_EMR_EM4 EXTI_EMR_MR4

#define	EXTI_EMR_EM5 EXTI_EMR_MR5

#define	EXTI_EMR_EM6 EXTI_EMR_MR6

#define	EXTI_EMR_EM7 EXTI_EMR_MR7

#define	EXTI_EMR_EM8 EXTI_EMR_MR8

#define	EXTI_EMR_EM9 EXTI_EMR_MR9

#define	EXTI_EMR_EM10 EXTI_EMR_MR10

#define	EXTI_EMR_EM11 EXTI_EMR_MR11

#define	EXTI_EMR_EM12 EXTI_EMR_MR12

#define	EXTI_EMR_EM13 EXTI_EMR_MR13

#define	EXTI_EMR_EM14 EXTI_EMR_MR14

#define	EXTI_EMR_EM15 EXTI_EMR_MR15

#define	EXTI_EMR_EM16 EXTI_EMR_MR16

#define	EXTI_EMR_EM17 EXTI_EMR_MR17

#define	EXTI_EMR_EM18 EXTI_EMR_MR18

#define	EXTI_EMR_EM19 EXTI_EMR_MR19

#define	EXTI_RTSR_TR0_Pos (0U)

#define	EXTI_RTSR_TR0_Msk (0x1UL << EXTI_RTSR_TR0_Pos)

#define	EXTI_RTSR_TR0 EXTI_RTSR_TR0_Msk

#define	EXTI_RTSR_TR1_Pos (1U)

#define	EXTI_RTSR_TR1_Msk (0x1UL << EXTI_RTSR_TR1_Pos)

#define	EXTI_RTSR_TR1 EXTI_RTSR_TR1_Msk

#define	EXTI_RTSR_TR2_Pos (2U)

#define	EXTI_RTSR_TR2_Msk (0x1UL << EXTI_RTSR_TR2_Pos)

#define	EXTI_RTSR_TR2 EXTI_RTSR_TR2_Msk

#define	EXTI_RTSR_TR3_Pos (3U)

#define	EXTI_RTSR_TR3_Msk (0x1UL << EXTI_RTSR_TR3_Pos)

#define	EXTI_RTSR_TR3 EXTI_RTSR_TR3_Msk

#define	EXTI_RTSR_TR4_Pos (4U)

#define	EXTI_RTSR_TR4_Msk (0x1UL << EXTI_RTSR_TR4_Pos)

#define	EXTI_RTSR_TR4 EXTI_RTSR_TR4_Msk

#define	EXTI_RTSR_TR5_Pos (5U)

#define	EXTI_RTSR_TR5_Msk (0x1UL << EXTI_RTSR_TR5_Pos)

#define	EXTI_RTSR_TR5 EXTI_RTSR_TR5_Msk

#define	EXTI_RTSR_TR6_Pos (6U)

#define	EXTI_RTSR_TR6_Msk (0x1UL << EXTI_RTSR_TR6_Pos)

#define	EXTI_RTSR_TR6 EXTI_RTSR_TR6_Msk

#define	EXTI_RTSR_TR7_Pos (7U)

#define	EXTI_RTSR_TR7_Msk (0x1UL << EXTI_RTSR_TR7_Pos)

#define	EXTI_RTSR_TR7 EXTI_RTSR_TR7_Msk

#define	EXTI_RTSR_TR8_Pos (8U)

#define	EXTI_RTSR_TR8_Msk (0x1UL << EXTI_RTSR_TR8_Pos)

#define	EXTI_RTSR_TR8 EXTI_RTSR_TR8_Msk

#define	EXTI_RTSR_TR9_Pos (9U)

#define	EXTI_RTSR_TR9_Msk (0x1UL << EXTI_RTSR_TR9_Pos)

#define	EXTI_RTSR_TR9 EXTI_RTSR_TR9_Msk

#define	EXTI_RTSR_TR10_Pos (10U)

#define	EXTI_RTSR_TR10_Msk (0x1UL << EXTI_RTSR_TR10_Pos)

#define	EXTI_RTSR_TR10 EXTI_RTSR_TR10_Msk

#define	EXTI_RTSR_TR11_Pos (11U)

#define	EXTI_RTSR_TR11_Msk (0x1UL << EXTI_RTSR_TR11_Pos)

#define	EXTI_RTSR_TR11 EXTI_RTSR_TR11_Msk

#define	EXTI_RTSR_TR12_Pos (12U)

#define	EXTI_RTSR_TR12_Msk (0x1UL << EXTI_RTSR_TR12_Pos)

#define	EXTI_RTSR_TR12 EXTI_RTSR_TR12_Msk

#define	EXTI_RTSR_TR13_Pos (13U)

#define	EXTI_RTSR_TR13_Msk (0x1UL << EXTI_RTSR_TR13_Pos)

#define	EXTI_RTSR_TR13 EXTI_RTSR_TR13_Msk

#define	EXTI_RTSR_TR14_Pos (14U)

#define	EXTI_RTSR_TR14_Msk (0x1UL << EXTI_RTSR_TR14_Pos)

#define	EXTI_RTSR_TR14 EXTI_RTSR_TR14_Msk

#define	EXTI_RTSR_TR15_Pos (15U)

#define	EXTI_RTSR_TR15_Msk (0x1UL << EXTI_RTSR_TR15_Pos)

#define	EXTI_RTSR_TR15 EXTI_RTSR_TR15_Msk

#define	EXTI_RTSR_TR16_Pos (16U)

#define	EXTI_RTSR_TR16_Msk (0x1UL << EXTI_RTSR_TR16_Pos)

#define	EXTI_RTSR_TR16 EXTI_RTSR_TR16_Msk

#define	EXTI_RTSR_TR17_Pos (17U)

#define	EXTI_RTSR_TR17_Msk (0x1UL << EXTI_RTSR_TR17_Pos)

#define	EXTI_RTSR_TR17 EXTI_RTSR_TR17_Msk

#define	EXTI_RTSR_TR18_Pos (18U)

#define	EXTI_RTSR_TR18_Msk (0x1UL << EXTI_RTSR_TR18_Pos)

#define	EXTI_RTSR_TR18 EXTI_RTSR_TR18_Msk

#define	EXTI_RTSR_TR19_Pos (19U)

#define	EXTI_RTSR_TR19_Msk (0x1UL << EXTI_RTSR_TR19_Pos)

#define	EXTI_RTSR_TR19 EXTI_RTSR_TR19_Msk

#define	EXTI_RTSR_RT0 EXTI_RTSR_TR0

#define	EXTI_RTSR_RT1 EXTI_RTSR_TR1

#define	EXTI_RTSR_RT2 EXTI_RTSR_TR2

#define	EXTI_RTSR_RT3 EXTI_RTSR_TR3

#define	EXTI_RTSR_RT4 EXTI_RTSR_TR4

#define	EXTI_RTSR_RT5 EXTI_RTSR_TR5

#define	EXTI_RTSR_RT6 EXTI_RTSR_TR6

#define	EXTI_RTSR_RT7 EXTI_RTSR_TR7

#define	EXTI_RTSR_RT8 EXTI_RTSR_TR8

#define	EXTI_RTSR_RT9 EXTI_RTSR_TR9

#define	EXTI_RTSR_RT10 EXTI_RTSR_TR10

#define	EXTI_RTSR_RT11 EXTI_RTSR_TR11

#define	EXTI_RTSR_RT12 EXTI_RTSR_TR12

#define	EXTI_RTSR_RT13 EXTI_RTSR_TR13

#define	EXTI_RTSR_RT14 EXTI_RTSR_TR14

#define	EXTI_RTSR_RT15 EXTI_RTSR_TR15

#define	EXTI_RTSR_RT16 EXTI_RTSR_TR16

#define	EXTI_RTSR_RT17 EXTI_RTSR_TR17

#define	EXTI_RTSR_RT18 EXTI_RTSR_TR18

#define	EXTI_RTSR_RT19 EXTI_RTSR_TR19

#define	EXTI_FTSR_TR0_Pos (0U)

#define	EXTI_FTSR_TR0_Msk (0x1UL << EXTI_FTSR_TR0_Pos)

#define	EXTI_FTSR_TR0 EXTI_FTSR_TR0_Msk

#define	EXTI_FTSR_TR1_Pos (1U)

#define	EXTI_FTSR_TR1_Msk (0x1UL << EXTI_FTSR_TR1_Pos)

#define	EXTI_FTSR_TR1 EXTI_FTSR_TR1_Msk

#define	EXTI_FTSR_TR2_Pos (2U)

#define	EXTI_FTSR_TR2_Msk (0x1UL << EXTI_FTSR_TR2_Pos)

#define	EXTI_FTSR_TR2 EXTI_FTSR_TR2_Msk

#define	EXTI_FTSR_TR3_Pos (3U)

#define	EXTI_FTSR_TR3_Msk (0x1UL << EXTI_FTSR_TR3_Pos)

#define	EXTI_FTSR_TR3 EXTI_FTSR_TR3_Msk

#define	EXTI_FTSR_TR4_Pos (4U)

#define	EXTI_FTSR_TR4_Msk (0x1UL << EXTI_FTSR_TR4_Pos)

#define	EXTI_FTSR_TR4 EXTI_FTSR_TR4_Msk

#define	EXTI_FTSR_TR5_Pos (5U)

#define	EXTI_FTSR_TR5_Msk (0x1UL << EXTI_FTSR_TR5_Pos)

#define	EXTI_FTSR_TR5 EXTI_FTSR_TR5_Msk

#define	EXTI_FTSR_TR6_Pos (6U)

#define	EXTI_FTSR_TR6_Msk (0x1UL << EXTI_FTSR_TR6_Pos)

#define	EXTI_FTSR_TR6 EXTI_FTSR_TR6_Msk

#define	EXTI_FTSR_TR7_Pos (7U)

#define	EXTI_FTSR_TR7_Msk (0x1UL << EXTI_FTSR_TR7_Pos)

#define	EXTI_FTSR_TR7 EXTI_FTSR_TR7_Msk

#define	EXTI_FTSR_TR8_Pos (8U)

#define	EXTI_FTSR_TR8_Msk (0x1UL << EXTI_FTSR_TR8_Pos)

#define	EXTI_FTSR_TR8 EXTI_FTSR_TR8_Msk

#define	EXTI_FTSR_TR9_Pos (9U)

#define	EXTI_FTSR_TR9_Msk (0x1UL << EXTI_FTSR_TR9_Pos)

#define	EXTI_FTSR_TR9 EXTI_FTSR_TR9_Msk

#define	EXTI_FTSR_TR10_Pos (10U)

#define	EXTI_FTSR_TR10_Msk (0x1UL << EXTI_FTSR_TR10_Pos)

#define	EXTI_FTSR_TR10 EXTI_FTSR_TR10_Msk

#define	EXTI_FTSR_TR11_Pos (11U)

#define	EXTI_FTSR_TR11_Msk (0x1UL << EXTI_FTSR_TR11_Pos)

#define	EXTI_FTSR_TR11 EXTI_FTSR_TR11_Msk

#define	EXTI_FTSR_TR12_Pos (12U)

#define	EXTI_FTSR_TR12_Msk (0x1UL << EXTI_FTSR_TR12_Pos)

#define	EXTI_FTSR_TR12 EXTI_FTSR_TR12_Msk

#define	EXTI_FTSR_TR13_Pos (13U)

#define	EXTI_FTSR_TR13_Msk (0x1UL << EXTI_FTSR_TR13_Pos)

#define	EXTI_FTSR_TR13 EXTI_FTSR_TR13_Msk

#define	EXTI_FTSR_TR14_Pos (14U)

#define	EXTI_FTSR_TR14_Msk (0x1UL << EXTI_FTSR_TR14_Pos)

#define	EXTI_FTSR_TR14 EXTI_FTSR_TR14_Msk

#define	EXTI_FTSR_TR15_Pos (15U)

#define	EXTI_FTSR_TR15_Msk (0x1UL << EXTI_FTSR_TR15_Pos)

#define	EXTI_FTSR_TR15 EXTI_FTSR_TR15_Msk

#define	EXTI_FTSR_TR16_Pos (16U)

#define	EXTI_FTSR_TR16_Msk (0x1UL << EXTI_FTSR_TR16_Pos)

#define	EXTI_FTSR_TR16 EXTI_FTSR_TR16_Msk

#define	EXTI_FTSR_TR17_Pos (17U)

#define	EXTI_FTSR_TR17_Msk (0x1UL << EXTI_FTSR_TR17_Pos)

#define	EXTI_FTSR_TR17 EXTI_FTSR_TR17_Msk

#define	EXTI_FTSR_TR18_Pos (18U)

#define	EXTI_FTSR_TR18_Msk (0x1UL << EXTI_FTSR_TR18_Pos)

#define	EXTI_FTSR_TR18 EXTI_FTSR_TR18_Msk

#define	EXTI_FTSR_TR19_Pos (19U)

#define	EXTI_FTSR_TR19_Msk (0x1UL << EXTI_FTSR_TR19_Pos)

#define	EXTI_FTSR_TR19 EXTI_FTSR_TR19_Msk

#define	EXTI_FTSR_FT0 EXTI_FTSR_TR0

#define	EXTI_FTSR_FT1 EXTI_FTSR_TR1

#define	EXTI_FTSR_FT2 EXTI_FTSR_TR2

#define	EXTI_FTSR_FT3 EXTI_FTSR_TR3

#define	EXTI_FTSR_FT4 EXTI_FTSR_TR4

#define	EXTI_FTSR_FT5 EXTI_FTSR_TR5

#define	EXTI_FTSR_FT6 EXTI_FTSR_TR6

#define	EXTI_FTSR_FT7 EXTI_FTSR_TR7

#define	EXTI_FTSR_FT8 EXTI_FTSR_TR8

#define	EXTI_FTSR_FT9 EXTI_FTSR_TR9

#define	EXTI_FTSR_FT10 EXTI_FTSR_TR10

#define	EXTI_FTSR_FT11 EXTI_FTSR_TR11

#define	EXTI_FTSR_FT12 EXTI_FTSR_TR12

#define	EXTI_FTSR_FT13 EXTI_FTSR_TR13

#define	EXTI_FTSR_FT14 EXTI_FTSR_TR14

#define	EXTI_FTSR_FT15 EXTI_FTSR_TR15

#define	EXTI_FTSR_FT16 EXTI_FTSR_TR16

#define	EXTI_FTSR_FT17 EXTI_FTSR_TR17

#define	EXTI_FTSR_FT18 EXTI_FTSR_TR18

#define	EXTI_FTSR_FT19 EXTI_FTSR_TR19

#define	EXTI_SWIER_SWIER0_Pos (0U)

#define	EXTI_SWIER_SWIER0_Msk (0x1UL << EXTI_SWIER_SWIER0_Pos)

#define	EXTI_SWIER_SWIER0 EXTI_SWIER_SWIER0_Msk

#define	EXTI_SWIER_SWIER1_Pos (1U)

#define	EXTI_SWIER_SWIER1_Msk (0x1UL << EXTI_SWIER_SWIER1_Pos)

#define	EXTI_SWIER_SWIER1 EXTI_SWIER_SWIER1_Msk

#define	EXTI_SWIER_SWIER2_Pos (2U)

#define	EXTI_SWIER_SWIER2_Msk (0x1UL << EXTI_SWIER_SWIER2_Pos)

#define	EXTI_SWIER_SWIER2 EXTI_SWIER_SWIER2_Msk

#define	EXTI_SWIER_SWIER3_Pos (3U)

#define	EXTI_SWIER_SWIER3_Msk (0x1UL << EXTI_SWIER_SWIER3_Pos)

#define	EXTI_SWIER_SWIER3 EXTI_SWIER_SWIER3_Msk

#define	EXTI_SWIER_SWIER4_Pos (4U)

#define	EXTI_SWIER_SWIER4_Msk (0x1UL << EXTI_SWIER_SWIER4_Pos)

#define	EXTI_SWIER_SWIER4 EXTI_SWIER_SWIER4_Msk

#define	EXTI_SWIER_SWIER5_Pos (5U)

#define	EXTI_SWIER_SWIER5_Msk (0x1UL << EXTI_SWIER_SWIER5_Pos)

#define	EXTI_SWIER_SWIER5 EXTI_SWIER_SWIER5_Msk

#define	EXTI_SWIER_SWIER6_Pos (6U)

#define	EXTI_SWIER_SWIER6_Msk (0x1UL << EXTI_SWIER_SWIER6_Pos)

#define	EXTI_SWIER_SWIER6 EXTI_SWIER_SWIER6_Msk

#define	EXTI_SWIER_SWIER7_Pos (7U)

#define	EXTI_SWIER_SWIER7_Msk (0x1UL << EXTI_SWIER_SWIER7_Pos)

#define	EXTI_SWIER_SWIER7 EXTI_SWIER_SWIER7_Msk

#define	EXTI_SWIER_SWIER8_Pos (8U)

#define	EXTI_SWIER_SWIER8_Msk (0x1UL << EXTI_SWIER_SWIER8_Pos)

#define	EXTI_SWIER_SWIER8 EXTI_SWIER_SWIER8_Msk

#define	EXTI_SWIER_SWIER9_Pos (9U)

#define	EXTI_SWIER_SWIER9_Msk (0x1UL << EXTI_SWIER_SWIER9_Pos)

#define	EXTI_SWIER_SWIER9 EXTI_SWIER_SWIER9_Msk

#define	EXTI_SWIER_SWIER10_Pos (10U)

#define	EXTI_SWIER_SWIER10_Msk (0x1UL << EXTI_SWIER_SWIER10_Pos)

#define	EXTI_SWIER_SWIER10 EXTI_SWIER_SWIER10_Msk

#define	EXTI_SWIER_SWIER11_Pos (11U)

#define	EXTI_SWIER_SWIER11_Msk (0x1UL << EXTI_SWIER_SWIER11_Pos)

#define	EXTI_SWIER_SWIER11 EXTI_SWIER_SWIER11_Msk

#define	EXTI_SWIER_SWIER12_Pos (12U)

#define	EXTI_SWIER_SWIER12_Msk (0x1UL << EXTI_SWIER_SWIER12_Pos)

#define	EXTI_SWIER_SWIER12 EXTI_SWIER_SWIER12_Msk

#define	EXTI_SWIER_SWIER13_Pos (13U)

#define	EXTI_SWIER_SWIER13_Msk (0x1UL << EXTI_SWIER_SWIER13_Pos)

#define	EXTI_SWIER_SWIER13 EXTI_SWIER_SWIER13_Msk

#define	EXTI_SWIER_SWIER14_Pos (14U)

#define	EXTI_SWIER_SWIER14_Msk (0x1UL << EXTI_SWIER_SWIER14_Pos)

#define	EXTI_SWIER_SWIER14 EXTI_SWIER_SWIER14_Msk

#define	EXTI_SWIER_SWIER15_Pos (15U)

#define	EXTI_SWIER_SWIER15_Msk (0x1UL << EXTI_SWIER_SWIER15_Pos)

#define	EXTI_SWIER_SWIER15 EXTI_SWIER_SWIER15_Msk

#define	EXTI_SWIER_SWIER16_Pos (16U)

#define	EXTI_SWIER_SWIER16_Msk (0x1UL << EXTI_SWIER_SWIER16_Pos)

#define	EXTI_SWIER_SWIER16 EXTI_SWIER_SWIER16_Msk

#define	EXTI_SWIER_SWIER17_Pos (17U)

#define	EXTI_SWIER_SWIER17_Msk (0x1UL << EXTI_SWIER_SWIER17_Pos)

#define	EXTI_SWIER_SWIER17 EXTI_SWIER_SWIER17_Msk

#define	EXTI_SWIER_SWIER18_Pos (18U)

#define	EXTI_SWIER_SWIER18_Msk (0x1UL << EXTI_SWIER_SWIER18_Pos)

#define	EXTI_SWIER_SWIER18 EXTI_SWIER_SWIER18_Msk

#define	EXTI_SWIER_SWIER19_Pos (19U)

#define	EXTI_SWIER_SWIER19_Msk (0x1UL << EXTI_SWIER_SWIER19_Pos)

#define	EXTI_SWIER_SWIER19 EXTI_SWIER_SWIER19_Msk

#define	EXTI_SWIER_SWI0 EXTI_SWIER_SWIER0

#define	EXTI_SWIER_SWI1 EXTI_SWIER_SWIER1

#define	EXTI_SWIER_SWI2 EXTI_SWIER_SWIER2

#define	EXTI_SWIER_SWI3 EXTI_SWIER_SWIER3

#define	EXTI_SWIER_SWI4 EXTI_SWIER_SWIER4

#define	EXTI_SWIER_SWI5 EXTI_SWIER_SWIER5

#define	EXTI_SWIER_SWI6 EXTI_SWIER_SWIER6

#define	EXTI_SWIER_SWI7 EXTI_SWIER_SWIER7

#define	EXTI_SWIER_SWI8 EXTI_SWIER_SWIER8

#define	EXTI_SWIER_SWI9 EXTI_SWIER_SWIER9

#define	EXTI_SWIER_SWI10 EXTI_SWIER_SWIER10

#define	EXTI_SWIER_SWI11 EXTI_SWIER_SWIER11

#define	EXTI_SWIER_SWI12 EXTI_SWIER_SWIER12

#define	EXTI_SWIER_SWI13 EXTI_SWIER_SWIER13

#define	EXTI_SWIER_SWI14 EXTI_SWIER_SWIER14

#define	EXTI_SWIER_SWI15 EXTI_SWIER_SWIER15

#define	EXTI_SWIER_SWI16 EXTI_SWIER_SWIER16

#define	EXTI_SWIER_SWI17 EXTI_SWIER_SWIER17

#define	EXTI_SWIER_SWI18 EXTI_SWIER_SWIER18

#define	EXTI_SWIER_SWI19 EXTI_SWIER_SWIER19

#define	EXTI_PR_PR0_Pos (0U)

#define	EXTI_PR_PR0_Msk (0x1UL << EXTI_PR_PR0_Pos)

#define	EXTI_PR_PR0 EXTI_PR_PR0_Msk

#define	EXTI_PR_PR1_Pos (1U)

#define	EXTI_PR_PR1_Msk (0x1UL << EXTI_PR_PR1_Pos)

#define	EXTI_PR_PR1 EXTI_PR_PR1_Msk

#define	EXTI_PR_PR2_Pos (2U)

#define	EXTI_PR_PR2_Msk (0x1UL << EXTI_PR_PR2_Pos)

#define	EXTI_PR_PR2 EXTI_PR_PR2_Msk

#define	EXTI_PR_PR3_Pos (3U)

#define	EXTI_PR_PR3_Msk (0x1UL << EXTI_PR_PR3_Pos)

#define	EXTI_PR_PR3 EXTI_PR_PR3_Msk

#define	EXTI_PR_PR4_Pos (4U)

#define	EXTI_PR_PR4_Msk (0x1UL << EXTI_PR_PR4_Pos)

#define	EXTI_PR_PR4 EXTI_PR_PR4_Msk

#define	EXTI_PR_PR5_Pos (5U)

#define	EXTI_PR_PR5_Msk (0x1UL << EXTI_PR_PR5_Pos)

#define	EXTI_PR_PR5 EXTI_PR_PR5_Msk

#define	EXTI_PR_PR6_Pos (6U)

#define	EXTI_PR_PR6_Msk (0x1UL << EXTI_PR_PR6_Pos)

#define	EXTI_PR_PR6 EXTI_PR_PR6_Msk

#define	EXTI_PR_PR7_Pos (7U)

#define	EXTI_PR_PR7_Msk (0x1UL << EXTI_PR_PR7_Pos)

#define	EXTI_PR_PR7 EXTI_PR_PR7_Msk

#define	EXTI_PR_PR8_Pos (8U)

#define	EXTI_PR_PR8_Msk (0x1UL << EXTI_PR_PR8_Pos)

#define	EXTI_PR_PR8 EXTI_PR_PR8_Msk

#define	EXTI_PR_PR9_Pos (9U)

#define	EXTI_PR_PR9_Msk (0x1UL << EXTI_PR_PR9_Pos)

#define	EXTI_PR_PR9 EXTI_PR_PR9_Msk

#define	EXTI_PR_PR10_Pos (10U)

#define	EXTI_PR_PR10_Msk (0x1UL << EXTI_PR_PR10_Pos)

#define	EXTI_PR_PR10 EXTI_PR_PR10_Msk

#define	EXTI_PR_PR11_Pos (11U)

#define	EXTI_PR_PR11_Msk (0x1UL << EXTI_PR_PR11_Pos)

#define	EXTI_PR_PR11 EXTI_PR_PR11_Msk

#define	EXTI_PR_PR12_Pos (12U)

#define	EXTI_PR_PR12_Msk (0x1UL << EXTI_PR_PR12_Pos)

#define	EXTI_PR_PR12 EXTI_PR_PR12_Msk

#define	EXTI_PR_PR13_Pos (13U)

#define	EXTI_PR_PR13_Msk (0x1UL << EXTI_PR_PR13_Pos)

#define	EXTI_PR_PR13 EXTI_PR_PR13_Msk

#define	EXTI_PR_PR14_Pos (14U)

#define	EXTI_PR_PR14_Msk (0x1UL << EXTI_PR_PR14_Pos)

#define	EXTI_PR_PR14 EXTI_PR_PR14_Msk

#define	EXTI_PR_PR15_Pos (15U)

#define	EXTI_PR_PR15_Msk (0x1UL << EXTI_PR_PR15_Pos)

#define	EXTI_PR_PR15 EXTI_PR_PR15_Msk

#define	EXTI_PR_PR16_Pos (16U)

#define	EXTI_PR_PR16_Msk (0x1UL << EXTI_PR_PR16_Pos)

#define	EXTI_PR_PR16 EXTI_PR_PR16_Msk

#define	EXTI_PR_PR17_Pos (17U)

#define	EXTI_PR_PR17_Msk (0x1UL << EXTI_PR_PR17_Pos)

#define	EXTI_PR_PR17 EXTI_PR_PR17_Msk

#define	EXTI_PR_PR18_Pos (18U)

#define	EXTI_PR_PR18_Msk (0x1UL << EXTI_PR_PR18_Pos)

#define	EXTI_PR_PR18 EXTI_PR_PR18_Msk

#define	EXTI_PR_PR19_Pos (19U)

#define	EXTI_PR_PR19_Msk (0x1UL << EXTI_PR_PR19_Pos)

#define	EXTI_PR_PR19 EXTI_PR_PR19_Msk

#define	EXTI_PR_PIF0 EXTI_PR_PR0

#define	EXTI_PR_PIF1 EXTI_PR_PR1

#define	EXTI_PR_PIF2 EXTI_PR_PR2

#define	EXTI_PR_PIF3 EXTI_PR_PR3

#define	EXTI_PR_PIF4 EXTI_PR_PR4

#define	EXTI_PR_PIF5 EXTI_PR_PR5

#define	EXTI_PR_PIF6 EXTI_PR_PR6

#define	EXTI_PR_PIF7 EXTI_PR_PR7

#define	EXTI_PR_PIF8 EXTI_PR_PR8

#define	EXTI_PR_PIF9 EXTI_PR_PR9

#define	EXTI_PR_PIF10 EXTI_PR_PR10

#define	EXTI_PR_PIF11 EXTI_PR_PR11

#define	EXTI_PR_PIF12 EXTI_PR_PR12

#define	EXTI_PR_PIF13 EXTI_PR_PR13

#define	EXTI_PR_PIF14 EXTI_PR_PR14

#define	EXTI_PR_PIF15 EXTI_PR_PR15

#define	EXTI_PR_PIF16 EXTI_PR_PR16

#define	EXTI_PR_PIF17 EXTI_PR_PR17

#define	EXTI_PR_PIF18 EXTI_PR_PR18

#define	EXTI_PR_PIF19 EXTI_PR_PR19

#define	DMA_ISR_GIF1_Pos (0U)

#define	DMA_ISR_GIF1_Msk (0x1UL << DMA_ISR_GIF1_Pos)

#define	DMA_ISR_GIF1 DMA_ISR_GIF1_Msk

#define	DMA_ISR_TCIF1_Pos (1U)

#define	DMA_ISR_TCIF1_Msk (0x1UL << DMA_ISR_TCIF1_Pos)

#define	DMA_ISR_TCIF1 DMA_ISR_TCIF1_Msk

#define	DMA_ISR_HTIF1_Pos (2U)

#define	DMA_ISR_HTIF1_Msk (0x1UL << DMA_ISR_HTIF1_Pos)

#define	DMA_ISR_HTIF1 DMA_ISR_HTIF1_Msk

#define	DMA_ISR_TEIF1_Pos (3U)

#define	DMA_ISR_TEIF1_Msk (0x1UL << DMA_ISR_TEIF1_Pos)

#define	DMA_ISR_TEIF1 DMA_ISR_TEIF1_Msk

#define	DMA_ISR_GIF2_Pos (4U)

#define	DMA_ISR_GIF2_Msk (0x1UL << DMA_ISR_GIF2_Pos)

#define	DMA_ISR_GIF2 DMA_ISR_GIF2_Msk

#define	DMA_ISR_TCIF2_Pos (5U)

#define	DMA_ISR_TCIF2_Msk (0x1UL << DMA_ISR_TCIF2_Pos)

#define	DMA_ISR_TCIF2 DMA_ISR_TCIF2_Msk

#define	DMA_ISR_HTIF2_Pos (6U)

#define	DMA_ISR_HTIF2_Msk (0x1UL << DMA_ISR_HTIF2_Pos)

#define	DMA_ISR_HTIF2 DMA_ISR_HTIF2_Msk

#define	DMA_ISR_TEIF2_Pos (7U)

#define	DMA_ISR_TEIF2_Msk (0x1UL << DMA_ISR_TEIF2_Pos)

#define	DMA_ISR_TEIF2 DMA_ISR_TEIF2_Msk

#define	DMA_ISR_GIF3_Pos (8U)

#define	DMA_ISR_GIF3_Msk (0x1UL << DMA_ISR_GIF3_Pos)

#define	DMA_ISR_GIF3 DMA_ISR_GIF3_Msk

#define	DMA_ISR_TCIF3_Pos (9U)

#define	DMA_ISR_TCIF3_Msk (0x1UL << DMA_ISR_TCIF3_Pos)

#define	DMA_ISR_TCIF3 DMA_ISR_TCIF3_Msk

#define	DMA_ISR_HTIF3_Pos (10U)

#define	DMA_ISR_HTIF3_Msk (0x1UL << DMA_ISR_HTIF3_Pos)

#define	DMA_ISR_HTIF3 DMA_ISR_HTIF3_Msk

#define	DMA_ISR_TEIF3_Pos (11U)

#define	DMA_ISR_TEIF3_Msk (0x1UL << DMA_ISR_TEIF3_Pos)

#define	DMA_ISR_TEIF3 DMA_ISR_TEIF3_Msk

#define	DMA_ISR_GIF4_Pos (12U)

#define	DMA_ISR_GIF4_Msk (0x1UL << DMA_ISR_GIF4_Pos)

#define	DMA_ISR_GIF4 DMA_ISR_GIF4_Msk

#define	DMA_ISR_TCIF4_Pos (13U)

#define	DMA_ISR_TCIF4_Msk (0x1UL << DMA_ISR_TCIF4_Pos)

#define	DMA_ISR_TCIF4 DMA_ISR_TCIF4_Msk

#define	DMA_ISR_HTIF4_Pos (14U)

#define	DMA_ISR_HTIF4_Msk (0x1UL << DMA_ISR_HTIF4_Pos)

#define	DMA_ISR_HTIF4 DMA_ISR_HTIF4_Msk

#define	DMA_ISR_TEIF4_Pos (15U)

#define	DMA_ISR_TEIF4_Msk (0x1UL << DMA_ISR_TEIF4_Pos)

#define	DMA_ISR_TEIF4 DMA_ISR_TEIF4_Msk

#define	DMA_ISR_GIF5_Pos (16U)

#define	DMA_ISR_GIF5_Msk (0x1UL << DMA_ISR_GIF5_Pos)

#define	DMA_ISR_GIF5 DMA_ISR_GIF5_Msk

#define	DMA_ISR_TCIF5_Pos (17U)

#define	DMA_ISR_TCIF5_Msk (0x1UL << DMA_ISR_TCIF5_Pos)

#define	DMA_ISR_TCIF5 DMA_ISR_TCIF5_Msk

#define	DMA_ISR_HTIF5_Pos (18U)

#define	DMA_ISR_HTIF5_Msk (0x1UL << DMA_ISR_HTIF5_Pos)

#define	DMA_ISR_HTIF5 DMA_ISR_HTIF5_Msk

#define	DMA_ISR_TEIF5_Pos (19U)

#define	DMA_ISR_TEIF5_Msk (0x1UL << DMA_ISR_TEIF5_Pos)

#define	DMA_ISR_TEIF5 DMA_ISR_TEIF5_Msk

#define	DMA_ISR_GIF6_Pos (20U)

#define	DMA_ISR_GIF6_Msk (0x1UL << DMA_ISR_GIF6_Pos)

#define	DMA_ISR_GIF6 DMA_ISR_GIF6_Msk

#define	DMA_ISR_TCIF6_Pos (21U)

#define	DMA_ISR_TCIF6_Msk (0x1UL << DMA_ISR_TCIF6_Pos)

#define	DMA_ISR_TCIF6 DMA_ISR_TCIF6_Msk

#define	DMA_ISR_HTIF6_Pos (22U)

#define	DMA_ISR_HTIF6_Msk (0x1UL << DMA_ISR_HTIF6_Pos)

#define	DMA_ISR_HTIF6 DMA_ISR_HTIF6_Msk

#define	DMA_ISR_TEIF6_Pos (23U)

#define	DMA_ISR_TEIF6_Msk (0x1UL << DMA_ISR_TEIF6_Pos)

#define	DMA_ISR_TEIF6 DMA_ISR_TEIF6_Msk

#define	DMA_ISR_GIF7_Pos (24U)

#define	DMA_ISR_GIF7_Msk (0x1UL << DMA_ISR_GIF7_Pos)

#define	DMA_ISR_GIF7 DMA_ISR_GIF7_Msk

#define	DMA_ISR_TCIF7_Pos (25U)

#define	DMA_ISR_TCIF7_Msk (0x1UL << DMA_ISR_TCIF7_Pos)

#define	DMA_ISR_TCIF7 DMA_ISR_TCIF7_Msk

#define	DMA_ISR_HTIF7_Pos (26U)

#define	DMA_ISR_HTIF7_Msk (0x1UL << DMA_ISR_HTIF7_Pos)

#define	DMA_ISR_HTIF7 DMA_ISR_HTIF7_Msk

#define	DMA_ISR_TEIF7_Pos (27U)

#define	DMA_ISR_TEIF7_Msk (0x1UL << DMA_ISR_TEIF7_Pos)

#define	DMA_ISR_TEIF7 DMA_ISR_TEIF7_Msk

#define	DMA_IFCR_CGIF1_Pos (0U)

#define	DMA_IFCR_CGIF1_Msk (0x1UL << DMA_IFCR_CGIF1_Pos)

#define	DMA_IFCR_CGIF1 DMA_IFCR_CGIF1_Msk

#define	DMA_IFCR_CTCIF1_Pos (1U)

#define	DMA_IFCR_CTCIF1_Msk (0x1UL << DMA_IFCR_CTCIF1_Pos)

#define	DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1_Msk

#define	DMA_IFCR_CHTIF1_Pos (2U)

#define	DMA_IFCR_CHTIF1_Msk (0x1UL << DMA_IFCR_CHTIF1_Pos)

#define	DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1_Msk

#define	DMA_IFCR_CTEIF1_Pos (3U)

#define	DMA_IFCR_CTEIF1_Msk (0x1UL << DMA_IFCR_CTEIF1_Pos)

#define	DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1_Msk

#define	DMA_IFCR_CGIF2_Pos (4U)

#define	DMA_IFCR_CGIF2_Msk (0x1UL << DMA_IFCR_CGIF2_Pos)

#define	DMA_IFCR_CGIF2 DMA_IFCR_CGIF2_Msk

#define	DMA_IFCR_CTCIF2_Pos (5U)

#define	DMA_IFCR_CTCIF2_Msk (0x1UL << DMA_IFCR_CTCIF2_Pos)

#define	DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2_Msk

#define	DMA_IFCR_CHTIF2_Pos (6U)

#define	DMA_IFCR_CHTIF2_Msk (0x1UL << DMA_IFCR_CHTIF2_Pos)

#define	DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2_Msk

#define	DMA_IFCR_CTEIF2_Pos (7U)

#define	DMA_IFCR_CTEIF2_Msk (0x1UL << DMA_IFCR_CTEIF2_Pos)

#define	DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2_Msk

#define	DMA_IFCR_CGIF3_Pos (8U)

#define	DMA_IFCR_CGIF3_Msk (0x1UL << DMA_IFCR_CGIF3_Pos)

#define	DMA_IFCR_CGIF3 DMA_IFCR_CGIF3_Msk

#define	DMA_IFCR_CTCIF3_Pos (9U)

#define	DMA_IFCR_CTCIF3_Msk (0x1UL << DMA_IFCR_CTCIF3_Pos)

#define	DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3_Msk

#define	DMA_IFCR_CHTIF3_Pos (10U)

#define	DMA_IFCR_CHTIF3_Msk (0x1UL << DMA_IFCR_CHTIF3_Pos)

#define	DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3_Msk

#define	DMA_IFCR_CTEIF3_Pos (11U)

#define	DMA_IFCR_CTEIF3_Msk (0x1UL << DMA_IFCR_CTEIF3_Pos)

#define	DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3_Msk

#define	DMA_IFCR_CGIF4_Pos (12U)

#define	DMA_IFCR_CGIF4_Msk (0x1UL << DMA_IFCR_CGIF4_Pos)

#define	DMA_IFCR_CGIF4 DMA_IFCR_CGIF4_Msk

#define	DMA_IFCR_CTCIF4_Pos (13U)

#define	DMA_IFCR_CTCIF4_Msk (0x1UL << DMA_IFCR_CTCIF4_Pos)

#define	DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4_Msk

#define	DMA_IFCR_CHTIF4_Pos (14U)

#define	DMA_IFCR_CHTIF4_Msk (0x1UL << DMA_IFCR_CHTIF4_Pos)

#define	DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4_Msk

#define	DMA_IFCR_CTEIF4_Pos (15U)

#define	DMA_IFCR_CTEIF4_Msk (0x1UL << DMA_IFCR_CTEIF4_Pos)

#define	DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4_Msk

#define	DMA_IFCR_CGIF5_Pos (16U)

#define	DMA_IFCR_CGIF5_Msk (0x1UL << DMA_IFCR_CGIF5_Pos)

#define	DMA_IFCR_CGIF5 DMA_IFCR_CGIF5_Msk

#define	DMA_IFCR_CTCIF5_Pos (17U)

#define	DMA_IFCR_CTCIF5_Msk (0x1UL << DMA_IFCR_CTCIF5_Pos)

#define	DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5_Msk

#define	DMA_IFCR_CHTIF5_Pos (18U)

#define	DMA_IFCR_CHTIF5_Msk (0x1UL << DMA_IFCR_CHTIF5_Pos)

#define	DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5_Msk

#define	DMA_IFCR_CTEIF5_Pos (19U)

#define	DMA_IFCR_CTEIF5_Msk (0x1UL << DMA_IFCR_CTEIF5_Pos)

#define	DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5_Msk

#define	DMA_IFCR_CGIF6_Pos (20U)

#define	DMA_IFCR_CGIF6_Msk (0x1UL << DMA_IFCR_CGIF6_Pos)

#define	DMA_IFCR_CGIF6 DMA_IFCR_CGIF6_Msk

#define	DMA_IFCR_CTCIF6_Pos (21U)

#define	DMA_IFCR_CTCIF6_Msk (0x1UL << DMA_IFCR_CTCIF6_Pos)

#define	DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6_Msk

#define	DMA_IFCR_CHTIF6_Pos (22U)

#define	DMA_IFCR_CHTIF6_Msk (0x1UL << DMA_IFCR_CHTIF6_Pos)

#define	DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6_Msk

#define	DMA_IFCR_CTEIF6_Pos (23U)

#define	DMA_IFCR_CTEIF6_Msk (0x1UL << DMA_IFCR_CTEIF6_Pos)

#define	DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6_Msk

#define	DMA_IFCR_CGIF7_Pos (24U)

#define	DMA_IFCR_CGIF7_Msk (0x1UL << DMA_IFCR_CGIF7_Pos)

#define	DMA_IFCR_CGIF7 DMA_IFCR_CGIF7_Msk

#define	DMA_IFCR_CTCIF7_Pos (25U)

#define	DMA_IFCR_CTCIF7_Msk (0x1UL << DMA_IFCR_CTCIF7_Pos)

#define	DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7_Msk

#define	DMA_IFCR_CHTIF7_Pos (26U)

#define	DMA_IFCR_CHTIF7_Msk (0x1UL << DMA_IFCR_CHTIF7_Pos)

#define	DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7_Msk

#define	DMA_IFCR_CTEIF7_Pos (27U)

#define	DMA_IFCR_CTEIF7_Msk (0x1UL << DMA_IFCR_CTEIF7_Pos)

#define	DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7_Msk

#define	DMA_CCR_EN_Pos (0U)

#define	DMA_CCR_EN_Msk (0x1UL << DMA_CCR_EN_Pos)

#define	DMA_CCR_EN DMA_CCR_EN_Msk

#define	DMA_CCR_TCIE_Pos (1U)

#define	DMA_CCR_TCIE_Msk (0x1UL << DMA_CCR_TCIE_Pos)

#define	DMA_CCR_TCIE DMA_CCR_TCIE_Msk

#define	DMA_CCR_HTIE_Pos (2U)

#define	DMA_CCR_HTIE_Msk (0x1UL << DMA_CCR_HTIE_Pos)

#define	DMA_CCR_HTIE DMA_CCR_HTIE_Msk

#define	DMA_CCR_TEIE_Pos (3U)

#define	DMA_CCR_TEIE_Msk (0x1UL << DMA_CCR_TEIE_Pos)

#define	DMA_CCR_TEIE DMA_CCR_TEIE_Msk

#define	DMA_CCR_DIR_Pos (4U)

#define	DMA_CCR_DIR_Msk (0x1UL << DMA_CCR_DIR_Pos)

#define	DMA_CCR_DIR DMA_CCR_DIR_Msk

#define	DMA_CCR_CIRC_Pos (5U)

#define	DMA_CCR_CIRC_Msk (0x1UL << DMA_CCR_CIRC_Pos)

#define	DMA_CCR_CIRC DMA_CCR_CIRC_Msk

#define	DMA_CCR_PINC_Pos (6U)

#define	DMA_CCR_PINC_Msk (0x1UL << DMA_CCR_PINC_Pos)

#define	DMA_CCR_PINC DMA_CCR_PINC_Msk

#define	DMA_CCR_MINC_Pos (7U)

#define	DMA_CCR_MINC_Msk (0x1UL << DMA_CCR_MINC_Pos)

#define	DMA_CCR_MINC DMA_CCR_MINC_Msk

#define	DMA_CCR_PSIZE_Pos (8U)

#define	DMA_CCR_PSIZE_Msk (0x3UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE DMA_CCR_PSIZE_Msk

#define	DMA_CCR_PSIZE_0 (0x1UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_PSIZE_1 (0x2UL << DMA_CCR_PSIZE_Pos)

#define	DMA_CCR_MSIZE_Pos (10U)

#define	DMA_CCR_MSIZE_Msk (0x3UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE DMA_CCR_MSIZE_Msk

#define	DMA_CCR_MSIZE_0 (0x1UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_MSIZE_1 (0x2UL << DMA_CCR_MSIZE_Pos)

#define	DMA_CCR_PL_Pos (12U)

#define	DMA_CCR_PL_Msk (0x3UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL DMA_CCR_PL_Msk

#define	DMA_CCR_PL_0 (0x1UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_PL_1 (0x2UL << DMA_CCR_PL_Pos)

#define	DMA_CCR_MEM2MEM_Pos (14U)

#define	DMA_CCR_MEM2MEM_Msk (0x1UL << DMA_CCR_MEM2MEM_Pos)

#define	DMA_CCR_MEM2MEM DMA_CCR_MEM2MEM_Msk

#define	DMA_CNDTR_NDT_Pos (0U)

#define	DMA_CNDTR_NDT_Msk (0xFFFFUL << DMA_CNDTR_NDT_Pos)

#define	DMA_CNDTR_NDT DMA_CNDTR_NDT_Msk

#define	DMA_CPAR_PA_Pos (0U)

#define	DMA_CPAR_PA_Msk (0xFFFFFFFFUL << DMA_CPAR_PA_Pos)

#define	DMA_CPAR_PA DMA_CPAR_PA_Msk

#define	DMA_CMAR_MA_Pos (0U)

#define	DMA_CMAR_MA_Msk (0xFFFFFFFFUL << DMA_CMAR_MA_Pos)

#define	DMA_CMAR_MA DMA_CMAR_MA_Msk

#define	ADC_MULTIMODE_SUPPORT

#define	ADC_SR_AWD_Pos (0U)

#define	ADC_SR_AWD_Msk (0x1UL << ADC_SR_AWD_Pos)

#define	ADC_SR_AWD ADC_SR_AWD_Msk

#define	ADC_SR_EOS_Pos (1U)

#define	ADC_SR_EOS_Msk (0x1UL << ADC_SR_EOS_Pos)

#define	ADC_SR_EOS ADC_SR_EOS_Msk

#define	ADC_SR_JEOS_Pos (2U)

#define	ADC_SR_JEOS_Msk (0x1UL << ADC_SR_JEOS_Pos)

#define	ADC_SR_JEOS ADC_SR_JEOS_Msk

#define	ADC_SR_JSTRT_Pos (3U)

#define	ADC_SR_JSTRT_Msk (0x1UL << ADC_SR_JSTRT_Pos)

#define	ADC_SR_JSTRT ADC_SR_JSTRT_Msk

#define	ADC_SR_STRT_Pos (4U)

#define	ADC_SR_STRT_Msk (0x1UL << ADC_SR_STRT_Pos)

#define	ADC_SR_STRT ADC_SR_STRT_Msk

#define	ADC_SR_EOC (ADC_SR_EOS)

#define	ADC_SR_JEOC (ADC_SR_JEOS)

#define	ADC_CR1_AWDCH_Pos (0U)

#define	ADC_CR1_AWDCH_Msk (0x1FUL << ADC_CR1_AWDCH_Pos)

#define	ADC_CR1_AWDCH ADC_CR1_AWDCH_Msk

#define	ADC_CR1_AWDCH_0 (0x01UL << ADC_CR1_AWDCH_Pos)

#define	ADC_CR1_AWDCH_1 (0x02UL << ADC_CR1_AWDCH_Pos)

#define	ADC_CR1_AWDCH_2 (0x04UL << ADC_CR1_AWDCH_Pos)

#define	ADC_CR1_AWDCH_3 (0x08UL << ADC_CR1_AWDCH_Pos)

#define	ADC_CR1_AWDCH_4 (0x10UL << ADC_CR1_AWDCH_Pos)

#define	ADC_CR1_EOSIE_Pos (5U)

#define	ADC_CR1_EOSIE_Msk (0x1UL << ADC_CR1_EOSIE_Pos)

#define	ADC_CR1_EOSIE ADC_CR1_EOSIE_Msk

#define	ADC_CR1_AWDIE_Pos (6U)

#define	ADC_CR1_AWDIE_Msk (0x1UL << ADC_CR1_AWDIE_Pos)

#define	ADC_CR1_AWDIE ADC_CR1_AWDIE_Msk

#define	ADC_CR1_JEOSIE_Pos (7U)

#define	ADC_CR1_JEOSIE_Msk (0x1UL << ADC_CR1_JEOSIE_Pos)

#define	ADC_CR1_JEOSIE ADC_CR1_JEOSIE_Msk

#define	ADC_CR1_SCAN_Pos (8U)

#define	ADC_CR1_SCAN_Msk (0x1UL << ADC_CR1_SCAN_Pos)

#define	ADC_CR1_SCAN ADC_CR1_SCAN_Msk

#define	ADC_CR1_AWDSGL_Pos (9U)

#define	ADC_CR1_AWDSGL_Msk (0x1UL << ADC_CR1_AWDSGL_Pos)

#define	ADC_CR1_AWDSGL ADC_CR1_AWDSGL_Msk

#define	ADC_CR1_JAUTO_Pos (10U)

#define	ADC_CR1_JAUTO_Msk (0x1UL << ADC_CR1_JAUTO_Pos)

#define	ADC_CR1_JAUTO ADC_CR1_JAUTO_Msk

#define	ADC_CR1_DISCEN_Pos (11U)

#define	ADC_CR1_DISCEN_Msk (0x1UL << ADC_CR1_DISCEN_Pos)

#define	ADC_CR1_DISCEN ADC_CR1_DISCEN_Msk

#define	ADC_CR1_JDISCEN_Pos (12U)

#define	ADC_CR1_JDISCEN_Msk (0x1UL << ADC_CR1_JDISCEN_Pos)

#define	ADC_CR1_JDISCEN ADC_CR1_JDISCEN_Msk

#define	ADC_CR1_DISCNUM_Pos (13U)

#define	ADC_CR1_DISCNUM_Msk (0x7UL << ADC_CR1_DISCNUM_Pos)

#define	ADC_CR1_DISCNUM ADC_CR1_DISCNUM_Msk

#define	ADC_CR1_DISCNUM_0 (0x1UL << ADC_CR1_DISCNUM_Pos)

#define	ADC_CR1_DISCNUM_1 (0x2UL << ADC_CR1_DISCNUM_Pos)

#define	ADC_CR1_DISCNUM_2 (0x4UL << ADC_CR1_DISCNUM_Pos)

#define	ADC_CR1_DUALMOD_Pos (16U)

#define	ADC_CR1_DUALMOD_Msk (0xFUL << ADC_CR1_DUALMOD_Pos)

#define	ADC_CR1_DUALMOD ADC_CR1_DUALMOD_Msk

#define	ADC_CR1_DUALMOD_0 (0x1UL << ADC_CR1_DUALMOD_Pos)

#define	ADC_CR1_DUALMOD_1 (0x2UL << ADC_CR1_DUALMOD_Pos)

#define	ADC_CR1_DUALMOD_2 (0x4UL << ADC_CR1_DUALMOD_Pos)

#define	ADC_CR1_DUALMOD_3 (0x8UL << ADC_CR1_DUALMOD_Pos)

#define	ADC_CR1_JAWDEN_Pos (22U)

#define	ADC_CR1_JAWDEN_Msk (0x1UL << ADC_CR1_JAWDEN_Pos)

#define	ADC_CR1_JAWDEN ADC_CR1_JAWDEN_Msk

#define	ADC_CR1_AWDEN_Pos (23U)

#define	ADC_CR1_AWDEN_Msk (0x1UL << ADC_CR1_AWDEN_Pos)

#define	ADC_CR1_AWDEN ADC_CR1_AWDEN_Msk

#define	ADC_CR1_EOCIE (ADC_CR1_EOSIE)

#define	ADC_CR1_JEOCIE (ADC_CR1_JEOSIE)

#define	ADC_CR2_ADON_Pos (0U)

#define	ADC_CR2_ADON_Msk (0x1UL << ADC_CR2_ADON_Pos)

#define	ADC_CR2_ADON ADC_CR2_ADON_Msk

#define	ADC_CR2_CONT_Pos (1U)

#define	ADC_CR2_CONT_Msk (0x1UL << ADC_CR2_CONT_Pos)

#define	ADC_CR2_CONT ADC_CR2_CONT_Msk

#define	ADC_CR2_CAL_Pos (2U)

#define	ADC_CR2_CAL_Msk (0x1UL << ADC_CR2_CAL_Pos)

#define	ADC_CR2_CAL ADC_CR2_CAL_Msk

#define	ADC_CR2_RSTCAL_Pos (3U)

#define	ADC_CR2_RSTCAL_Msk (0x1UL << ADC_CR2_RSTCAL_Pos)

#define	ADC_CR2_RSTCAL ADC_CR2_RSTCAL_Msk

#define	ADC_CR2_DMA_Pos (8U)

#define	ADC_CR2_DMA_Msk (0x1UL << ADC_CR2_DMA_Pos)

#define	ADC_CR2_DMA ADC_CR2_DMA_Msk

#define	ADC_CR2_ALIGN_Pos (11U)

#define	ADC_CR2_ALIGN_Msk (0x1UL << ADC_CR2_ALIGN_Pos)

#define	ADC_CR2_ALIGN ADC_CR2_ALIGN_Msk

#define	ADC_CR2_JEXTSEL_Pos (12U)

#define	ADC_CR2_JEXTSEL_Msk (0x7UL << ADC_CR2_JEXTSEL_Pos)

#define	ADC_CR2_JEXTSEL ADC_CR2_JEXTSEL_Msk

#define	ADC_CR2_JEXTSEL_0 (0x1UL << ADC_CR2_JEXTSEL_Pos)

#define	ADC_CR2_JEXTSEL_1 (0x2UL << ADC_CR2_JEXTSEL_Pos)

#define	ADC_CR2_JEXTSEL_2 (0x4UL << ADC_CR2_JEXTSEL_Pos)

#define	ADC_CR2_JEXTTRIG_Pos (15U)

#define	ADC_CR2_JEXTTRIG_Msk (0x1UL << ADC_CR2_JEXTTRIG_Pos)

#define	ADC_CR2_JEXTTRIG ADC_CR2_JEXTTRIG_Msk

#define	ADC_CR2_EXTSEL_Pos (17U)

#define	ADC_CR2_EXTSEL_Msk (0x7UL << ADC_CR2_EXTSEL_Pos)

#define	ADC_CR2_EXTSEL ADC_CR2_EXTSEL_Msk

#define	ADC_CR2_EXTSEL_0 (0x1UL << ADC_CR2_EXTSEL_Pos)

#define	ADC_CR2_EXTSEL_1 (0x2UL << ADC_CR2_EXTSEL_Pos)

#define	ADC_CR2_EXTSEL_2 (0x4UL << ADC_CR2_EXTSEL_Pos)

#define	ADC_CR2_EXTTRIG_Pos (20U)

#define	ADC_CR2_EXTTRIG_Msk (0x1UL << ADC_CR2_EXTTRIG_Pos)

#define	ADC_CR2_EXTTRIG ADC_CR2_EXTTRIG_Msk

#define	ADC_CR2_JSWSTART_Pos (21U)

#define	ADC_CR2_JSWSTART_Msk (0x1UL << ADC_CR2_JSWSTART_Pos)

#define	ADC_CR2_JSWSTART ADC_CR2_JSWSTART_Msk

#define	ADC_CR2_SWSTART_Pos (22U)

#define	ADC_CR2_SWSTART_Msk (0x1UL << ADC_CR2_SWSTART_Pos)

#define	ADC_CR2_SWSTART ADC_CR2_SWSTART_Msk

#define	ADC_CR2_TSVREFE_Pos (23U)

#define	ADC_CR2_TSVREFE_Msk (0x1UL << ADC_CR2_TSVREFE_Pos)

#define	ADC_CR2_TSVREFE ADC_CR2_TSVREFE_Msk

#define	ADC_SMPR1_SMP10_Pos (0U)

#define	ADC_SMPR1_SMP10_Msk (0x7UL << ADC_SMPR1_SMP10_Pos)

#define	ADC_SMPR1_SMP10 ADC_SMPR1_SMP10_Msk

#define	ADC_SMPR1_SMP10_0 (0x1UL << ADC_SMPR1_SMP10_Pos)

#define	ADC_SMPR1_SMP10_1 (0x2UL << ADC_SMPR1_SMP10_Pos)

#define	ADC_SMPR1_SMP10_2 (0x4UL << ADC_SMPR1_SMP10_Pos)

#define	ADC_SMPR1_SMP11_Pos (3U)

#define	ADC_SMPR1_SMP11_Msk (0x7UL << ADC_SMPR1_SMP11_Pos)

#define	ADC_SMPR1_SMP11 ADC_SMPR1_SMP11_Msk

#define	ADC_SMPR1_SMP11_0 (0x1UL << ADC_SMPR1_SMP11_Pos)

#define	ADC_SMPR1_SMP11_1 (0x2UL << ADC_SMPR1_SMP11_Pos)

#define	ADC_SMPR1_SMP11_2 (0x4UL << ADC_SMPR1_SMP11_Pos)

#define	ADC_SMPR1_SMP12_Pos (6U)

#define	ADC_SMPR1_SMP12_Msk (0x7UL << ADC_SMPR1_SMP12_Pos)

#define	ADC_SMPR1_SMP12 ADC_SMPR1_SMP12_Msk

#define	ADC_SMPR1_SMP12_0 (0x1UL << ADC_SMPR1_SMP12_Pos)

#define	ADC_SMPR1_SMP12_1 (0x2UL << ADC_SMPR1_SMP12_Pos)

#define	ADC_SMPR1_SMP12_2 (0x4UL << ADC_SMPR1_SMP12_Pos)

#define	ADC_SMPR1_SMP13_Pos (9U)

#define	ADC_SMPR1_SMP13_Msk (0x7UL << ADC_SMPR1_SMP13_Pos)

#define	ADC_SMPR1_SMP13 ADC_SMPR1_SMP13_Msk

#define	ADC_SMPR1_SMP13_0 (0x1UL << ADC_SMPR1_SMP13_Pos)

#define	ADC_SMPR1_SMP13_1 (0x2UL << ADC_SMPR1_SMP13_Pos)

#define	ADC_SMPR1_SMP13_2 (0x4UL << ADC_SMPR1_SMP13_Pos)

#define	ADC_SMPR1_SMP14_Pos (12U)

#define	ADC_SMPR1_SMP14_Msk (0x7UL << ADC_SMPR1_SMP14_Pos)

#define	ADC_SMPR1_SMP14 ADC_SMPR1_SMP14_Msk

#define	ADC_SMPR1_SMP14_0 (0x1UL << ADC_SMPR1_SMP14_Pos)

#define	ADC_SMPR1_SMP14_1 (0x2UL << ADC_SMPR1_SMP14_Pos)

#define	ADC_SMPR1_SMP14_2 (0x4UL << ADC_SMPR1_SMP14_Pos)

#define	ADC_SMPR1_SMP15_Pos (15U)

#define	ADC_SMPR1_SMP15_Msk (0x7UL << ADC_SMPR1_SMP15_Pos)

#define	ADC_SMPR1_SMP15 ADC_SMPR1_SMP15_Msk

#define	ADC_SMPR1_SMP15_0 (0x1UL << ADC_SMPR1_SMP15_Pos)

#define	ADC_SMPR1_SMP15_1 (0x2UL << ADC_SMPR1_SMP15_Pos)

#define	ADC_SMPR1_SMP15_2 (0x4UL << ADC_SMPR1_SMP15_Pos)

#define	ADC_SMPR1_SMP16_Pos (18U)

#define	ADC_SMPR1_SMP16_Msk (0x7UL << ADC_SMPR1_SMP16_Pos)

#define	ADC_SMPR1_SMP16 ADC_SMPR1_SMP16_Msk

#define	ADC_SMPR1_SMP16_0 (0x1UL << ADC_SMPR1_SMP16_Pos)

#define	ADC_SMPR1_SMP16_1 (0x2UL << ADC_SMPR1_SMP16_Pos)

#define	ADC_SMPR1_SMP16_2 (0x4UL << ADC_SMPR1_SMP16_Pos)

#define	ADC_SMPR1_SMP17_Pos (21U)

#define	ADC_SMPR1_SMP17_Msk (0x7UL << ADC_SMPR1_SMP17_Pos)

#define	ADC_SMPR1_SMP17 ADC_SMPR1_SMP17_Msk

#define	ADC_SMPR1_SMP17_0 (0x1UL << ADC_SMPR1_SMP17_Pos)

#define	ADC_SMPR1_SMP17_1 (0x2UL << ADC_SMPR1_SMP17_Pos)

#define	ADC_SMPR1_SMP17_2 (0x4UL << ADC_SMPR1_SMP17_Pos)

#define	ADC_SMPR2_SMP0_Pos (0U)

#define	ADC_SMPR2_SMP0_Msk (0x7UL << ADC_SMPR2_SMP0_Pos)

#define	ADC_SMPR2_SMP0 ADC_SMPR2_SMP0_Msk

#define	ADC_SMPR2_SMP0_0 (0x1UL << ADC_SMPR2_SMP0_Pos)

#define	ADC_SMPR2_SMP0_1 (0x2UL << ADC_SMPR2_SMP0_Pos)

#define	ADC_SMPR2_SMP0_2 (0x4UL << ADC_SMPR2_SMP0_Pos)

#define	ADC_SMPR2_SMP1_Pos (3U)

#define	ADC_SMPR2_SMP1_Msk (0x7UL << ADC_SMPR2_SMP1_Pos)

#define	ADC_SMPR2_SMP1 ADC_SMPR2_SMP1_Msk

#define	ADC_SMPR2_SMP1_0 (0x1UL << ADC_SMPR2_SMP1_Pos)

#define	ADC_SMPR2_SMP1_1 (0x2UL << ADC_SMPR2_SMP1_Pos)

#define	ADC_SMPR2_SMP1_2 (0x4UL << ADC_SMPR2_SMP1_Pos)

#define	ADC_SMPR2_SMP2_Pos (6U)

#define	ADC_SMPR2_SMP2_Msk (0x7UL << ADC_SMPR2_SMP2_Pos)

#define	ADC_SMPR2_SMP2 ADC_SMPR2_SMP2_Msk

#define	ADC_SMPR2_SMP2_0 (0x1UL << ADC_SMPR2_SMP2_Pos)

#define	ADC_SMPR2_SMP2_1 (0x2UL << ADC_SMPR2_SMP2_Pos)

#define	ADC_SMPR2_SMP2_2 (0x4UL << ADC_SMPR2_SMP2_Pos)

#define	ADC_SMPR2_SMP3_Pos (9U)

#define	ADC_SMPR2_SMP3_Msk (0x7UL << ADC_SMPR2_SMP3_Pos)

#define	ADC_SMPR2_SMP3 ADC_SMPR2_SMP3_Msk

#define	ADC_SMPR2_SMP3_0 (0x1UL << ADC_SMPR2_SMP3_Pos)

#define	ADC_SMPR2_SMP3_1 (0x2UL << ADC_SMPR2_SMP3_Pos)

#define	ADC_SMPR2_SMP3_2 (0x4UL << ADC_SMPR2_SMP3_Pos)

#define	ADC_SMPR2_SMP4_Pos (12U)

#define	ADC_SMPR2_SMP4_Msk (0x7UL << ADC_SMPR2_SMP4_Pos)

#define	ADC_SMPR2_SMP4 ADC_SMPR2_SMP4_Msk

#define	ADC_SMPR2_SMP4_0 (0x1UL << ADC_SMPR2_SMP4_Pos)

#define	ADC_SMPR2_SMP4_1 (0x2UL << ADC_SMPR2_SMP4_Pos)

#define	ADC_SMPR2_SMP4_2 (0x4UL << ADC_SMPR2_SMP4_Pos)

#define	ADC_SMPR2_SMP5_Pos (15U)

#define	ADC_SMPR2_SMP5_Msk (0x7UL << ADC_SMPR2_SMP5_Pos)

#define	ADC_SMPR2_SMP5 ADC_SMPR2_SMP5_Msk

#define	ADC_SMPR2_SMP5_0 (0x1UL << ADC_SMPR2_SMP5_Pos)

#define	ADC_SMPR2_SMP5_1 (0x2UL << ADC_SMPR2_SMP5_Pos)

#define	ADC_SMPR2_SMP5_2 (0x4UL << ADC_SMPR2_SMP5_Pos)

#define	ADC_SMPR2_SMP6_Pos (18U)

#define	ADC_SMPR2_SMP6_Msk (0x7UL << ADC_SMPR2_SMP6_Pos)

#define	ADC_SMPR2_SMP6 ADC_SMPR2_SMP6_Msk

#define	ADC_SMPR2_SMP6_0 (0x1UL << ADC_SMPR2_SMP6_Pos)

#define	ADC_SMPR2_SMP6_1 (0x2UL << ADC_SMPR2_SMP6_Pos)

#define	ADC_SMPR2_SMP6_2 (0x4UL << ADC_SMPR2_SMP6_Pos)

#define	ADC_SMPR2_SMP7_Pos (21U)

#define	ADC_SMPR2_SMP7_Msk (0x7UL << ADC_SMPR2_SMP7_Pos)

#define	ADC_SMPR2_SMP7 ADC_SMPR2_SMP7_Msk

#define	ADC_SMPR2_SMP7_0 (0x1UL << ADC_SMPR2_SMP7_Pos)

#define	ADC_SMPR2_SMP7_1 (0x2UL << ADC_SMPR2_SMP7_Pos)

#define	ADC_SMPR2_SMP7_2 (0x4UL << ADC_SMPR2_SMP7_Pos)

#define	ADC_SMPR2_SMP8_Pos (24U)

#define	ADC_SMPR2_SMP8_Msk (0x7UL << ADC_SMPR2_SMP8_Pos)

#define	ADC_SMPR2_SMP8 ADC_SMPR2_SMP8_Msk

#define	ADC_SMPR2_SMP8_0 (0x1UL << ADC_SMPR2_SMP8_Pos)

#define	ADC_SMPR2_SMP8_1 (0x2UL << ADC_SMPR2_SMP8_Pos)

#define	ADC_SMPR2_SMP8_2 (0x4UL << ADC_SMPR2_SMP8_Pos)

#define	ADC_SMPR2_SMP9_Pos (27U)

#define	ADC_SMPR2_SMP9_Msk (0x7UL << ADC_SMPR2_SMP9_Pos)

#define	ADC_SMPR2_SMP9 ADC_SMPR2_SMP9_Msk

#define	ADC_SMPR2_SMP9_0 (0x1UL << ADC_SMPR2_SMP9_Pos)

#define	ADC_SMPR2_SMP9_1 (0x2UL << ADC_SMPR2_SMP9_Pos)

#define	ADC_SMPR2_SMP9_2 (0x4UL << ADC_SMPR2_SMP9_Pos)

#define	ADC_JOFR1_JOFFSET1_Pos (0U)

#define	ADC_JOFR1_JOFFSET1_Msk (0xFFFUL << ADC_JOFR1_JOFFSET1_Pos)

#define	ADC_JOFR1_JOFFSET1 ADC_JOFR1_JOFFSET1_Msk

#define	ADC_JOFR2_JOFFSET2_Pos (0U)

#define	ADC_JOFR2_JOFFSET2_Msk (0xFFFUL << ADC_JOFR2_JOFFSET2_Pos)

#define	ADC_JOFR2_JOFFSET2 ADC_JOFR2_JOFFSET2_Msk

#define	ADC_JOFR3_JOFFSET3_Pos (0U)

#define	ADC_JOFR3_JOFFSET3_Msk (0xFFFUL << ADC_JOFR3_JOFFSET3_Pos)

#define	ADC_JOFR3_JOFFSET3 ADC_JOFR3_JOFFSET3_Msk

#define	ADC_JOFR4_JOFFSET4_Pos (0U)

#define	ADC_JOFR4_JOFFSET4_Msk (0xFFFUL << ADC_JOFR4_JOFFSET4_Pos)

#define	ADC_JOFR4_JOFFSET4 ADC_JOFR4_JOFFSET4_Msk

#define	ADC_HTR_HT_Pos (0U)

#define	ADC_HTR_HT_Msk (0xFFFUL << ADC_HTR_HT_Pos)

#define	ADC_HTR_HT ADC_HTR_HT_Msk

#define	ADC_LTR_LT_Pos (0U)

#define	ADC_LTR_LT_Msk (0xFFFUL << ADC_LTR_LT_Pos)

#define	ADC_LTR_LT ADC_LTR_LT_Msk

#define	ADC_SQR1_SQ13_Pos (0U)

#define	ADC_SQR1_SQ13_Msk (0x1FUL << ADC_SQR1_SQ13_Pos)

#define	ADC_SQR1_SQ13 ADC_SQR1_SQ13_Msk

#define	ADC_SQR1_SQ13_0 (0x01UL << ADC_SQR1_SQ13_Pos)

#define	ADC_SQR1_SQ13_1 (0x02UL << ADC_SQR1_SQ13_Pos)

#define	ADC_SQR1_SQ13_2 (0x04UL << ADC_SQR1_SQ13_Pos)

#define	ADC_SQR1_SQ13_3 (0x08UL << ADC_SQR1_SQ13_Pos)

#define	ADC_SQR1_SQ13_4 (0x10UL << ADC_SQR1_SQ13_Pos)

#define	ADC_SQR1_SQ14_Pos (5U)

#define	ADC_SQR1_SQ14_Msk (0x1FUL << ADC_SQR1_SQ14_Pos)

#define	ADC_SQR1_SQ14 ADC_SQR1_SQ14_Msk

#define	ADC_SQR1_SQ14_0 (0x01UL << ADC_SQR1_SQ14_Pos)

#define	ADC_SQR1_SQ14_1 (0x02UL << ADC_SQR1_SQ14_Pos)

#define	ADC_SQR1_SQ14_2 (0x04UL << ADC_SQR1_SQ14_Pos)

#define	ADC_SQR1_SQ14_3 (0x08UL << ADC_SQR1_SQ14_Pos)

#define	ADC_SQR1_SQ14_4 (0x10UL << ADC_SQR1_SQ14_Pos)

#define	ADC_SQR1_SQ15_Pos (10U)

#define	ADC_SQR1_SQ15_Msk (0x1FUL << ADC_SQR1_SQ15_Pos)

#define	ADC_SQR1_SQ15 ADC_SQR1_SQ15_Msk

#define	ADC_SQR1_SQ15_0 (0x01UL << ADC_SQR1_SQ15_Pos)

#define	ADC_SQR1_SQ15_1 (0x02UL << ADC_SQR1_SQ15_Pos)

#define	ADC_SQR1_SQ15_2 (0x04UL << ADC_SQR1_SQ15_Pos)

#define	ADC_SQR1_SQ15_3 (0x08UL << ADC_SQR1_SQ15_Pos)

#define	ADC_SQR1_SQ15_4 (0x10UL << ADC_SQR1_SQ15_Pos)

#define	ADC_SQR1_SQ16_Pos (15U)

#define	ADC_SQR1_SQ16_Msk (0x1FUL << ADC_SQR1_SQ16_Pos)

#define	ADC_SQR1_SQ16 ADC_SQR1_SQ16_Msk

#define	ADC_SQR1_SQ16_0 (0x01UL << ADC_SQR1_SQ16_Pos)

#define	ADC_SQR1_SQ16_1 (0x02UL << ADC_SQR1_SQ16_Pos)

#define	ADC_SQR1_SQ16_2 (0x04UL << ADC_SQR1_SQ16_Pos)

#define	ADC_SQR1_SQ16_3 (0x08UL << ADC_SQR1_SQ16_Pos)

#define	ADC_SQR1_SQ16_4 (0x10UL << ADC_SQR1_SQ16_Pos)

#define	ADC_SQR1_L_Pos (20U)

#define	ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L ADC_SQR1_L_Msk

#define	ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos)

#define	ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos)

#define	ADC_SQR2_SQ7_Pos (0U)

#define	ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk

#define	ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos)

#define	ADC_SQR2_SQ8_Pos (5U)

#define	ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk

#define	ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos)

#define	ADC_SQR2_SQ9_Pos (10U)

#define	ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk

#define	ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos)

#define	ADC_SQR2_SQ10_Pos (15U)

#define	ADC_SQR2_SQ10_Msk (0x1FUL << ADC_SQR2_SQ10_Pos)

#define	ADC_SQR2_SQ10 ADC_SQR2_SQ10_Msk

#define	ADC_SQR2_SQ10_0 (0x01UL << ADC_SQR2_SQ10_Pos)

#define	ADC_SQR2_SQ10_1 (0x02UL << ADC_SQR2_SQ10_Pos)

#define	ADC_SQR2_SQ10_2 (0x04UL << ADC_SQR2_SQ10_Pos)

#define	ADC_SQR2_SQ10_3 (0x08UL << ADC_SQR2_SQ10_Pos)

#define	ADC_SQR2_SQ10_4 (0x10UL << ADC_SQR2_SQ10_Pos)

#define	ADC_SQR2_SQ11_Pos (20U)

#define	ADC_SQR2_SQ11_Msk (0x1FUL << ADC_SQR2_SQ11_Pos)

#define	ADC_SQR2_SQ11 ADC_SQR2_SQ11_Msk

#define	ADC_SQR2_SQ11_0 (0x01UL << ADC_SQR2_SQ11_Pos)

#define	ADC_SQR2_SQ11_1 (0x02UL << ADC_SQR2_SQ11_Pos)

#define	ADC_SQR2_SQ11_2 (0x04UL << ADC_SQR2_SQ11_Pos)

#define	ADC_SQR2_SQ11_3 (0x08UL << ADC_SQR2_SQ11_Pos)

#define	ADC_SQR2_SQ11_4 (0x10UL << ADC_SQR2_SQ11_Pos)

#define	ADC_SQR2_SQ12_Pos (25U)

#define	ADC_SQR2_SQ12_Msk (0x1FUL << ADC_SQR2_SQ12_Pos)

#define	ADC_SQR2_SQ12 ADC_SQR2_SQ12_Msk

#define	ADC_SQR2_SQ12_0 (0x01UL << ADC_SQR2_SQ12_Pos)

#define	ADC_SQR2_SQ12_1 (0x02UL << ADC_SQR2_SQ12_Pos)

#define	ADC_SQR2_SQ12_2 (0x04UL << ADC_SQR2_SQ12_Pos)

#define	ADC_SQR2_SQ12_3 (0x08UL << ADC_SQR2_SQ12_Pos)

#define	ADC_SQR2_SQ12_4 (0x10UL << ADC_SQR2_SQ12_Pos)

#define	ADC_SQR3_SQ1_Pos (0U)

#define	ADC_SQR3_SQ1_Msk (0x1FUL << ADC_SQR3_SQ1_Pos)

#define	ADC_SQR3_SQ1 ADC_SQR3_SQ1_Msk

#define	ADC_SQR3_SQ1_0 (0x01UL << ADC_SQR3_SQ1_Pos)

#define	ADC_SQR3_SQ1_1 (0x02UL << ADC_SQR3_SQ1_Pos)

#define	ADC_SQR3_SQ1_2 (0x04UL << ADC_SQR3_SQ1_Pos)

#define	ADC_SQR3_SQ1_3 (0x08UL << ADC_SQR3_SQ1_Pos)

#define	ADC_SQR3_SQ1_4 (0x10UL << ADC_SQR3_SQ1_Pos)

#define	ADC_SQR3_SQ2_Pos (5U)

#define	ADC_SQR3_SQ2_Msk (0x1FUL << ADC_SQR3_SQ2_Pos)

#define	ADC_SQR3_SQ2 ADC_SQR3_SQ2_Msk

#define	ADC_SQR3_SQ2_0 (0x01UL << ADC_SQR3_SQ2_Pos)

#define	ADC_SQR3_SQ2_1 (0x02UL << ADC_SQR3_SQ2_Pos)

#define	ADC_SQR3_SQ2_2 (0x04UL << ADC_SQR3_SQ2_Pos)

#define	ADC_SQR3_SQ2_3 (0x08UL << ADC_SQR3_SQ2_Pos)

#define	ADC_SQR3_SQ2_4 (0x10UL << ADC_SQR3_SQ2_Pos)

#define	ADC_SQR3_SQ3_Pos (10U)

#define	ADC_SQR3_SQ3_Msk (0x1FUL << ADC_SQR3_SQ3_Pos)

#define	ADC_SQR3_SQ3 ADC_SQR3_SQ3_Msk

#define	ADC_SQR3_SQ3_0 (0x01UL << ADC_SQR3_SQ3_Pos)

#define	ADC_SQR3_SQ3_1 (0x02UL << ADC_SQR3_SQ3_Pos)

#define	ADC_SQR3_SQ3_2 (0x04UL << ADC_SQR3_SQ3_Pos)

#define	ADC_SQR3_SQ3_3 (0x08UL << ADC_SQR3_SQ3_Pos)

#define	ADC_SQR3_SQ3_4 (0x10UL << ADC_SQR3_SQ3_Pos)

#define	ADC_SQR3_SQ4_Pos (15U)

#define	ADC_SQR3_SQ4_Msk (0x1FUL << ADC_SQR3_SQ4_Pos)

#define	ADC_SQR3_SQ4 ADC_SQR3_SQ4_Msk

#define	ADC_SQR3_SQ4_0 (0x01UL << ADC_SQR3_SQ4_Pos)

#define	ADC_SQR3_SQ4_1 (0x02UL << ADC_SQR3_SQ4_Pos)

#define	ADC_SQR3_SQ4_2 (0x04UL << ADC_SQR3_SQ4_Pos)

#define	ADC_SQR3_SQ4_3 (0x08UL << ADC_SQR3_SQ4_Pos)

#define	ADC_SQR3_SQ4_4 (0x10UL << ADC_SQR3_SQ4_Pos)

#define	ADC_SQR3_SQ5_Pos (20U)

#define	ADC_SQR3_SQ5_Msk (0x1FUL << ADC_SQR3_SQ5_Pos)

#define	ADC_SQR3_SQ5 ADC_SQR3_SQ5_Msk

#define	ADC_SQR3_SQ5_0 (0x01UL << ADC_SQR3_SQ5_Pos)

#define	ADC_SQR3_SQ5_1 (0x02UL << ADC_SQR3_SQ5_Pos)

#define	ADC_SQR3_SQ5_2 (0x04UL << ADC_SQR3_SQ5_Pos)

#define	ADC_SQR3_SQ5_3 (0x08UL << ADC_SQR3_SQ5_Pos)

#define	ADC_SQR3_SQ5_4 (0x10UL << ADC_SQR3_SQ5_Pos)

#define	ADC_SQR3_SQ6_Pos (25U)

#define	ADC_SQR3_SQ6_Msk (0x1FUL << ADC_SQR3_SQ6_Pos)

#define	ADC_SQR3_SQ6 ADC_SQR3_SQ6_Msk

#define	ADC_SQR3_SQ6_0 (0x01UL << ADC_SQR3_SQ6_Pos)

#define	ADC_SQR3_SQ6_1 (0x02UL << ADC_SQR3_SQ6_Pos)

#define	ADC_SQR3_SQ6_2 (0x04UL << ADC_SQR3_SQ6_Pos)

#define	ADC_SQR3_SQ6_3 (0x08UL << ADC_SQR3_SQ6_Pos)

#define	ADC_SQR3_SQ6_4 (0x10UL << ADC_SQR3_SQ6_Pos)

#define	ADC_JSQR_JSQ1_Pos (0U)

#define	ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk

#define	ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos)

#define	ADC_JSQR_JSQ2_Pos (5U)

#define	ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk

#define	ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos)

#define	ADC_JSQR_JSQ3_Pos (10U)

#define	ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk

#define	ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos)

#define	ADC_JSQR_JSQ4_Pos (15U)

#define	ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk

#define	ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos)

#define	ADC_JSQR_JL_Pos (20U)

#define	ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL ADC_JSQR_JL_Msk

#define	ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos)

#define	ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos)

#define	ADC_JDR1_JDATA_Pos (0U)

#define	ADC_JDR1_JDATA_Msk (0xFFFFUL << ADC_JDR1_JDATA_Pos)

#define	ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk

#define	ADC_JDR2_JDATA_Pos (0U)

#define	ADC_JDR2_JDATA_Msk (0xFFFFUL << ADC_JDR2_JDATA_Pos)

#define	ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk

#define	ADC_JDR3_JDATA_Pos (0U)

#define	ADC_JDR3_JDATA_Msk (0xFFFFUL << ADC_JDR3_JDATA_Pos)

#define	ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk

#define	ADC_JDR4_JDATA_Pos (0U)

#define	ADC_JDR4_JDATA_Msk (0xFFFFUL << ADC_JDR4_JDATA_Pos)

#define	ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk

#define	ADC_DR_DATA_Pos (0U)

#define	ADC_DR_DATA_Msk (0xFFFFUL << ADC_DR_DATA_Pos)

#define	ADC_DR_DATA ADC_DR_DATA_Msk

#define	ADC_DR_ADC2DATA_Pos (16U)

#define	ADC_DR_ADC2DATA_Msk (0xFFFFUL << ADC_DR_ADC2DATA_Pos)

#define	ADC_DR_ADC2DATA ADC_DR_ADC2DATA_Msk

#define	DAC_CR_EN1_Pos (0U)

#define	DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos)

#define	DAC_CR_EN1 DAC_CR_EN1_Msk

#define	DAC_CR_BOFF1_Pos (1U)

#define	DAC_CR_BOFF1_Msk (0x1UL << DAC_CR_BOFF1_Pos)

#define	DAC_CR_BOFF1 DAC_CR_BOFF1_Msk

#define	DAC_CR_TEN1_Pos (2U)

#define	DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos)

#define	DAC_CR_TEN1 DAC_CR_TEN1_Msk

#define	DAC_CR_TSEL1_Pos (3U)

#define	DAC_CR_TSEL1_Msk (0x7UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1 DAC_CR_TSEL1_Msk

#define	DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos)

#define	DAC_CR_WAVE1_Pos (6U)

#define	DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1 DAC_CR_WAVE1_Msk

#define	DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos)

#define	DAC_CR_MAMP1_Pos (8U)

#define	DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1 DAC_CR_MAMP1_Msk

#define	DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos)

#define	DAC_CR_DMAEN1_Pos (12U)

#define	DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos)

#define	DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk

#define	DAC_CR_EN2_Pos (16U)

#define	DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos)

#define	DAC_CR_EN2 DAC_CR_EN2_Msk

#define	DAC_CR_BOFF2_Pos (17U)

#define	DAC_CR_BOFF2_Msk (0x1UL << DAC_CR_BOFF2_Pos)

#define	DAC_CR_BOFF2 DAC_CR_BOFF2_Msk

#define	DAC_CR_TEN2_Pos (18U)

#define	DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos)

#define	DAC_CR_TEN2 DAC_CR_TEN2_Msk

#define	DAC_CR_TSEL2_Pos (19U)

#define	DAC_CR_TSEL2_Msk (0x7UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2 DAC_CR_TSEL2_Msk

#define	DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos)

#define	DAC_CR_WAVE2_Pos (22U)

#define	DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2 DAC_CR_WAVE2_Msk

#define	DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos)

#define	DAC_CR_MAMP2_Pos (24U)

#define	DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2 DAC_CR_MAMP2_Msk

#define	DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos)

#define	DAC_CR_DMAEN2_Pos (28U)

#define	DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos)

#define	DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk

#define	DAC_SWTRIGR_SWTRIG1_Pos (0U)

#define	DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos)

#define	DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk

#define	DAC_SWTRIGR_SWTRIG2_Pos (1U)

#define	DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos)

#define	DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk

#define	DAC_DHR12R1_DACC1DHR_Pos (0U)

#define	DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos)

#define	DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk

#define	DAC_DHR12L1_DACC1DHR_Pos (4U)

#define	DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos)

#define	DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk

#define	DAC_DHR8R1_DACC1DHR_Pos (0U)

#define	DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos)

#define	DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk

#define	DAC_DHR12R2_DACC2DHR_Pos (0U)

#define	DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos)

#define	DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk

#define	DAC_DHR12L2_DACC2DHR_Pos (4U)

#define	DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos)

#define	DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk

#define	DAC_DHR8R2_DACC2DHR_Pos (0U)

#define	DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos)

#define	DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk

#define	DAC_DHR12RD_DACC1DHR_Pos (0U)

#define	DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos)

#define	DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk

#define	DAC_DHR12RD_DACC2DHR_Pos (16U)

#define	DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos)

#define	DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk

#define	DAC_DHR12LD_DACC1DHR_Pos (4U)

#define	DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos)

#define	DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk

#define	DAC_DHR12LD_DACC2DHR_Pos (20U)

#define	DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos)

#define	DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk

#define	DAC_DHR8RD_DACC1DHR_Pos (0U)

#define	DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos)

#define	DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk

#define	DAC_DHR8RD_DACC2DHR_Pos (8U)

#define	DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos)

#define	DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk

#define	DAC_DOR1_DACC1DOR_Pos (0U)

#define	DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos)

#define	DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk

#define	DAC_DOR2_DACC2DOR_Pos (0U)

#define	DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos)

#define	DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk

#define	TIM_CR1_CEN_Pos (0U)

#define	TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos)

#define	TIM_CR1_CEN TIM_CR1_CEN_Msk

#define	TIM_CR1_UDIS_Pos (1U)

#define	TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos)

#define	TIM_CR1_UDIS TIM_CR1_UDIS_Msk

#define	TIM_CR1_URS_Pos (2U)

#define	TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos)

#define	TIM_CR1_URS TIM_CR1_URS_Msk

#define	TIM_CR1_OPM_Pos (3U)

#define	TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos)

#define	TIM_CR1_OPM TIM_CR1_OPM_Msk

#define	TIM_CR1_DIR_Pos (4U)

#define	TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos)

#define	TIM_CR1_DIR TIM_CR1_DIR_Msk

#define	TIM_CR1_CMS_Pos (5U)

#define	TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS TIM_CR1_CMS_Msk

#define	TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos)

#define	TIM_CR1_ARPE_Pos (7U)

#define	TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos)

#define	TIM_CR1_ARPE TIM_CR1_ARPE_Msk

#define	TIM_CR1_CKD_Pos (8U)

#define	TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD TIM_CR1_CKD_Msk

#define	TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos)

#define	TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos)

#define	TIM_CR2_CCPC_Pos (0U)

#define	TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos)

#define	TIM_CR2_CCPC TIM_CR2_CCPC_Msk

#define	TIM_CR2_CCUS_Pos (2U)

#define	TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos)

#define	TIM_CR2_CCUS TIM_CR2_CCUS_Msk

#define	TIM_CR2_CCDS_Pos (3U)

#define	TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos)

#define	TIM_CR2_CCDS TIM_CR2_CCDS_Msk

#define	TIM_CR2_MMS_Pos (4U)

#define	TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS TIM_CR2_MMS_Msk

#define	TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos)

#define	TIM_CR2_TI1S_Pos (7U)

#define	TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos)

#define	TIM_CR2_TI1S TIM_CR2_TI1S_Msk

#define	TIM_CR2_OIS1_Pos (8U)

#define	TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos)

#define	TIM_CR2_OIS1 TIM_CR2_OIS1_Msk

#define	TIM_CR2_OIS1N_Pos (9U)

#define	TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos)

#define	TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk

#define	TIM_CR2_OIS2_Pos (10U)

#define	TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos)

#define	TIM_CR2_OIS2 TIM_CR2_OIS2_Msk

#define	TIM_CR2_OIS2N_Pos (11U)

#define	TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos)

#define	TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk

#define	TIM_CR2_OIS3_Pos (12U)

#define	TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos)

#define	TIM_CR2_OIS3 TIM_CR2_OIS3_Msk

#define	TIM_CR2_OIS3N_Pos (13U)

#define	TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos)

#define	TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk

#define	TIM_CR2_OIS4_Pos (14U)

#define	TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos)

#define	TIM_CR2_OIS4 TIM_CR2_OIS4_Msk

#define	TIM_SMCR_SMS_Pos (0U)

#define	TIM_SMCR_SMS_Msk (0x7UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS TIM_SMCR_SMS_Msk

#define	TIM_SMCR_SMS_0 (0x1UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_1 (0x2UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_SMS_2 (0x4UL << TIM_SMCR_SMS_Pos)

#define	TIM_SMCR_TS_Pos (4U)

#define	TIM_SMCR_TS_Msk (0x7UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS TIM_SMCR_TS_Msk

#define	TIM_SMCR_TS_0 (0x1UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_1 (0x2UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_TS_2 (0x4UL << TIM_SMCR_TS_Pos)

#define	TIM_SMCR_MSM_Pos (7U)

#define	TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos)

#define	TIM_SMCR_MSM TIM_SMCR_MSM_Msk

#define	TIM_SMCR_ETF_Pos (8U)

#define	TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF TIM_SMCR_ETF_Msk

#define	TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos)

#define	TIM_SMCR_ETPS_Pos (12U)

#define	TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk

#define	TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos)

#define	TIM_SMCR_ECE_Pos (14U)

#define	TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos)

#define	TIM_SMCR_ECE TIM_SMCR_ECE_Msk

#define	TIM_SMCR_ETP_Pos (15U)

#define	TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos)

#define	TIM_SMCR_ETP TIM_SMCR_ETP_Msk

#define	TIM_DIER_UIE_Pos (0U)

#define	TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos)

#define	TIM_DIER_UIE TIM_DIER_UIE_Msk

#define	TIM_DIER_CC1IE_Pos (1U)

#define	TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos)

#define	TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk

#define	TIM_DIER_CC2IE_Pos (2U)

#define	TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos)

#define	TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk

#define	TIM_DIER_CC3IE_Pos (3U)

#define	TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos)

#define	TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk

#define	TIM_DIER_CC4IE_Pos (4U)

#define	TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos)

#define	TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk

#define	TIM_DIER_COMIE_Pos (5U)

#define	TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos)

#define	TIM_DIER_COMIE TIM_DIER_COMIE_Msk

#define	TIM_DIER_TIE_Pos (6U)

#define	TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos)

#define	TIM_DIER_TIE TIM_DIER_TIE_Msk

#define	TIM_DIER_BIE_Pos (7U)

#define	TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos)

#define	TIM_DIER_BIE TIM_DIER_BIE_Msk

#define	TIM_DIER_UDE_Pos (8U)

#define	TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos)

#define	TIM_DIER_UDE TIM_DIER_UDE_Msk

#define	TIM_DIER_CC1DE_Pos (9U)

#define	TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos)

#define	TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk

#define	TIM_DIER_CC2DE_Pos (10U)

#define	TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos)

#define	TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk

#define	TIM_DIER_CC3DE_Pos (11U)

#define	TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos)

#define	TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk

#define	TIM_DIER_CC4DE_Pos (12U)

#define	TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos)

#define	TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk

#define	TIM_DIER_COMDE_Pos (13U)

#define	TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos)

#define	TIM_DIER_COMDE TIM_DIER_COMDE_Msk

#define	TIM_DIER_TDE_Pos (14U)

#define	TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos)

#define	TIM_DIER_TDE TIM_DIER_TDE_Msk

#define	TIM_SR_UIF_Pos (0U)

#define	TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos)

#define	TIM_SR_UIF TIM_SR_UIF_Msk

#define	TIM_SR_CC1IF_Pos (1U)

#define	TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos)

#define	TIM_SR_CC1IF TIM_SR_CC1IF_Msk

#define	TIM_SR_CC2IF_Pos (2U)

#define	TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos)

#define	TIM_SR_CC2IF TIM_SR_CC2IF_Msk

#define	TIM_SR_CC3IF_Pos (3U)

#define	TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos)

#define	TIM_SR_CC3IF TIM_SR_CC3IF_Msk

#define	TIM_SR_CC4IF_Pos (4U)

#define	TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos)

#define	TIM_SR_CC4IF TIM_SR_CC4IF_Msk

#define	TIM_SR_COMIF_Pos (5U)

#define	TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos)

#define	TIM_SR_COMIF TIM_SR_COMIF_Msk

#define	TIM_SR_TIF_Pos (6U)

#define	TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos)

#define	TIM_SR_TIF TIM_SR_TIF_Msk

#define	TIM_SR_BIF_Pos (7U)

#define	TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos)

#define	TIM_SR_BIF TIM_SR_BIF_Msk

#define	TIM_SR_CC1OF_Pos (9U)

#define	TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos)

#define	TIM_SR_CC1OF TIM_SR_CC1OF_Msk

#define	TIM_SR_CC2OF_Pos (10U)

#define	TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos)

#define	TIM_SR_CC2OF TIM_SR_CC2OF_Msk

#define	TIM_SR_CC3OF_Pos (11U)

#define	TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos)

#define	TIM_SR_CC3OF TIM_SR_CC3OF_Msk

#define	TIM_SR_CC4OF_Pos (12U)

#define	TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos)

#define	TIM_SR_CC4OF TIM_SR_CC4OF_Msk

#define	TIM_EGR_UG_Pos (0U)

#define	TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos)

#define	TIM_EGR_UG TIM_EGR_UG_Msk

#define	TIM_EGR_CC1G_Pos (1U)

#define	TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos)

#define	TIM_EGR_CC1G TIM_EGR_CC1G_Msk

#define	TIM_EGR_CC2G_Pos (2U)

#define	TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos)

#define	TIM_EGR_CC2G TIM_EGR_CC2G_Msk

#define	TIM_EGR_CC3G_Pos (3U)

#define	TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos)

#define	TIM_EGR_CC3G TIM_EGR_CC3G_Msk

#define	TIM_EGR_CC4G_Pos (4U)

#define	TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos)

#define	TIM_EGR_CC4G TIM_EGR_CC4G_Msk

#define	TIM_EGR_COMG_Pos (5U)

#define	TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos)

#define	TIM_EGR_COMG TIM_EGR_COMG_Msk

#define	TIM_EGR_TG_Pos (6U)

#define	TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos)

#define	TIM_EGR_TG TIM_EGR_TG_Msk

#define	TIM_EGR_BG_Pos (7U)

#define	TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos)

#define	TIM_EGR_BG TIM_EGR_BG_Msk

#define	TIM_CCMR1_CC1S_Pos (0U)

#define	TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk

#define	TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos)

#define	TIM_CCMR1_OC1FE_Pos (2U)

#define	TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos)

#define	TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk

#define	TIM_CCMR1_OC1PE_Pos (3U)

#define	TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos)

#define	TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk

#define	TIM_CCMR1_OC1M_Pos (4U)

#define	TIM_CCMR1_OC1M_Msk (0x7UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk

#define	TIM_CCMR1_OC1M_0 (0x1UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_1 (0x2UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1M_2 (0x4UL << TIM_CCMR1_OC1M_Pos)

#define	TIM_CCMR1_OC1CE_Pos (7U)

#define	TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos)

#define	TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk

#define	TIM_CCMR1_CC2S_Pos (8U)

#define	TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk

#define	TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos)

#define	TIM_CCMR1_OC2FE_Pos (10U)

#define	TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos)

#define	TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk

#define	TIM_CCMR1_OC2PE_Pos (11U)

#define	TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos)

#define	TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk

#define	TIM_CCMR1_OC2M_Pos (12U)

#define	TIM_CCMR1_OC2M_Msk (0x7UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk

#define	TIM_CCMR1_OC2M_0 (0x1UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_1 (0x2UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2M_2 (0x4UL << TIM_CCMR1_OC2M_Pos)

#define	TIM_CCMR1_OC2CE_Pos (15U)

#define	TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos)

#define	TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk

#define	TIM_CCMR1_IC1PSC_Pos (2U)

#define	TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk

#define	TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos)

#define	TIM_CCMR1_IC1F_Pos (4U)

#define	TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk

#define	TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos)

#define	TIM_CCMR1_IC2PSC_Pos (10U)

#define	TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk

#define	TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos)

#define	TIM_CCMR1_IC2F_Pos (12U)

#define	TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk

#define	TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos)

#define	TIM_CCMR2_CC3S_Pos (0U)

#define	TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk

#define	TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos)

#define	TIM_CCMR2_OC3FE_Pos (2U)

#define	TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos)

#define	TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk

#define	TIM_CCMR2_OC3PE_Pos (3U)

#define	TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos)

#define	TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk

#define	TIM_CCMR2_OC3M_Pos (4U)

#define	TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk

#define	TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos)

#define	TIM_CCMR2_OC3CE_Pos (7U)

#define	TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos)

#define	TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk

#define	TIM_CCMR2_CC4S_Pos (8U)

#define	TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk

#define	TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos)

#define	TIM_CCMR2_OC4FE_Pos (10U)

#define	TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos)

#define	TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk

#define	TIM_CCMR2_OC4PE_Pos (11U)

#define	TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos)

#define	TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk

#define	TIM_CCMR2_OC4M_Pos (12U)

#define	TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk

#define	TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos)

#define	TIM_CCMR2_OC4CE_Pos (15U)

#define	TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos)

#define	TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk

#define	TIM_CCMR2_IC3PSC_Pos (2U)

#define	TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk

#define	TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos)

#define	TIM_CCMR2_IC3F_Pos (4U)

#define	TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk

#define	TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos)

#define	TIM_CCMR2_IC4PSC_Pos (10U)

#define	TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk

#define	TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos)

#define	TIM_CCMR2_IC4F_Pos (12U)

#define	TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk

#define	TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos)

#define	TIM_CCER_CC1E_Pos (0U)

#define	TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos)

#define	TIM_CCER_CC1E TIM_CCER_CC1E_Msk

#define	TIM_CCER_CC1P_Pos (1U)

#define	TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos)

#define	TIM_CCER_CC1P TIM_CCER_CC1P_Msk

#define	TIM_CCER_CC1NE_Pos (2U)

#define	TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos)

#define	TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk

#define	TIM_CCER_CC1NP_Pos (3U)

#define	TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos)

#define	TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk

#define	TIM_CCER_CC2E_Pos (4U)

#define	TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos)

#define	TIM_CCER_CC2E TIM_CCER_CC2E_Msk

#define	TIM_CCER_CC2P_Pos (5U)

#define	TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos)

#define	TIM_CCER_CC2P TIM_CCER_CC2P_Msk

#define	TIM_CCER_CC2NE_Pos (6U)

#define	TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos)

#define	TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk

#define	TIM_CCER_CC2NP_Pos (7U)

#define	TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos)

#define	TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk

#define	TIM_CCER_CC3E_Pos (8U)

#define	TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos)

#define	TIM_CCER_CC3E TIM_CCER_CC3E_Msk

#define	TIM_CCER_CC3P_Pos (9U)

#define	TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos)

#define	TIM_CCER_CC3P TIM_CCER_CC3P_Msk

#define	TIM_CCER_CC3NE_Pos (10U)

#define	TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos)

#define	TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk

#define	TIM_CCER_CC3NP_Pos (11U)

#define	TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos)

#define	TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk

#define	TIM_CCER_CC4E_Pos (12U)

#define	TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos)

#define	TIM_CCER_CC4E TIM_CCER_CC4E_Msk

#define	TIM_CCER_CC4P_Pos (13U)

#define	TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos)

#define	TIM_CCER_CC4P TIM_CCER_CC4P_Msk

#define	TIM_CNT_CNT_Pos (0U)

#define	TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos)

#define	TIM_CNT_CNT TIM_CNT_CNT_Msk

#define	TIM_PSC_PSC_Pos (0U)

#define	TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos)

#define	TIM_PSC_PSC TIM_PSC_PSC_Msk

#define	TIM_ARR_ARR_Pos (0U)

#define	TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos)

#define	TIM_ARR_ARR TIM_ARR_ARR_Msk

#define	TIM_RCR_REP_Pos (0U)

#define	TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos)

#define	TIM_RCR_REP TIM_RCR_REP_Msk

#define	TIM_CCR1_CCR1_Pos (0U)

#define	TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos)

#define	TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk

#define	TIM_CCR2_CCR2_Pos (0U)

#define	TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos)

#define	TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk

#define	TIM_CCR3_CCR3_Pos (0U)

#define	TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos)

#define	TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk

#define	TIM_CCR4_CCR4_Pos (0U)

#define	TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos)

#define	TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk

#define	TIM_BDTR_DTG_Pos (0U)

#define	TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG TIM_BDTR_DTG_Msk

#define	TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos)

#define	TIM_BDTR_LOCK_Pos (8U)

#define	TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk

#define	TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos)

#define	TIM_BDTR_OSSI_Pos (10U)

#define	TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos)

#define	TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk

#define	TIM_BDTR_OSSR_Pos (11U)

#define	TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos)

#define	TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk

#define	TIM_BDTR_BKE_Pos (12U)

#define	TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos)

#define	TIM_BDTR_BKE TIM_BDTR_BKE_Msk

#define	TIM_BDTR_BKP_Pos (13U)

#define	TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos)

#define	TIM_BDTR_BKP TIM_BDTR_BKP_Msk

#define	TIM_BDTR_AOE_Pos (14U)

#define	TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos)

#define	TIM_BDTR_AOE TIM_BDTR_AOE_Msk

#define	TIM_BDTR_MOE_Pos (15U)

#define	TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos)

#define	TIM_BDTR_MOE TIM_BDTR_MOE_Msk

#define	TIM_DCR_DBA_Pos (0U)

#define	TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA TIM_DCR_DBA_Msk

#define	TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos)

#define	TIM_DCR_DBL_Pos (8U)

#define	TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL TIM_DCR_DBL_Msk

#define	TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos)

#define	TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos)

#define	TIM_DMAR_DMAB_Pos (0U)

#define	TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos)

#define	TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk

#define	RTC_CRH_SECIE_Pos (0U)

#define	RTC_CRH_SECIE_Msk (0x1UL << RTC_CRH_SECIE_Pos)

#define	RTC_CRH_SECIE RTC_CRH_SECIE_Msk

#define	RTC_CRH_ALRIE_Pos (1U)

#define	RTC_CRH_ALRIE_Msk (0x1UL << RTC_CRH_ALRIE_Pos)

#define	RTC_CRH_ALRIE RTC_CRH_ALRIE_Msk

#define	RTC_CRH_OWIE_Pos (2U)

#define	RTC_CRH_OWIE_Msk (0x1UL << RTC_CRH_OWIE_Pos)

#define	RTC_CRH_OWIE RTC_CRH_OWIE_Msk

#define	RTC_CRL_SECF_Pos (0U)

#define	RTC_CRL_SECF_Msk (0x1UL << RTC_CRL_SECF_Pos)

#define	RTC_CRL_SECF RTC_CRL_SECF_Msk

#define	RTC_CRL_ALRF_Pos (1U)

#define	RTC_CRL_ALRF_Msk (0x1UL << RTC_CRL_ALRF_Pos)

#define	RTC_CRL_ALRF RTC_CRL_ALRF_Msk

#define	RTC_CRL_OWF_Pos (2U)

#define	RTC_CRL_OWF_Msk (0x1UL << RTC_CRL_OWF_Pos)

#define	RTC_CRL_OWF RTC_CRL_OWF_Msk

#define	RTC_CRL_RSF_Pos (3U)

#define	RTC_CRL_RSF_Msk (0x1UL << RTC_CRL_RSF_Pos)

#define	RTC_CRL_RSF RTC_CRL_RSF_Msk

#define	RTC_CRL_CNF_Pos (4U)

#define	RTC_CRL_CNF_Msk (0x1UL << RTC_CRL_CNF_Pos)

#define	RTC_CRL_CNF RTC_CRL_CNF_Msk

#define	RTC_CRL_RTOFF_Pos (5U)

#define	RTC_CRL_RTOFF_Msk (0x1UL << RTC_CRL_RTOFF_Pos)

#define	RTC_CRL_RTOFF RTC_CRL_RTOFF_Msk

#define	RTC_PRLH_PRL_Pos (0U)

#define	RTC_PRLH_PRL_Msk (0xFUL << RTC_PRLH_PRL_Pos)

#define	RTC_PRLH_PRL RTC_PRLH_PRL_Msk

#define	RTC_PRLL_PRL_Pos (0U)

#define	RTC_PRLL_PRL_Msk (0xFFFFUL << RTC_PRLL_PRL_Pos)

#define	RTC_PRLL_PRL RTC_PRLL_PRL_Msk

#define	RTC_DIVH_RTC_DIV_Pos (0U)

#define	RTC_DIVH_RTC_DIV_Msk (0xFUL << RTC_DIVH_RTC_DIV_Pos)

#define	RTC_DIVH_RTC_DIV RTC_DIVH_RTC_DIV_Msk

#define	RTC_DIVL_RTC_DIV_Pos (0U)

#define	RTC_DIVL_RTC_DIV_Msk (0xFFFFUL << RTC_DIVL_RTC_DIV_Pos)

#define	RTC_DIVL_RTC_DIV RTC_DIVL_RTC_DIV_Msk

#define	RTC_CNTH_RTC_CNT_Pos (0U)

#define	RTC_CNTH_RTC_CNT_Msk (0xFFFFUL << RTC_CNTH_RTC_CNT_Pos)

#define	RTC_CNTH_RTC_CNT RTC_CNTH_RTC_CNT_Msk

#define	RTC_CNTL_RTC_CNT_Pos (0U)

#define	RTC_CNTL_RTC_CNT_Msk (0xFFFFUL << RTC_CNTL_RTC_CNT_Pos)

#define	RTC_CNTL_RTC_CNT RTC_CNTL_RTC_CNT_Msk

#define	RTC_ALRH_RTC_ALR_Pos (0U)

#define	RTC_ALRH_RTC_ALR_Msk (0xFFFFUL << RTC_ALRH_RTC_ALR_Pos)

#define	RTC_ALRH_RTC_ALR RTC_ALRH_RTC_ALR_Msk

#define	RTC_ALRL_RTC_ALR_Pos (0U)

#define	RTC_ALRL_RTC_ALR_Msk (0xFFFFUL << RTC_ALRL_RTC_ALR_Pos)

#define	RTC_ALRL_RTC_ALR RTC_ALRL_RTC_ALR_Msk

#define	IWDG_KR_KEY_Pos (0U)

#define	IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos)

#define	IWDG_KR_KEY IWDG_KR_KEY_Msk

#define	IWDG_PR_PR_Pos (0U)

#define	IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR IWDG_PR_PR_Msk

#define	IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos)

#define	IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos)

#define	IWDG_RLR_RL_Pos (0U)

#define	IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos)

#define	IWDG_RLR_RL IWDG_RLR_RL_Msk

#define	IWDG_SR_PVU_Pos (0U)

#define	IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos)

#define	IWDG_SR_PVU IWDG_SR_PVU_Msk

#define	IWDG_SR_RVU_Pos (1U)

#define	IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos)

#define	IWDG_SR_RVU IWDG_SR_RVU_Msk

#define	WWDG_CR_T_Pos (0U)

#define	WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos)

#define	WWDG_CR_T WWDG_CR_T_Msk

#define	WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos)

#define	WWDG_CR_T0 WWDG_CR_T_0

#define	WWDG_CR_T1 WWDG_CR_T_1

#define	WWDG_CR_T2 WWDG_CR_T_2

#define	WWDG_CR_T3 WWDG_CR_T_3

#define	WWDG_CR_T4 WWDG_CR_T_4

#define	WWDG_CR_T5 WWDG_CR_T_5

#define	WWDG_CR_T6 WWDG_CR_T_6

#define	WWDG_CR_WDGA_Pos (7U)

#define	WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos)

#define	WWDG_CR_WDGA WWDG_CR_WDGA_Msk

#define	WWDG_CFR_W_Pos (0U)

#define	WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W WWDG_CFR_W_Msk

#define	WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos)

#define	WWDG_CFR_W0 WWDG_CFR_W_0

#define	WWDG_CFR_W1 WWDG_CFR_W_1

#define	WWDG_CFR_W2 WWDG_CFR_W_2

#define	WWDG_CFR_W3 WWDG_CFR_W_3

#define	WWDG_CFR_W4 WWDG_CFR_W_4

#define	WWDG_CFR_W5 WWDG_CFR_W_5

#define	WWDG_CFR_W6 WWDG_CFR_W_6

#define	WWDG_CFR_WDGTB_Pos (7U)

#define	WWDG_CFR_WDGTB_Msk (0x3UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk

#define	WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos)

#define	WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0

#define	WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1

#define	WWDG_CFR_EWI_Pos (9U)

#define	WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos)

#define	WWDG_CFR_EWI WWDG_CFR_EWI_Msk

#define	WWDG_SR_EWIF_Pos (0U)

#define	WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos)

#define	WWDG_SR_EWIF WWDG_SR_EWIF_Msk

#define	CAN_MCR_INRQ_Pos (0U)

#define	CAN_MCR_INRQ_Msk (0x1UL << CAN_MCR_INRQ_Pos)

#define	CAN_MCR_INRQ CAN_MCR_INRQ_Msk

#define	CAN_MCR_SLEEP_Pos (1U)

#define	CAN_MCR_SLEEP_Msk (0x1UL << CAN_MCR_SLEEP_Pos)

#define	CAN_MCR_SLEEP CAN_MCR_SLEEP_Msk

#define	CAN_MCR_TXFP_Pos (2U)

#define	CAN_MCR_TXFP_Msk (0x1UL << CAN_MCR_TXFP_Pos)

#define	CAN_MCR_TXFP CAN_MCR_TXFP_Msk

#define	CAN_MCR_RFLM_Pos (3U)

#define	CAN_MCR_RFLM_Msk (0x1UL << CAN_MCR_RFLM_Pos)

#define	CAN_MCR_RFLM CAN_MCR_RFLM_Msk

#define	CAN_MCR_NART_Pos (4U)

#define	CAN_MCR_NART_Msk (0x1UL << CAN_MCR_NART_Pos)

#define	CAN_MCR_NART CAN_MCR_NART_Msk

#define	CAN_MCR_AWUM_Pos (5U)

#define	CAN_MCR_AWUM_Msk (0x1UL << CAN_MCR_AWUM_Pos)

#define	CAN_MCR_AWUM CAN_MCR_AWUM_Msk

#define	CAN_MCR_ABOM_Pos (6U)

#define	CAN_MCR_ABOM_Msk (0x1UL << CAN_MCR_ABOM_Pos)

#define	CAN_MCR_ABOM CAN_MCR_ABOM_Msk

#define	CAN_MCR_TTCM_Pos (7U)

#define	CAN_MCR_TTCM_Msk (0x1UL << CAN_MCR_TTCM_Pos)

#define	CAN_MCR_TTCM CAN_MCR_TTCM_Msk

#define	CAN_MCR_RESET_Pos (15U)

#define	CAN_MCR_RESET_Msk (0x1UL << CAN_MCR_RESET_Pos)

#define	CAN_MCR_RESET CAN_MCR_RESET_Msk

#define	CAN_MCR_DBF_Pos (16U)

#define	CAN_MCR_DBF_Msk (0x1UL << CAN_MCR_DBF_Pos)

#define	CAN_MCR_DBF CAN_MCR_DBF_Msk

#define	CAN_MSR_INAK_Pos (0U)

#define	CAN_MSR_INAK_Msk (0x1UL << CAN_MSR_INAK_Pos)

#define	CAN_MSR_INAK CAN_MSR_INAK_Msk

#define	CAN_MSR_SLAK_Pos (1U)

#define	CAN_MSR_SLAK_Msk (0x1UL << CAN_MSR_SLAK_Pos)

#define	CAN_MSR_SLAK CAN_MSR_SLAK_Msk

#define	CAN_MSR_ERRI_Pos (2U)

#define	CAN_MSR_ERRI_Msk (0x1UL << CAN_MSR_ERRI_Pos)

#define	CAN_MSR_ERRI CAN_MSR_ERRI_Msk

#define	CAN_MSR_WKUI_Pos (3U)

#define	CAN_MSR_WKUI_Msk (0x1UL << CAN_MSR_WKUI_Pos)

#define	CAN_MSR_WKUI CAN_MSR_WKUI_Msk

#define	CAN_MSR_SLAKI_Pos (4U)

#define	CAN_MSR_SLAKI_Msk (0x1UL << CAN_MSR_SLAKI_Pos)

#define	CAN_MSR_SLAKI CAN_MSR_SLAKI_Msk

#define	CAN_MSR_TXM_Pos (8U)

#define	CAN_MSR_TXM_Msk (0x1UL << CAN_MSR_TXM_Pos)

#define	CAN_MSR_TXM CAN_MSR_TXM_Msk

#define	CAN_MSR_RXM_Pos (9U)

#define	CAN_MSR_RXM_Msk (0x1UL << CAN_MSR_RXM_Pos)

#define	CAN_MSR_RXM CAN_MSR_RXM_Msk

#define	CAN_MSR_SAMP_Pos (10U)

#define	CAN_MSR_SAMP_Msk (0x1UL << CAN_MSR_SAMP_Pos)

#define	CAN_MSR_SAMP CAN_MSR_SAMP_Msk

#define	CAN_MSR_RX_Pos (11U)

#define	CAN_MSR_RX_Msk (0x1UL << CAN_MSR_RX_Pos)

#define	CAN_MSR_RX CAN_MSR_RX_Msk

#define	CAN_TSR_RQCP0_Pos (0U)

#define	CAN_TSR_RQCP0_Msk (0x1UL << CAN_TSR_RQCP0_Pos)

#define	CAN_TSR_RQCP0 CAN_TSR_RQCP0_Msk

#define	CAN_TSR_TXOK0_Pos (1U)

#define	CAN_TSR_TXOK0_Msk (0x1UL << CAN_TSR_TXOK0_Pos)

#define	CAN_TSR_TXOK0 CAN_TSR_TXOK0_Msk

#define	CAN_TSR_ALST0_Pos (2U)

#define	CAN_TSR_ALST0_Msk (0x1UL << CAN_TSR_ALST0_Pos)

#define	CAN_TSR_ALST0 CAN_TSR_ALST0_Msk

#define	CAN_TSR_TERR0_Pos (3U)

#define	CAN_TSR_TERR0_Msk (0x1UL << CAN_TSR_TERR0_Pos)

#define	CAN_TSR_TERR0 CAN_TSR_TERR0_Msk

#define	CAN_TSR_ABRQ0_Pos (7U)

#define	CAN_TSR_ABRQ0_Msk (0x1UL << CAN_TSR_ABRQ0_Pos)

#define	CAN_TSR_ABRQ0 CAN_TSR_ABRQ0_Msk

#define	CAN_TSR_RQCP1_Pos (8U)

#define	CAN_TSR_RQCP1_Msk (0x1UL << CAN_TSR_RQCP1_Pos)

#define	CAN_TSR_RQCP1 CAN_TSR_RQCP1_Msk

#define	CAN_TSR_TXOK1_Pos (9U)

#define	CAN_TSR_TXOK1_Msk (0x1UL << CAN_TSR_TXOK1_Pos)

#define	CAN_TSR_TXOK1 CAN_TSR_TXOK1_Msk

#define	CAN_TSR_ALST1_Pos (10U)

#define	CAN_TSR_ALST1_Msk (0x1UL << CAN_TSR_ALST1_Pos)

#define	CAN_TSR_ALST1 CAN_TSR_ALST1_Msk

#define	CAN_TSR_TERR1_Pos (11U)

#define	CAN_TSR_TERR1_Msk (0x1UL << CAN_TSR_TERR1_Pos)

#define	CAN_TSR_TERR1 CAN_TSR_TERR1_Msk

#define	CAN_TSR_ABRQ1_Pos (15U)

#define	CAN_TSR_ABRQ1_Msk (0x1UL << CAN_TSR_ABRQ1_Pos)

#define	CAN_TSR_ABRQ1 CAN_TSR_ABRQ1_Msk

#define	CAN_TSR_RQCP2_Pos (16U)

#define	CAN_TSR_RQCP2_Msk (0x1UL << CAN_TSR_RQCP2_Pos)

#define	CAN_TSR_RQCP2 CAN_TSR_RQCP2_Msk

#define	CAN_TSR_TXOK2_Pos (17U)

#define	CAN_TSR_TXOK2_Msk (0x1UL << CAN_TSR_TXOK2_Pos)

#define	CAN_TSR_TXOK2 CAN_TSR_TXOK2_Msk

#define	CAN_TSR_ALST2_Pos (18U)

#define	CAN_TSR_ALST2_Msk (0x1UL << CAN_TSR_ALST2_Pos)

#define	CAN_TSR_ALST2 CAN_TSR_ALST2_Msk

#define	CAN_TSR_TERR2_Pos (19U)

#define	CAN_TSR_TERR2_Msk (0x1UL << CAN_TSR_TERR2_Pos)

#define	CAN_TSR_TERR2 CAN_TSR_TERR2_Msk

#define	CAN_TSR_ABRQ2_Pos (23U)

#define	CAN_TSR_ABRQ2_Msk (0x1UL << CAN_TSR_ABRQ2_Pos)

#define	CAN_TSR_ABRQ2 CAN_TSR_ABRQ2_Msk

#define	CAN_TSR_CODE_Pos (24U)

#define	CAN_TSR_CODE_Msk (0x3UL << CAN_TSR_CODE_Pos)

#define	CAN_TSR_CODE CAN_TSR_CODE_Msk

#define	CAN_TSR_TME_Pos (26U)

#define	CAN_TSR_TME_Msk (0x7UL << CAN_TSR_TME_Pos)

#define	CAN_TSR_TME CAN_TSR_TME_Msk

#define	CAN_TSR_TME0_Pos (26U)

#define	CAN_TSR_TME0_Msk (0x1UL << CAN_TSR_TME0_Pos)

#define	CAN_TSR_TME0 CAN_TSR_TME0_Msk

#define	CAN_TSR_TME1_Pos (27U)

#define	CAN_TSR_TME1_Msk (0x1UL << CAN_TSR_TME1_Pos)

#define	CAN_TSR_TME1 CAN_TSR_TME1_Msk

#define	CAN_TSR_TME2_Pos (28U)

#define	CAN_TSR_TME2_Msk (0x1UL << CAN_TSR_TME2_Pos)

#define	CAN_TSR_TME2 CAN_TSR_TME2_Msk

#define	CAN_TSR_LOW_Pos (29U)

#define	CAN_TSR_LOW_Msk (0x7UL << CAN_TSR_LOW_Pos)

#define	CAN_TSR_LOW CAN_TSR_LOW_Msk

#define	CAN_TSR_LOW0_Pos (29U)

#define	CAN_TSR_LOW0_Msk (0x1UL << CAN_TSR_LOW0_Pos)

#define	CAN_TSR_LOW0 CAN_TSR_LOW0_Msk

#define	CAN_TSR_LOW1_Pos (30U)

#define	CAN_TSR_LOW1_Msk (0x1UL << CAN_TSR_LOW1_Pos)

#define	CAN_TSR_LOW1 CAN_TSR_LOW1_Msk

#define	CAN_TSR_LOW2_Pos (31U)

#define	CAN_TSR_LOW2_Msk (0x1UL << CAN_TSR_LOW2_Pos)

#define	CAN_TSR_LOW2 CAN_TSR_LOW2_Msk

#define	CAN_RF0R_FMP0_Pos (0U)

#define	CAN_RF0R_FMP0_Msk (0x3UL << CAN_RF0R_FMP0_Pos)

#define	CAN_RF0R_FMP0 CAN_RF0R_FMP0_Msk

#define	CAN_RF0R_FULL0_Pos (3U)

#define	CAN_RF0R_FULL0_Msk (0x1UL << CAN_RF0R_FULL0_Pos)

#define	CAN_RF0R_FULL0 CAN_RF0R_FULL0_Msk

#define	CAN_RF0R_FOVR0_Pos (4U)

#define	CAN_RF0R_FOVR0_Msk (0x1UL << CAN_RF0R_FOVR0_Pos)

#define	CAN_RF0R_FOVR0 CAN_RF0R_FOVR0_Msk

#define	CAN_RF0R_RFOM0_Pos (5U)

#define	CAN_RF0R_RFOM0_Msk (0x1UL << CAN_RF0R_RFOM0_Pos)

#define	CAN_RF0R_RFOM0 CAN_RF0R_RFOM0_Msk

#define	CAN_RF1R_FMP1_Pos (0U)

#define	CAN_RF1R_FMP1_Msk (0x3UL << CAN_RF1R_FMP1_Pos)

#define	CAN_RF1R_FMP1 CAN_RF1R_FMP1_Msk

#define	CAN_RF1R_FULL1_Pos (3U)

#define	CAN_RF1R_FULL1_Msk (0x1UL << CAN_RF1R_FULL1_Pos)

#define	CAN_RF1R_FULL1 CAN_RF1R_FULL1_Msk

#define	CAN_RF1R_FOVR1_Pos (4U)

#define	CAN_RF1R_FOVR1_Msk (0x1UL << CAN_RF1R_FOVR1_Pos)

#define	CAN_RF1R_FOVR1 CAN_RF1R_FOVR1_Msk

#define	CAN_RF1R_RFOM1_Pos (5U)

#define	CAN_RF1R_RFOM1_Msk (0x1UL << CAN_RF1R_RFOM1_Pos)

#define	CAN_RF1R_RFOM1 CAN_RF1R_RFOM1_Msk

#define	CAN_IER_TMEIE_Pos (0U)

#define	CAN_IER_TMEIE_Msk (0x1UL << CAN_IER_TMEIE_Pos)

#define	CAN_IER_TMEIE CAN_IER_TMEIE_Msk

#define	CAN_IER_FMPIE0_Pos (1U)

#define	CAN_IER_FMPIE0_Msk (0x1UL << CAN_IER_FMPIE0_Pos)

#define	CAN_IER_FMPIE0 CAN_IER_FMPIE0_Msk

#define	CAN_IER_FFIE0_Pos (2U)

#define	CAN_IER_FFIE0_Msk (0x1UL << CAN_IER_FFIE0_Pos)

#define	CAN_IER_FFIE0 CAN_IER_FFIE0_Msk

#define	CAN_IER_FOVIE0_Pos (3U)

#define	CAN_IER_FOVIE0_Msk (0x1UL << CAN_IER_FOVIE0_Pos)

#define	CAN_IER_FOVIE0 CAN_IER_FOVIE0_Msk

#define	CAN_IER_FMPIE1_Pos (4U)

#define	CAN_IER_FMPIE1_Msk (0x1UL << CAN_IER_FMPIE1_Pos)

#define	CAN_IER_FMPIE1 CAN_IER_FMPIE1_Msk

#define	CAN_IER_FFIE1_Pos (5U)

#define	CAN_IER_FFIE1_Msk (0x1UL << CAN_IER_FFIE1_Pos)

#define	CAN_IER_FFIE1 CAN_IER_FFIE1_Msk

#define	CAN_IER_FOVIE1_Pos (6U)

#define	CAN_IER_FOVIE1_Msk (0x1UL << CAN_IER_FOVIE1_Pos)

#define	CAN_IER_FOVIE1 CAN_IER_FOVIE1_Msk

#define	CAN_IER_EWGIE_Pos (8U)

#define	CAN_IER_EWGIE_Msk (0x1UL << CAN_IER_EWGIE_Pos)

#define	CAN_IER_EWGIE CAN_IER_EWGIE_Msk

#define	CAN_IER_EPVIE_Pos (9U)

#define	CAN_IER_EPVIE_Msk (0x1UL << CAN_IER_EPVIE_Pos)

#define	CAN_IER_EPVIE CAN_IER_EPVIE_Msk

#define	CAN_IER_BOFIE_Pos (10U)

#define	CAN_IER_BOFIE_Msk (0x1UL << CAN_IER_BOFIE_Pos)

#define	CAN_IER_BOFIE CAN_IER_BOFIE_Msk

#define	CAN_IER_LECIE_Pos (11U)

#define	CAN_IER_LECIE_Msk (0x1UL << CAN_IER_LECIE_Pos)

#define	CAN_IER_LECIE CAN_IER_LECIE_Msk

#define	CAN_IER_ERRIE_Pos (15U)

#define	CAN_IER_ERRIE_Msk (0x1UL << CAN_IER_ERRIE_Pos)

#define	CAN_IER_ERRIE CAN_IER_ERRIE_Msk

#define	CAN_IER_WKUIE_Pos (16U)

#define	CAN_IER_WKUIE_Msk (0x1UL << CAN_IER_WKUIE_Pos)

#define	CAN_IER_WKUIE CAN_IER_WKUIE_Msk

#define	CAN_IER_SLKIE_Pos (17U)

#define	CAN_IER_SLKIE_Msk (0x1UL << CAN_IER_SLKIE_Pos)

#define	CAN_IER_SLKIE CAN_IER_SLKIE_Msk

#define	CAN_ESR_EWGF_Pos (0U)

#define	CAN_ESR_EWGF_Msk (0x1UL << CAN_ESR_EWGF_Pos)

#define	CAN_ESR_EWGF CAN_ESR_EWGF_Msk

#define	CAN_ESR_EPVF_Pos (1U)

#define	CAN_ESR_EPVF_Msk (0x1UL << CAN_ESR_EPVF_Pos)

#define	CAN_ESR_EPVF CAN_ESR_EPVF_Msk

#define	CAN_ESR_BOFF_Pos (2U)

#define	CAN_ESR_BOFF_Msk (0x1UL << CAN_ESR_BOFF_Pos)

#define	CAN_ESR_BOFF CAN_ESR_BOFF_Msk

#define	CAN_ESR_LEC_Pos (4U)

#define	CAN_ESR_LEC_Msk (0x7UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC CAN_ESR_LEC_Msk

#define	CAN_ESR_LEC_0 (0x1UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC_1 (0x2UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_LEC_2 (0x4UL << CAN_ESR_LEC_Pos)

#define	CAN_ESR_TEC_Pos (16U)

#define	CAN_ESR_TEC_Msk (0xFFUL << CAN_ESR_TEC_Pos)

#define	CAN_ESR_TEC CAN_ESR_TEC_Msk

#define	CAN_ESR_REC_Pos (24U)

#define	CAN_ESR_REC_Msk (0xFFUL << CAN_ESR_REC_Pos)

#define	CAN_ESR_REC CAN_ESR_REC_Msk

#define	CAN_BTR_BRP_Pos (0U)

#define	CAN_BTR_BRP_Msk (0x3FFUL << CAN_BTR_BRP_Pos)

#define	CAN_BTR_BRP CAN_BTR_BRP_Msk

#define	CAN_BTR_TS1_Pos (16U)

#define	CAN_BTR_TS1_Msk (0xFUL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1 CAN_BTR_TS1_Msk

#define	CAN_BTR_TS1_0 (0x1UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_1 (0x2UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_2 (0x4UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS1_3 (0x8UL << CAN_BTR_TS1_Pos)

#define	CAN_BTR_TS2_Pos (20U)

#define	CAN_BTR_TS2_Msk (0x7UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2 CAN_BTR_TS2_Msk

#define	CAN_BTR_TS2_0 (0x1UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2_1 (0x2UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_TS2_2 (0x4UL << CAN_BTR_TS2_Pos)

#define	CAN_BTR_SJW_Pos (24U)

#define	CAN_BTR_SJW_Msk (0x3UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_SJW CAN_BTR_SJW_Msk

#define	CAN_BTR_SJW_0 (0x1UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_SJW_1 (0x2UL << CAN_BTR_SJW_Pos)

#define	CAN_BTR_LBKM_Pos (30U)

#define	CAN_BTR_LBKM_Msk (0x1UL << CAN_BTR_LBKM_Pos)

#define	CAN_BTR_LBKM CAN_BTR_LBKM_Msk

#define	CAN_BTR_SILM_Pos (31U)

#define	CAN_BTR_SILM_Msk (0x1UL << CAN_BTR_SILM_Pos)

#define	CAN_BTR_SILM CAN_BTR_SILM_Msk

#define	CAN_TI0R_TXRQ_Pos (0U)

#define	CAN_TI0R_TXRQ_Msk (0x1UL << CAN_TI0R_TXRQ_Pos)

#define	CAN_TI0R_TXRQ CAN_TI0R_TXRQ_Msk

#define	CAN_TI0R_RTR_Pos (1U)

#define	CAN_TI0R_RTR_Msk (0x1UL << CAN_TI0R_RTR_Pos)

#define	CAN_TI0R_RTR CAN_TI0R_RTR_Msk

#define	CAN_TI0R_IDE_Pos (2U)

#define	CAN_TI0R_IDE_Msk (0x1UL << CAN_TI0R_IDE_Pos)

#define	CAN_TI0R_IDE CAN_TI0R_IDE_Msk

#define	CAN_TI0R_EXID_Pos (3U)

#define	CAN_TI0R_EXID_Msk (0x3FFFFUL << CAN_TI0R_EXID_Pos)

#define	CAN_TI0R_EXID CAN_TI0R_EXID_Msk

#define	CAN_TI0R_STID_Pos (21U)

#define	CAN_TI0R_STID_Msk (0x7FFUL << CAN_TI0R_STID_Pos)

#define	CAN_TI0R_STID CAN_TI0R_STID_Msk

#define	CAN_TDT0R_DLC_Pos (0U)

#define	CAN_TDT0R_DLC_Msk (0xFUL << CAN_TDT0R_DLC_Pos)

#define	CAN_TDT0R_DLC CAN_TDT0R_DLC_Msk

#define	CAN_TDT0R_TGT_Pos (8U)

#define	CAN_TDT0R_TGT_Msk (0x1UL << CAN_TDT0R_TGT_Pos)

#define	CAN_TDT0R_TGT CAN_TDT0R_TGT_Msk

#define	CAN_TDT0R_TIME_Pos (16U)

#define	CAN_TDT0R_TIME_Msk (0xFFFFUL << CAN_TDT0R_TIME_Pos)

#define	CAN_TDT0R_TIME CAN_TDT0R_TIME_Msk

#define	CAN_TDL0R_DATA0_Pos (0U)

#define	CAN_TDL0R_DATA0_Msk (0xFFUL << CAN_TDL0R_DATA0_Pos)

#define	CAN_TDL0R_DATA0 CAN_TDL0R_DATA0_Msk

#define	CAN_TDL0R_DATA1_Pos (8U)

#define	CAN_TDL0R_DATA1_Msk (0xFFUL << CAN_TDL0R_DATA1_Pos)

#define	CAN_TDL0R_DATA1 CAN_TDL0R_DATA1_Msk

#define	CAN_TDL0R_DATA2_Pos (16U)

#define	CAN_TDL0R_DATA2_Msk (0xFFUL << CAN_TDL0R_DATA2_Pos)

#define	CAN_TDL0R_DATA2 CAN_TDL0R_DATA2_Msk

#define	CAN_TDL0R_DATA3_Pos (24U)

#define	CAN_TDL0R_DATA3_Msk (0xFFUL << CAN_TDL0R_DATA3_Pos)

#define	CAN_TDL0R_DATA3 CAN_TDL0R_DATA3_Msk

#define	CAN_TDH0R_DATA4_Pos (0U)

#define	CAN_TDH0R_DATA4_Msk (0xFFUL << CAN_TDH0R_DATA4_Pos)

#define	CAN_TDH0R_DATA4 CAN_TDH0R_DATA4_Msk

#define	CAN_TDH0R_DATA5_Pos (8U)

#define	CAN_TDH0R_DATA5_Msk (0xFFUL << CAN_TDH0R_DATA5_Pos)

#define	CAN_TDH0R_DATA5 CAN_TDH0R_DATA5_Msk

#define	CAN_TDH0R_DATA6_Pos (16U)

#define	CAN_TDH0R_DATA6_Msk (0xFFUL << CAN_TDH0R_DATA6_Pos)

#define	CAN_TDH0R_DATA6 CAN_TDH0R_DATA6_Msk

#define	CAN_TDH0R_DATA7_Pos (24U)

#define	CAN_TDH0R_DATA7_Msk (0xFFUL << CAN_TDH0R_DATA7_Pos)

#define	CAN_TDH0R_DATA7 CAN_TDH0R_DATA7_Msk

#define	CAN_TI1R_TXRQ_Pos (0U)

#define	CAN_TI1R_TXRQ_Msk (0x1UL << CAN_TI1R_TXRQ_Pos)

#define	CAN_TI1R_TXRQ CAN_TI1R_TXRQ_Msk

#define	CAN_TI1R_RTR_Pos (1U)

#define	CAN_TI1R_RTR_Msk (0x1UL << CAN_TI1R_RTR_Pos)

#define	CAN_TI1R_RTR CAN_TI1R_RTR_Msk

#define	CAN_TI1R_IDE_Pos (2U)

#define	CAN_TI1R_IDE_Msk (0x1UL << CAN_TI1R_IDE_Pos)

#define	CAN_TI1R_IDE CAN_TI1R_IDE_Msk

#define	CAN_TI1R_EXID_Pos (3U)

#define	CAN_TI1R_EXID_Msk (0x3FFFFUL << CAN_TI1R_EXID_Pos)

#define	CAN_TI1R_EXID CAN_TI1R_EXID_Msk

#define	CAN_TI1R_STID_Pos (21U)

#define	CAN_TI1R_STID_Msk (0x7FFUL << CAN_TI1R_STID_Pos)

#define	CAN_TI1R_STID CAN_TI1R_STID_Msk

#define	CAN_TDT1R_DLC_Pos (0U)

#define	CAN_TDT1R_DLC_Msk (0xFUL << CAN_TDT1R_DLC_Pos)

#define	CAN_TDT1R_DLC CAN_TDT1R_DLC_Msk

#define	CAN_TDT1R_TGT_Pos (8U)

#define	CAN_TDT1R_TGT_Msk (0x1UL << CAN_TDT1R_TGT_Pos)

#define	CAN_TDT1R_TGT CAN_TDT1R_TGT_Msk

#define	CAN_TDT1R_TIME_Pos (16U)

#define	CAN_TDT1R_TIME_Msk (0xFFFFUL << CAN_TDT1R_TIME_Pos)

#define	CAN_TDT1R_TIME CAN_TDT1R_TIME_Msk

#define	CAN_TDL1R_DATA0_Pos (0U)

#define	CAN_TDL1R_DATA0_Msk (0xFFUL << CAN_TDL1R_DATA0_Pos)

#define	CAN_TDL1R_DATA0 CAN_TDL1R_DATA0_Msk

#define	CAN_TDL1R_DATA1_Pos (8U)

#define	CAN_TDL1R_DATA1_Msk (0xFFUL << CAN_TDL1R_DATA1_Pos)

#define	CAN_TDL1R_DATA1 CAN_TDL1R_DATA1_Msk

#define	CAN_TDL1R_DATA2_Pos (16U)

#define	CAN_TDL1R_DATA2_Msk (0xFFUL << CAN_TDL1R_DATA2_Pos)

#define	CAN_TDL1R_DATA2 CAN_TDL1R_DATA2_Msk

#define	CAN_TDL1R_DATA3_Pos (24U)

#define	CAN_TDL1R_DATA3_Msk (0xFFUL << CAN_TDL1R_DATA3_Pos)

#define	CAN_TDL1R_DATA3 CAN_TDL1R_DATA3_Msk

#define	CAN_TDH1R_DATA4_Pos (0U)

#define	CAN_TDH1R_DATA4_Msk (0xFFUL << CAN_TDH1R_DATA4_Pos)

#define	CAN_TDH1R_DATA4 CAN_TDH1R_DATA4_Msk

#define	CAN_TDH1R_DATA5_Pos (8U)

#define	CAN_TDH1R_DATA5_Msk (0xFFUL << CAN_TDH1R_DATA5_Pos)

#define	CAN_TDH1R_DATA5 CAN_TDH1R_DATA5_Msk

#define	CAN_TDH1R_DATA6_Pos (16U)

#define	CAN_TDH1R_DATA6_Msk (0xFFUL << CAN_TDH1R_DATA6_Pos)

#define	CAN_TDH1R_DATA6 CAN_TDH1R_DATA6_Msk

#define	CAN_TDH1R_DATA7_Pos (24U)

#define	CAN_TDH1R_DATA7_Msk (0xFFUL << CAN_TDH1R_DATA7_Pos)

#define	CAN_TDH1R_DATA7 CAN_TDH1R_DATA7_Msk

#define	CAN_TI2R_TXRQ_Pos (0U)

#define	CAN_TI2R_TXRQ_Msk (0x1UL << CAN_TI2R_TXRQ_Pos)

#define	CAN_TI2R_TXRQ CAN_TI2R_TXRQ_Msk

#define	CAN_TI2R_RTR_Pos (1U)

#define	CAN_TI2R_RTR_Msk (0x1UL << CAN_TI2R_RTR_Pos)

#define	CAN_TI2R_RTR CAN_TI2R_RTR_Msk

#define	CAN_TI2R_IDE_Pos (2U)

#define	CAN_TI2R_IDE_Msk (0x1UL << CAN_TI2R_IDE_Pos)

#define	CAN_TI2R_IDE CAN_TI2R_IDE_Msk

#define	CAN_TI2R_EXID_Pos (3U)

#define	CAN_TI2R_EXID_Msk (0x3FFFFUL << CAN_TI2R_EXID_Pos)

#define	CAN_TI2R_EXID CAN_TI2R_EXID_Msk

#define	CAN_TI2R_STID_Pos (21U)

#define	CAN_TI2R_STID_Msk (0x7FFUL << CAN_TI2R_STID_Pos)

#define	CAN_TI2R_STID CAN_TI2R_STID_Msk

#define	CAN_TDT2R_DLC_Pos (0U)

#define	CAN_TDT2R_DLC_Msk (0xFUL << CAN_TDT2R_DLC_Pos)

#define	CAN_TDT2R_DLC CAN_TDT2R_DLC_Msk

#define	CAN_TDT2R_TGT_Pos (8U)

#define	CAN_TDT2R_TGT_Msk (0x1UL << CAN_TDT2R_TGT_Pos)

#define	CAN_TDT2R_TGT CAN_TDT2R_TGT_Msk

#define	CAN_TDT2R_TIME_Pos (16U)

#define	CAN_TDT2R_TIME_Msk (0xFFFFUL << CAN_TDT2R_TIME_Pos)

#define	CAN_TDT2R_TIME CAN_TDT2R_TIME_Msk

#define	CAN_TDL2R_DATA0_Pos (0U)

#define	CAN_TDL2R_DATA0_Msk (0xFFUL << CAN_TDL2R_DATA0_Pos)

#define	CAN_TDL2R_DATA0 CAN_TDL2R_DATA0_Msk

#define	CAN_TDL2R_DATA1_Pos (8U)

#define	CAN_TDL2R_DATA1_Msk (0xFFUL << CAN_TDL2R_DATA1_Pos)

#define	CAN_TDL2R_DATA1 CAN_TDL2R_DATA1_Msk

#define	CAN_TDL2R_DATA2_Pos (16U)

#define	CAN_TDL2R_DATA2_Msk (0xFFUL << CAN_TDL2R_DATA2_Pos)

#define	CAN_TDL2R_DATA2 CAN_TDL2R_DATA2_Msk

#define	CAN_TDL2R_DATA3_Pos (24U)

#define	CAN_TDL2R_DATA3_Msk (0xFFUL << CAN_TDL2R_DATA3_Pos)

#define	CAN_TDL2R_DATA3 CAN_TDL2R_DATA3_Msk

#define	CAN_TDH2R_DATA4_Pos (0U)

#define	CAN_TDH2R_DATA4_Msk (0xFFUL << CAN_TDH2R_DATA4_Pos)

#define	CAN_TDH2R_DATA4 CAN_TDH2R_DATA4_Msk

#define	CAN_TDH2R_DATA5_Pos (8U)

#define	CAN_TDH2R_DATA5_Msk (0xFFUL << CAN_TDH2R_DATA5_Pos)

#define	CAN_TDH2R_DATA5 CAN_TDH2R_DATA5_Msk

#define	CAN_TDH2R_DATA6_Pos (16U)

#define	CAN_TDH2R_DATA6_Msk (0xFFUL << CAN_TDH2R_DATA6_Pos)

#define	CAN_TDH2R_DATA6 CAN_TDH2R_DATA6_Msk

#define	CAN_TDH2R_DATA7_Pos (24U)

#define	CAN_TDH2R_DATA7_Msk (0xFFUL << CAN_TDH2R_DATA7_Pos)

#define	CAN_TDH2R_DATA7 CAN_TDH2R_DATA7_Msk

#define	CAN_RI0R_RTR_Pos (1U)

#define	CAN_RI0R_RTR_Msk (0x1UL << CAN_RI0R_RTR_Pos)

#define	CAN_RI0R_RTR CAN_RI0R_RTR_Msk

#define	CAN_RI0R_IDE_Pos (2U)

#define	CAN_RI0R_IDE_Msk (0x1UL << CAN_RI0R_IDE_Pos)

#define	CAN_RI0R_IDE CAN_RI0R_IDE_Msk

#define	CAN_RI0R_EXID_Pos (3U)

#define	CAN_RI0R_EXID_Msk (0x3FFFFUL << CAN_RI0R_EXID_Pos)

#define	CAN_RI0R_EXID CAN_RI0R_EXID_Msk

#define	CAN_RI0R_STID_Pos (21U)

#define	CAN_RI0R_STID_Msk (0x7FFUL << CAN_RI0R_STID_Pos)

#define	CAN_RI0R_STID CAN_RI0R_STID_Msk

#define	CAN_RDT0R_DLC_Pos (0U)

#define	CAN_RDT0R_DLC_Msk (0xFUL << CAN_RDT0R_DLC_Pos)

#define	CAN_RDT0R_DLC CAN_RDT0R_DLC_Msk

#define	CAN_RDT0R_FMI_Pos (8U)

#define	CAN_RDT0R_FMI_Msk (0xFFUL << CAN_RDT0R_FMI_Pos)

#define	CAN_RDT0R_FMI CAN_RDT0R_FMI_Msk

#define	CAN_RDT0R_TIME_Pos (16U)

#define	CAN_RDT0R_TIME_Msk (0xFFFFUL << CAN_RDT0R_TIME_Pos)

#define	CAN_RDT0R_TIME CAN_RDT0R_TIME_Msk

#define	CAN_RDL0R_DATA0_Pos (0U)

#define	CAN_RDL0R_DATA0_Msk (0xFFUL << CAN_RDL0R_DATA0_Pos)

#define	CAN_RDL0R_DATA0 CAN_RDL0R_DATA0_Msk

#define	CAN_RDL0R_DATA1_Pos (8U)

#define	CAN_RDL0R_DATA1_Msk (0xFFUL << CAN_RDL0R_DATA1_Pos)

#define	CAN_RDL0R_DATA1 CAN_RDL0R_DATA1_Msk

#define	CAN_RDL0R_DATA2_Pos (16U)

#define	CAN_RDL0R_DATA2_Msk (0xFFUL << CAN_RDL0R_DATA2_Pos)

#define	CAN_RDL0R_DATA2 CAN_RDL0R_DATA2_Msk

#define	CAN_RDL0R_DATA3_Pos (24U)

#define	CAN_RDL0R_DATA3_Msk (0xFFUL << CAN_RDL0R_DATA3_Pos)

#define	CAN_RDL0R_DATA3 CAN_RDL0R_DATA3_Msk

#define	CAN_RDH0R_DATA4_Pos (0U)

#define	CAN_RDH0R_DATA4_Msk (0xFFUL << CAN_RDH0R_DATA4_Pos)

#define	CAN_RDH0R_DATA4 CAN_RDH0R_DATA4_Msk

#define	CAN_RDH0R_DATA5_Pos (8U)

#define	CAN_RDH0R_DATA5_Msk (0xFFUL << CAN_RDH0R_DATA5_Pos)

#define	CAN_RDH0R_DATA5 CAN_RDH0R_DATA5_Msk

#define	CAN_RDH0R_DATA6_Pos (16U)

#define	CAN_RDH0R_DATA6_Msk (0xFFUL << CAN_RDH0R_DATA6_Pos)

#define	CAN_RDH0R_DATA6 CAN_RDH0R_DATA6_Msk

#define	CAN_RDH0R_DATA7_Pos (24U)

#define	CAN_RDH0R_DATA7_Msk (0xFFUL << CAN_RDH0R_DATA7_Pos)

#define	CAN_RDH0R_DATA7 CAN_RDH0R_DATA7_Msk

#define	CAN_RI1R_RTR_Pos (1U)

#define	CAN_RI1R_RTR_Msk (0x1UL << CAN_RI1R_RTR_Pos)

#define	CAN_RI1R_RTR CAN_RI1R_RTR_Msk

#define	CAN_RI1R_IDE_Pos (2U)

#define	CAN_RI1R_IDE_Msk (0x1UL << CAN_RI1R_IDE_Pos)

#define	CAN_RI1R_IDE CAN_RI1R_IDE_Msk

#define	CAN_RI1R_EXID_Pos (3U)

#define	CAN_RI1R_EXID_Msk (0x3FFFFUL << CAN_RI1R_EXID_Pos)

#define	CAN_RI1R_EXID CAN_RI1R_EXID_Msk

#define	CAN_RI1R_STID_Pos (21U)

#define	CAN_RI1R_STID_Msk (0x7FFUL << CAN_RI1R_STID_Pos)

#define	CAN_RI1R_STID CAN_RI1R_STID_Msk

#define	CAN_RDT1R_DLC_Pos (0U)

#define	CAN_RDT1R_DLC_Msk (0xFUL << CAN_RDT1R_DLC_Pos)

#define	CAN_RDT1R_DLC CAN_RDT1R_DLC_Msk

#define	CAN_RDT1R_FMI_Pos (8U)

#define	CAN_RDT1R_FMI_Msk (0xFFUL << CAN_RDT1R_FMI_Pos)

#define	CAN_RDT1R_FMI CAN_RDT1R_FMI_Msk

#define	CAN_RDT1R_TIME_Pos (16U)

#define	CAN_RDT1R_TIME_Msk (0xFFFFUL << CAN_RDT1R_TIME_Pos)

#define	CAN_RDT1R_TIME CAN_RDT1R_TIME_Msk

#define	CAN_RDL1R_DATA0_Pos (0U)

#define	CAN_RDL1R_DATA0_Msk (0xFFUL << CAN_RDL1R_DATA0_Pos)

#define	CAN_RDL1R_DATA0 CAN_RDL1R_DATA0_Msk

#define	CAN_RDL1R_DATA1_Pos (8U)

#define	CAN_RDL1R_DATA1_Msk (0xFFUL << CAN_RDL1R_DATA1_Pos)

#define	CAN_RDL1R_DATA1 CAN_RDL1R_DATA1_Msk

#define	CAN_RDL1R_DATA2_Pos (16U)

#define	CAN_RDL1R_DATA2_Msk (0xFFUL << CAN_RDL1R_DATA2_Pos)

#define	CAN_RDL1R_DATA2 CAN_RDL1R_DATA2_Msk

#define	CAN_RDL1R_DATA3_Pos (24U)

#define	CAN_RDL1R_DATA3_Msk (0xFFUL << CAN_RDL1R_DATA3_Pos)

#define	CAN_RDL1R_DATA3 CAN_RDL1R_DATA3_Msk

#define	CAN_RDH1R_DATA4_Pos (0U)

#define	CAN_RDH1R_DATA4_Msk (0xFFUL << CAN_RDH1R_DATA4_Pos)

#define	CAN_RDH1R_DATA4 CAN_RDH1R_DATA4_Msk

#define	CAN_RDH1R_DATA5_Pos (8U)

#define	CAN_RDH1R_DATA5_Msk (0xFFUL << CAN_RDH1R_DATA5_Pos)

#define	CAN_RDH1R_DATA5 CAN_RDH1R_DATA5_Msk

#define	CAN_RDH1R_DATA6_Pos (16U)

#define	CAN_RDH1R_DATA6_Msk (0xFFUL << CAN_RDH1R_DATA6_Pos)

#define	CAN_RDH1R_DATA6 CAN_RDH1R_DATA6_Msk

#define	CAN_RDH1R_DATA7_Pos (24U)

#define	CAN_RDH1R_DATA7_Msk (0xFFUL << CAN_RDH1R_DATA7_Pos)

#define	CAN_RDH1R_DATA7 CAN_RDH1R_DATA7_Msk

#define	CAN_FMR_FINIT_Pos (0U)

#define	CAN_FMR_FINIT_Msk (0x1UL << CAN_FMR_FINIT_Pos)

#define	CAN_FMR_FINIT CAN_FMR_FINIT_Msk

#define	CAN_FMR_CAN2SB_Pos (8U)

#define	CAN_FMR_CAN2SB_Msk (0x3FUL << CAN_FMR_CAN2SB_Pos)

#define	CAN_FMR_CAN2SB CAN_FMR_CAN2SB_Msk

#define	CAN_FM1R_FBM_Pos (0U)

#define	CAN_FM1R_FBM_Msk (0x3FFFUL << CAN_FM1R_FBM_Pos)

#define	CAN_FM1R_FBM CAN_FM1R_FBM_Msk

#define	CAN_FM1R_FBM0_Pos (0U)

#define	CAN_FM1R_FBM0_Msk (0x1UL << CAN_FM1R_FBM0_Pos)

#define	CAN_FM1R_FBM0 CAN_FM1R_FBM0_Msk

#define	CAN_FM1R_FBM1_Pos (1U)

#define	CAN_FM1R_FBM1_Msk (0x1UL << CAN_FM1R_FBM1_Pos)

#define	CAN_FM1R_FBM1 CAN_FM1R_FBM1_Msk

#define	CAN_FM1R_FBM2_Pos (2U)

#define	CAN_FM1R_FBM2_Msk (0x1UL << CAN_FM1R_FBM2_Pos)

#define	CAN_FM1R_FBM2 CAN_FM1R_FBM2_Msk

#define	CAN_FM1R_FBM3_Pos (3U)

#define	CAN_FM1R_FBM3_Msk (0x1UL << CAN_FM1R_FBM3_Pos)

#define	CAN_FM1R_FBM3 CAN_FM1R_FBM3_Msk

#define	CAN_FM1R_FBM4_Pos (4U)

#define	CAN_FM1R_FBM4_Msk (0x1UL << CAN_FM1R_FBM4_Pos)

#define	CAN_FM1R_FBM4 CAN_FM1R_FBM4_Msk

#define	CAN_FM1R_FBM5_Pos (5U)

#define	CAN_FM1R_FBM5_Msk (0x1UL << CAN_FM1R_FBM5_Pos)

#define	CAN_FM1R_FBM5 CAN_FM1R_FBM5_Msk

#define	CAN_FM1R_FBM6_Pos (6U)

#define	CAN_FM1R_FBM6_Msk (0x1UL << CAN_FM1R_FBM6_Pos)

#define	CAN_FM1R_FBM6 CAN_FM1R_FBM6_Msk

#define	CAN_FM1R_FBM7_Pos (7U)

#define	CAN_FM1R_FBM7_Msk (0x1UL << CAN_FM1R_FBM7_Pos)

#define	CAN_FM1R_FBM7 CAN_FM1R_FBM7_Msk

#define	CAN_FM1R_FBM8_Pos (8U)

#define	CAN_FM1R_FBM8_Msk (0x1UL << CAN_FM1R_FBM8_Pos)

#define	CAN_FM1R_FBM8 CAN_FM1R_FBM8_Msk

#define	CAN_FM1R_FBM9_Pos (9U)

#define	CAN_FM1R_FBM9_Msk (0x1UL << CAN_FM1R_FBM9_Pos)

#define	CAN_FM1R_FBM9 CAN_FM1R_FBM9_Msk

#define	CAN_FM1R_FBM10_Pos (10U)

#define	CAN_FM1R_FBM10_Msk (0x1UL << CAN_FM1R_FBM10_Pos)

#define	CAN_FM1R_FBM10 CAN_FM1R_FBM10_Msk

#define	CAN_FM1R_FBM11_Pos (11U)

#define	CAN_FM1R_FBM11_Msk (0x1UL << CAN_FM1R_FBM11_Pos)

#define	CAN_FM1R_FBM11 CAN_FM1R_FBM11_Msk

#define	CAN_FM1R_FBM12_Pos (12U)

#define	CAN_FM1R_FBM12_Msk (0x1UL << CAN_FM1R_FBM12_Pos)

#define	CAN_FM1R_FBM12 CAN_FM1R_FBM12_Msk

#define	CAN_FM1R_FBM13_Pos (13U)

#define	CAN_FM1R_FBM13_Msk (0x1UL << CAN_FM1R_FBM13_Pos)

#define	CAN_FM1R_FBM13 CAN_FM1R_FBM13_Msk

#define	CAN_FM1R_FBM14_Pos (14U)

#define	CAN_FM1R_FBM14_Msk (0x1UL << CAN_FM1R_FBM14_Pos)

#define	CAN_FM1R_FBM14 CAN_FM1R_FBM14_Msk

#define	CAN_FM1R_FBM15_Pos (15U)

#define	CAN_FM1R_FBM15_Msk (0x1UL << CAN_FM1R_FBM15_Pos)

#define	CAN_FM1R_FBM15 CAN_FM1R_FBM15_Msk

#define	CAN_FM1R_FBM16_Pos (16U)

#define	CAN_FM1R_FBM16_Msk (0x1UL << CAN_FM1R_FBM16_Pos)

#define	CAN_FM1R_FBM16 CAN_FM1R_FBM16_Msk

#define	CAN_FM1R_FBM17_Pos (17U)

#define	CAN_FM1R_FBM17_Msk (0x1UL << CAN_FM1R_FBM17_Pos)

#define	CAN_FM1R_FBM17 CAN_FM1R_FBM17_Msk

#define	CAN_FM1R_FBM18_Pos (18U)

#define	CAN_FM1R_FBM18_Msk (0x1UL << CAN_FM1R_FBM18_Pos)

#define	CAN_FM1R_FBM18 CAN_FM1R_FBM18_Msk

#define	CAN_FM1R_FBM19_Pos (19U)

#define	CAN_FM1R_FBM19_Msk (0x1UL << CAN_FM1R_FBM19_Pos)

#define	CAN_FM1R_FBM19 CAN_FM1R_FBM19_Msk

#define	CAN_FM1R_FBM20_Pos (20U)

#define	CAN_FM1R_FBM20_Msk (0x1UL << CAN_FM1R_FBM20_Pos)

#define	CAN_FM1R_FBM20 CAN_FM1R_FBM20_Msk

#define	CAN_FM1R_FBM21_Pos (21U)

#define	CAN_FM1R_FBM21_Msk (0x1UL << CAN_FM1R_FBM21_Pos)

#define	CAN_FM1R_FBM21 CAN_FM1R_FBM21_Msk

#define	CAN_FM1R_FBM22_Pos (22U)

#define	CAN_FM1R_FBM22_Msk (0x1UL << CAN_FM1R_FBM22_Pos)

#define	CAN_FM1R_FBM22 CAN_FM1R_FBM22_Msk

#define	CAN_FM1R_FBM23_Pos (23U)

#define	CAN_FM1R_FBM23_Msk (0x1UL << CAN_FM1R_FBM23_Pos)

#define	CAN_FM1R_FBM23 CAN_FM1R_FBM23_Msk

#define	CAN_FM1R_FBM24_Pos (24U)

#define	CAN_FM1R_FBM24_Msk (0x1UL << CAN_FM1R_FBM24_Pos)

#define	CAN_FM1R_FBM24 CAN_FM1R_FBM24_Msk

#define	CAN_FM1R_FBM25_Pos (25U)

#define	CAN_FM1R_FBM25_Msk (0x1UL << CAN_FM1R_FBM25_Pos)

#define	CAN_FM1R_FBM25 CAN_FM1R_FBM25_Msk

#define	CAN_FM1R_FBM26_Pos (26U)

#define	CAN_FM1R_FBM26_Msk (0x1UL << CAN_FM1R_FBM26_Pos)

#define	CAN_FM1R_FBM26 CAN_FM1R_FBM26_Msk

#define	CAN_FM1R_FBM27_Pos (27U)

#define	CAN_FM1R_FBM27_Msk (0x1UL << CAN_FM1R_FBM27_Pos)

#define	CAN_FM1R_FBM27 CAN_FM1R_FBM27_Msk

#define	CAN_FS1R_FSC_Pos (0U)

#define	CAN_FS1R_FSC_Msk (0x3FFFUL << CAN_FS1R_FSC_Pos)

#define	CAN_FS1R_FSC CAN_FS1R_FSC_Msk

#define	CAN_FS1R_FSC0_Pos (0U)

#define	CAN_FS1R_FSC0_Msk (0x1UL << CAN_FS1R_FSC0_Pos)

#define	CAN_FS1R_FSC0 CAN_FS1R_FSC0_Msk

#define	CAN_FS1R_FSC1_Pos (1U)

#define	CAN_FS1R_FSC1_Msk (0x1UL << CAN_FS1R_FSC1_Pos)

#define	CAN_FS1R_FSC1 CAN_FS1R_FSC1_Msk

#define	CAN_FS1R_FSC2_Pos (2U)

#define	CAN_FS1R_FSC2_Msk (0x1UL << CAN_FS1R_FSC2_Pos)

#define	CAN_FS1R_FSC2 CAN_FS1R_FSC2_Msk

#define	CAN_FS1R_FSC3_Pos (3U)

#define	CAN_FS1R_FSC3_Msk (0x1UL << CAN_FS1R_FSC3_Pos)

#define	CAN_FS1R_FSC3 CAN_FS1R_FSC3_Msk

#define	CAN_FS1R_FSC4_Pos (4U)

#define	CAN_FS1R_FSC4_Msk (0x1UL << CAN_FS1R_FSC4_Pos)

#define	CAN_FS1R_FSC4 CAN_FS1R_FSC4_Msk

#define	CAN_FS1R_FSC5_Pos (5U)

#define	CAN_FS1R_FSC5_Msk (0x1UL << CAN_FS1R_FSC5_Pos)

#define	CAN_FS1R_FSC5 CAN_FS1R_FSC5_Msk

#define	CAN_FS1R_FSC6_Pos (6U)

#define	CAN_FS1R_FSC6_Msk (0x1UL << CAN_FS1R_FSC6_Pos)

#define	CAN_FS1R_FSC6 CAN_FS1R_FSC6_Msk

#define	CAN_FS1R_FSC7_Pos (7U)

#define	CAN_FS1R_FSC7_Msk (0x1UL << CAN_FS1R_FSC7_Pos)

#define	CAN_FS1R_FSC7 CAN_FS1R_FSC7_Msk

#define	CAN_FS1R_FSC8_Pos (8U)

#define	CAN_FS1R_FSC8_Msk (0x1UL << CAN_FS1R_FSC8_Pos)

#define	CAN_FS1R_FSC8 CAN_FS1R_FSC8_Msk

#define	CAN_FS1R_FSC9_Pos (9U)

#define	CAN_FS1R_FSC9_Msk (0x1UL << CAN_FS1R_FSC9_Pos)

#define	CAN_FS1R_FSC9 CAN_FS1R_FSC9_Msk

#define	CAN_FS1R_FSC10_Pos (10U)

#define	CAN_FS1R_FSC10_Msk (0x1UL << CAN_FS1R_FSC10_Pos)

#define	CAN_FS1R_FSC10 CAN_FS1R_FSC10_Msk

#define	CAN_FS1R_FSC11_Pos (11U)

#define	CAN_FS1R_FSC11_Msk (0x1UL << CAN_FS1R_FSC11_Pos)

#define	CAN_FS1R_FSC11 CAN_FS1R_FSC11_Msk

#define	CAN_FS1R_FSC12_Pos (12U)

#define	CAN_FS1R_FSC12_Msk (0x1UL << CAN_FS1R_FSC12_Pos)

#define	CAN_FS1R_FSC12 CAN_FS1R_FSC12_Msk

#define	CAN_FS1R_FSC13_Pos (13U)

#define	CAN_FS1R_FSC13_Msk (0x1UL << CAN_FS1R_FSC13_Pos)

#define	CAN_FS1R_FSC13 CAN_FS1R_FSC13_Msk

#define	CAN_FS1R_FSC14_Pos (14U)

#define	CAN_FS1R_FSC14_Msk (0x1UL << CAN_FS1R_FSC14_Pos)

#define	CAN_FS1R_FSC14 CAN_FS1R_FSC14_Msk

#define	CAN_FS1R_FSC15_Pos (15U)

#define	CAN_FS1R_FSC15_Msk (0x1UL << CAN_FS1R_FSC15_Pos)

#define	CAN_FS1R_FSC15 CAN_FS1R_FSC15_Msk

#define	CAN_FS1R_FSC16_Pos (16U)

#define	CAN_FS1R_FSC16_Msk (0x1UL << CAN_FS1R_FSC16_Pos)

#define	CAN_FS1R_FSC16 CAN_FS1R_FSC16_Msk

#define	CAN_FS1R_FSC17_Pos (17U)

#define	CAN_FS1R_FSC17_Msk (0x1UL << CAN_FS1R_FSC17_Pos)

#define	CAN_FS1R_FSC17 CAN_FS1R_FSC17_Msk

#define	CAN_FS1R_FSC18_Pos (18U)

#define	CAN_FS1R_FSC18_Msk (0x1UL << CAN_FS1R_FSC18_Pos)

#define	CAN_FS1R_FSC18 CAN_FS1R_FSC18_Msk

#define	CAN_FS1R_FSC19_Pos (19U)

#define	CAN_FS1R_FSC19_Msk (0x1UL << CAN_FS1R_FSC19_Pos)

#define	CAN_FS1R_FSC19 CAN_FS1R_FSC19_Msk

#define	CAN_FS1R_FSC20_Pos (20U)

#define	CAN_FS1R_FSC20_Msk (0x1UL << CAN_FS1R_FSC20_Pos)

#define	CAN_FS1R_FSC20 CAN_FS1R_FSC20_Msk

#define	CAN_FS1R_FSC21_Pos (21U)

#define	CAN_FS1R_FSC21_Msk (0x1UL << CAN_FS1R_FSC21_Pos)

#define	CAN_FS1R_FSC21 CAN_FS1R_FSC21_Msk

#define	CAN_FS1R_FSC22_Pos (22U)

#define	CAN_FS1R_FSC22_Msk (0x1UL << CAN_FS1R_FSC22_Pos)

#define	CAN_FS1R_FSC22 CAN_FS1R_FSC22_Msk

#define	CAN_FS1R_FSC23_Pos (23U)

#define	CAN_FS1R_FSC23_Msk (0x1UL << CAN_FS1R_FSC23_Pos)

#define	CAN_FS1R_FSC23 CAN_FS1R_FSC23_Msk

#define	CAN_FS1R_FSC24_Pos (24U)

#define	CAN_FS1R_FSC24_Msk (0x1UL << CAN_FS1R_FSC24_Pos)

#define	CAN_FS1R_FSC24 CAN_FS1R_FSC24_Msk

#define	CAN_FS1R_FSC25_Pos (25U)

#define	CAN_FS1R_FSC25_Msk (0x1UL << CAN_FS1R_FSC25_Pos)

#define	CAN_FS1R_FSC25 CAN_FS1R_FSC25_Msk

#define	CAN_FS1R_FSC26_Pos (26U)

#define	CAN_FS1R_FSC26_Msk (0x1UL << CAN_FS1R_FSC26_Pos)

#define	CAN_FS1R_FSC26 CAN_FS1R_FSC26_Msk

#define	CAN_FS1R_FSC27_Pos (27U)

#define	CAN_FS1R_FSC27_Msk (0x1UL << CAN_FS1R_FSC27_Pos)

#define	CAN_FS1R_FSC27 CAN_FS1R_FSC27_Msk

#define	CAN_FFA1R_FFA_Pos (0U)

#define	CAN_FFA1R_FFA_Msk (0x3FFFUL << CAN_FFA1R_FFA_Pos)

#define	CAN_FFA1R_FFA CAN_FFA1R_FFA_Msk

#define	CAN_FFA1R_FFA0_Pos (0U)

#define	CAN_FFA1R_FFA0_Msk (0x1UL << CAN_FFA1R_FFA0_Pos)

#define	CAN_FFA1R_FFA0 CAN_FFA1R_FFA0_Msk

#define	CAN_FFA1R_FFA1_Pos (1U)

#define	CAN_FFA1R_FFA1_Msk (0x1UL << CAN_FFA1R_FFA1_Pos)

#define	CAN_FFA1R_FFA1 CAN_FFA1R_FFA1_Msk

#define	CAN_FFA1R_FFA2_Pos (2U)

#define	CAN_FFA1R_FFA2_Msk (0x1UL << CAN_FFA1R_FFA2_Pos)

#define	CAN_FFA1R_FFA2 CAN_FFA1R_FFA2_Msk

#define	CAN_FFA1R_FFA3_Pos (3U)

#define	CAN_FFA1R_FFA3_Msk (0x1UL << CAN_FFA1R_FFA3_Pos)

#define	CAN_FFA1R_FFA3 CAN_FFA1R_FFA3_Msk

#define	CAN_FFA1R_FFA4_Pos (4U)

#define	CAN_FFA1R_FFA4_Msk (0x1UL << CAN_FFA1R_FFA4_Pos)

#define	CAN_FFA1R_FFA4 CAN_FFA1R_FFA4_Msk

#define	CAN_FFA1R_FFA5_Pos (5U)

#define	CAN_FFA1R_FFA5_Msk (0x1UL << CAN_FFA1R_FFA5_Pos)

#define	CAN_FFA1R_FFA5 CAN_FFA1R_FFA5_Msk

#define	CAN_FFA1R_FFA6_Pos (6U)

#define	CAN_FFA1R_FFA6_Msk (0x1UL << CAN_FFA1R_FFA6_Pos)

#define	CAN_FFA1R_FFA6 CAN_FFA1R_FFA6_Msk

#define	CAN_FFA1R_FFA7_Pos (7U)

#define	CAN_FFA1R_FFA7_Msk (0x1UL << CAN_FFA1R_FFA7_Pos)

#define	CAN_FFA1R_FFA7 CAN_FFA1R_FFA7_Msk

#define	CAN_FFA1R_FFA8_Pos (8U)

#define	CAN_FFA1R_FFA8_Msk (0x1UL << CAN_FFA1R_FFA8_Pos)

#define	CAN_FFA1R_FFA8 CAN_FFA1R_FFA8_Msk

#define	CAN_FFA1R_FFA9_Pos (9U)

#define	CAN_FFA1R_FFA9_Msk (0x1UL << CAN_FFA1R_FFA9_Pos)

#define	CAN_FFA1R_FFA9 CAN_FFA1R_FFA9_Msk

#define	CAN_FFA1R_FFA10_Pos (10U)

#define	CAN_FFA1R_FFA10_Msk (0x1UL << CAN_FFA1R_FFA10_Pos)

#define	CAN_FFA1R_FFA10 CAN_FFA1R_FFA10_Msk

#define	CAN_FFA1R_FFA11_Pos (11U)

#define	CAN_FFA1R_FFA11_Msk (0x1UL << CAN_FFA1R_FFA11_Pos)

#define	CAN_FFA1R_FFA11 CAN_FFA1R_FFA11_Msk

#define	CAN_FFA1R_FFA12_Pos (12U)

#define	CAN_FFA1R_FFA12_Msk (0x1UL << CAN_FFA1R_FFA12_Pos)

#define	CAN_FFA1R_FFA12 CAN_FFA1R_FFA12_Msk

#define	CAN_FFA1R_FFA13_Pos (13U)

#define	CAN_FFA1R_FFA13_Msk (0x1UL << CAN_FFA1R_FFA13_Pos)

#define	CAN_FFA1R_FFA13 CAN_FFA1R_FFA13_Msk

#define	CAN_FFA1_FFA14_Pos (14U)

#define	CAN_FFA1_FFA14_Msk (0x1UL << CAN_FFA1_FFA14_Pos)

#define	CAN_FFA1_FFA14 CAN_FFA1_FFA14_Msk

#define	CAN_FFA1_FFA15_Pos (15U)

#define	CAN_FFA1_FFA15_Msk (0x1UL << CAN_FFA1_FFA15_Pos)

#define	CAN_FFA1_FFA15 CAN_FFA1_FFA15_Msk

#define	CAN_FFA1_FFA16_Pos (16U)

#define	CAN_FFA1_FFA16_Msk (0x1UL << CAN_FFA1_FFA16_Pos)

#define	CAN_FFA1_FFA16 CAN_FFA1_FFA16_Msk

#define	CAN_FFA1_FFA17_Pos (17U)

#define	CAN_FFA1_FFA17_Msk (0x1UL << CAN_FFA1_FFA17_Pos)

#define	CAN_FFA1_FFA17 CAN_FFA1_FFA17_Msk

#define	CAN_FFA1_FFA18_Pos (18U)

#define	CAN_FFA1_FFA18_Msk (0x1UL << CAN_FFA1_FFA18_Pos)

#define	CAN_FFA1_FFA18 CAN_FFA1_FFA18_Msk

#define	CAN_FFA1_FFA19_Pos (19U)

#define	CAN_FFA1_FFA19_Msk (0x1UL << CAN_FFA1_FFA19_Pos)

#define	CAN_FFA1_FFA19 CAN_FFA1_FFA19_Msk

#define	CAN_FFA1_FFA20_Pos (20U)

#define	CAN_FFA1_FFA20_Msk (0x1UL << CAN_FFA1_FFA20_Pos)

#define	CAN_FFA1_FFA20 CAN_FFA1_FFA20_Msk

#define	CAN_FFA1_FFA21_Pos (21U)

#define	CAN_FFA1_FFA21_Msk (0x1UL << CAN_FFA1_FFA21_Pos)

#define	CAN_FFA1_FFA21 CAN_FFA1_FFA21_Msk

#define	CAN_FFA1_FFA22_Pos (22U)

#define	CAN_FFA1_FFA22_Msk (0x1UL << CAN_FFA1_FFA22_Pos)

#define	CAN_FFA1_FFA22 CAN_FFA1_FFA22_Msk

#define	CAN_FFA1_FFA23_Pos (23U)

#define	CAN_FFA1_FFA23_Msk (0x1UL << CAN_FFA1_FFA23_Pos)

#define	CAN_FFA1_FFA23 CAN_FFA1_FFA23_Msk

#define	CAN_FFA1_FFA24_Pos (24U)

#define	CAN_FFA1_FFA24_Msk (0x1UL << CAN_FFA1_FFA24_Pos)

#define	CAN_FFA1_FFA24 CAN_FFA1_FFA24_Msk

#define	CAN_FFA1_FFA25_Pos (25U)

#define	CAN_FFA1_FFA25_Msk (0x1UL << CAN_FFA1_FFA25_Pos)

#define	CAN_FFA1_FFA25 CAN_FFA1_FFA25_Msk

#define	CAN_FFA1_FFA26_Pos (26U)

#define	CAN_FFA1_FFA26_Msk (0x1UL << CAN_FFA1_FFA26_Pos)

#define	CAN_FFA1_FFA26 CAN_FFA1_FFA26_Msk

#define	CAN_FFA1_FFA27_Pos (27U)

#define	CAN_FFA1_FFA27_Msk (0x1UL << CAN_FFA1_FFA27_Pos)

#define	CAN_FFA1_FFA27 CAN_FFA1_FFA27_Msk

#define	CAN_FA1R_FACT_Pos (0U)

#define	CAN_FA1R_FACT_Msk (0x3FFFUL << CAN_FA1R_FACT_Pos)

#define	CAN_FA1R_FACT CAN_FA1R_FACT_Msk

#define	CAN_FA1R_FACT0_Pos (0U)

#define	CAN_FA1R_FACT0_Msk (0x1UL << CAN_FA1R_FACT0_Pos)

#define	CAN_FA1R_FACT0 CAN_FA1R_FACT0_Msk

#define	CAN_FA1R_FACT1_Pos (1U)

#define	CAN_FA1R_FACT1_Msk (0x1UL << CAN_FA1R_FACT1_Pos)

#define	CAN_FA1R_FACT1 CAN_FA1R_FACT1_Msk

#define	CAN_FA1R_FACT2_Pos (2U)

#define	CAN_FA1R_FACT2_Msk (0x1UL << CAN_FA1R_FACT2_Pos)

#define	CAN_FA1R_FACT2 CAN_FA1R_FACT2_Msk

#define	CAN_FA1R_FACT3_Pos (3U)

#define	CAN_FA1R_FACT3_Msk (0x1UL << CAN_FA1R_FACT3_Pos)

#define	CAN_FA1R_FACT3 CAN_FA1R_FACT3_Msk

#define	CAN_FA1R_FACT4_Pos (4U)

#define	CAN_FA1R_FACT4_Msk (0x1UL << CAN_FA1R_FACT4_Pos)

#define	CAN_FA1R_FACT4 CAN_FA1R_FACT4_Msk

#define	CAN_FA1R_FACT5_Pos (5U)

#define	CAN_FA1R_FACT5_Msk (0x1UL << CAN_FA1R_FACT5_Pos)

#define	CAN_FA1R_FACT5 CAN_FA1R_FACT5_Msk

#define	CAN_FA1R_FACT6_Pos (6U)

#define	CAN_FA1R_FACT6_Msk (0x1UL << CAN_FA1R_FACT6_Pos)

#define	CAN_FA1R_FACT6 CAN_FA1R_FACT6_Msk

#define	CAN_FA1R_FACT7_Pos (7U)

#define	CAN_FA1R_FACT7_Msk (0x1UL << CAN_FA1R_FACT7_Pos)

#define	CAN_FA1R_FACT7 CAN_FA1R_FACT7_Msk

#define	CAN_FA1R_FACT8_Pos (8U)

#define	CAN_FA1R_FACT8_Msk (0x1UL << CAN_FA1R_FACT8_Pos)

#define	CAN_FA1R_FACT8 CAN_FA1R_FACT8_Msk

#define	CAN_FA1R_FACT9_Pos (9U)

#define	CAN_FA1R_FACT9_Msk (0x1UL << CAN_FA1R_FACT9_Pos)

#define	CAN_FA1R_FACT9 CAN_FA1R_FACT9_Msk

#define	CAN_FA1R_FACT10_Pos (10U)

#define	CAN_FA1R_FACT10_Msk (0x1UL << CAN_FA1R_FACT10_Pos)

#define	CAN_FA1R_FACT10 CAN_FA1R_FACT10_Msk

#define	CAN_FA1R_FACT11_Pos (11U)

#define	CAN_FA1R_FACT11_Msk (0x1UL << CAN_FA1R_FACT11_Pos)

#define	CAN_FA1R_FACT11 CAN_FA1R_FACT11_Msk

#define	CAN_FA1R_FACT12_Pos (12U)

#define	CAN_FA1R_FACT12_Msk (0x1UL << CAN_FA1R_FACT12_Pos)

#define	CAN_FA1R_FACT12 CAN_FA1R_FACT12_Msk

#define	CAN_FA1R_FACT13_Pos (13U)

#define	CAN_FA1R_FACT13_Msk (0x1UL << CAN_FA1R_FACT13_Pos)

#define	CAN_FA1R_FACT13 CAN_FA1R_FACT13_Msk

#define	CAN_FA1R_FACT14_Pos (14U)

#define	CAN_FA1R_FACT14_Msk (0x1UL << CAN_FA1R_FACT14_Pos)

#define	CAN_FA1R_FACT14 CAN_FA1R_FACT14_Msk

#define	CAN_FA1R_FACT15_Pos (15U)

#define	CAN_FA1R_FACT15_Msk (0x1UL << CAN_FA1R_FACT15_Pos)

#define	CAN_FA1R_FACT15 CAN_FA1R_FACT15_Msk

#define	CAN_FA1R_FACT16_Pos (16U)

#define	CAN_FA1R_FACT16_Msk (0x1UL << CAN_FA1R_FACT16_Pos)

#define	CAN_FA1R_FACT16 CAN_FA1R_FACT16_Msk

#define	CAN_FA1R_FACT17_Pos (17U)

#define	CAN_FA1R_FACT17_Msk (0x1UL << CAN_FA1R_FACT17_Pos)

#define	CAN_FA1R_FACT17 CAN_FA1R_FACT17_Msk

#define	CAN_FA1R_FACT18_Pos (18U)

#define	CAN_FA1R_FACT18_Msk (0x1UL << CAN_FA1R_FACT18_Pos)

#define	CAN_FA1R_FACT18 CAN_FA1R_FACT18_Msk

#define	CAN_FA1R_FACT19_Pos (19U)

#define	CAN_FA1R_FACT19_Msk (0x1UL << CAN_FA1R_FACT19_Pos)

#define	CAN_FA1R_FACT19 CAN_FA1R_FACT19_Msk

#define	CAN_FA1R_FACT20_Pos (20U)

#define	CAN_FA1R_FACT20_Msk (0x1UL << CAN_FA1R_FACT20_Pos)

#define	CAN_FA1R_FACT20 CAN_FA1R_FACT20_Msk

#define	CAN_FA1R_FACT21_Pos (21U)

#define	CAN_FA1R_FACT21_Msk (0x1UL << CAN_FA1R_FACT21_Pos)

#define	CAN_FA1R_FACT21 CAN_FA1R_FACT21_Msk

#define	CAN_FA1R_FACT22_Pos (22U)

#define	CAN_FA1R_FACT22_Msk (0x1UL << CAN_FA1R_FACT22_Pos)

#define	CAN_FA1R_FACT22 CAN_FA1R_FACT22_Msk

#define	CAN_FA1R_FACT23_Pos (23U)

#define	CAN_FA1R_FACT23_Msk (0x1UL << CAN_FA1R_FACT23_Pos)

#define	CAN_FA1R_FACT23 CAN_FA1R_FACT23_Msk

#define	CAN_FA1R_FACT24_Pos (24U)

#define	CAN_FA1R_FACT24_Msk (0x1UL << CAN_FA1R_FACT24_Pos)

#define	CAN_FA1R_FACT24 CAN_FA1R_FACT24_Msk

#define	CAN_FA1R_FACT25_Pos (25U)

#define	CAN_FA1R_FACT25_Msk (0x1UL << CAN_FA1R_FACT25_Pos)

#define	CAN_FA1R_FACT25 CAN_FA1R_FACT25_Msk

#define	CAN_FA1R_FACT26_Pos (26U)

#define	CAN_FA1R_FACT26_Msk (0x1UL << CAN_FA1R_FACT26_Pos)

#define	CAN_FA1R_FACT26 CAN_FA1R_FACT26_Msk

#define	CAN_FA1R_FACT27_Pos (27U)

#define	CAN_FA1R_FACT27_Msk (0x1UL << CAN_FA1R_FACT27_Pos)

#define	CAN_FA1R_FACT27 CAN_FA1R_FACT27_Msk

#define	CAN_F0R1_FB0_Pos (0U)

#define	CAN_F0R1_FB0_Msk (0x1UL << CAN_F0R1_FB0_Pos)

#define	CAN_F0R1_FB0 CAN_F0R1_FB0_Msk

#define	CAN_F0R1_FB1_Pos (1U)

#define	CAN_F0R1_FB1_Msk (0x1UL << CAN_F0R1_FB1_Pos)

#define	CAN_F0R1_FB1 CAN_F0R1_FB1_Msk

#define	CAN_F0R1_FB2_Pos (2U)

#define	CAN_F0R1_FB2_Msk (0x1UL << CAN_F0R1_FB2_Pos)

#define	CAN_F0R1_FB2 CAN_F0R1_FB2_Msk

#define	CAN_F0R1_FB3_Pos (3U)

#define	CAN_F0R1_FB3_Msk (0x1UL << CAN_F0R1_FB3_Pos)

#define	CAN_F0R1_FB3 CAN_F0R1_FB3_Msk

#define	CAN_F0R1_FB4_Pos (4U)

#define	CAN_F0R1_FB4_Msk (0x1UL << CAN_F0R1_FB4_Pos)

#define	CAN_F0R1_FB4 CAN_F0R1_FB4_Msk

#define	CAN_F0R1_FB5_Pos (5U)

#define	CAN_F0R1_FB5_Msk (0x1UL << CAN_F0R1_FB5_Pos)

#define	CAN_F0R1_FB5 CAN_F0R1_FB5_Msk

#define	CAN_F0R1_FB6_Pos (6U)

#define	CAN_F0R1_FB6_Msk (0x1UL << CAN_F0R1_FB6_Pos)

#define	CAN_F0R1_FB6 CAN_F0R1_FB6_Msk

#define	CAN_F0R1_FB7_Pos (7U)

#define	CAN_F0R1_FB7_Msk (0x1UL << CAN_F0R1_FB7_Pos)

#define	CAN_F0R1_FB7 CAN_F0R1_FB7_Msk

#define	CAN_F0R1_FB8_Pos (8U)

#define	CAN_F0R1_FB8_Msk (0x1UL << CAN_F0R1_FB8_Pos)

#define	CAN_F0R1_FB8 CAN_F0R1_FB8_Msk

#define	CAN_F0R1_FB9_Pos (9U)

#define	CAN_F0R1_FB9_Msk (0x1UL << CAN_F0R1_FB9_Pos)

#define	CAN_F0R1_FB9 CAN_F0R1_FB9_Msk

#define	CAN_F0R1_FB10_Pos (10U)

#define	CAN_F0R1_FB10_Msk (0x1UL << CAN_F0R1_FB10_Pos)

#define	CAN_F0R1_FB10 CAN_F0R1_FB10_Msk

#define	CAN_F0R1_FB11_Pos (11U)

#define	CAN_F0R1_FB11_Msk (0x1UL << CAN_F0R1_FB11_Pos)

#define	CAN_F0R1_FB11 CAN_F0R1_FB11_Msk

#define	CAN_F0R1_FB12_Pos (12U)

#define	CAN_F0R1_FB12_Msk (0x1UL << CAN_F0R1_FB12_Pos)

#define	CAN_F0R1_FB12 CAN_F0R1_FB12_Msk

#define	CAN_F0R1_FB13_Pos (13U)

#define	CAN_F0R1_FB13_Msk (0x1UL << CAN_F0R1_FB13_Pos)

#define	CAN_F0R1_FB13 CAN_F0R1_FB13_Msk

#define	CAN_F0R1_FB14_Pos (14U)

#define	CAN_F0R1_FB14_Msk (0x1UL << CAN_F0R1_FB14_Pos)

#define	CAN_F0R1_FB14 CAN_F0R1_FB14_Msk

#define	CAN_F0R1_FB15_Pos (15U)

#define	CAN_F0R1_FB15_Msk (0x1UL << CAN_F0R1_FB15_Pos)

#define	CAN_F0R1_FB15 CAN_F0R1_FB15_Msk

#define	CAN_F0R1_FB16_Pos (16U)

#define	CAN_F0R1_FB16_Msk (0x1UL << CAN_F0R1_FB16_Pos)

#define	CAN_F0R1_FB16 CAN_F0R1_FB16_Msk

#define	CAN_F0R1_FB17_Pos (17U)

#define	CAN_F0R1_FB17_Msk (0x1UL << CAN_F0R1_FB17_Pos)

#define	CAN_F0R1_FB17 CAN_F0R1_FB17_Msk

#define	CAN_F0R1_FB18_Pos (18U)

#define	CAN_F0R1_FB18_Msk (0x1UL << CAN_F0R1_FB18_Pos)

#define	CAN_F0R1_FB18 CAN_F0R1_FB18_Msk

#define	CAN_F0R1_FB19_Pos (19U)

#define	CAN_F0R1_FB19_Msk (0x1UL << CAN_F0R1_FB19_Pos)

#define	CAN_F0R1_FB19 CAN_F0R1_FB19_Msk

#define	CAN_F0R1_FB20_Pos (20U)

#define	CAN_F0R1_FB20_Msk (0x1UL << CAN_F0R1_FB20_Pos)

#define	CAN_F0R1_FB20 CAN_F0R1_FB20_Msk

#define	CAN_F0R1_FB21_Pos (21U)

#define	CAN_F0R1_FB21_Msk (0x1UL << CAN_F0R1_FB21_Pos)

#define	CAN_F0R1_FB21 CAN_F0R1_FB21_Msk

#define	CAN_F0R1_FB22_Pos (22U)

#define	CAN_F0R1_FB22_Msk (0x1UL << CAN_F0R1_FB22_Pos)

#define	CAN_F0R1_FB22 CAN_F0R1_FB22_Msk

#define	CAN_F0R1_FB23_Pos (23U)

#define	CAN_F0R1_FB23_Msk (0x1UL << CAN_F0R1_FB23_Pos)

#define	CAN_F0R1_FB23 CAN_F0R1_FB23_Msk

#define	CAN_F0R1_FB24_Pos (24U)

#define	CAN_F0R1_FB24_Msk (0x1UL << CAN_F0R1_FB24_Pos)

#define	CAN_F0R1_FB24 CAN_F0R1_FB24_Msk

#define	CAN_F0R1_FB25_Pos (25U)

#define	CAN_F0R1_FB25_Msk (0x1UL << CAN_F0R1_FB25_Pos)

#define	CAN_F0R1_FB25 CAN_F0R1_FB25_Msk

#define	CAN_F0R1_FB26_Pos (26U)

#define	CAN_F0R1_FB26_Msk (0x1UL << CAN_F0R1_FB26_Pos)

#define	CAN_F0R1_FB26 CAN_F0R1_FB26_Msk

#define	CAN_F0R1_FB27_Pos (27U)

#define	CAN_F0R1_FB27_Msk (0x1UL << CAN_F0R1_FB27_Pos)

#define	CAN_F0R1_FB27 CAN_F0R1_FB27_Msk

#define	CAN_F0R1_FB28_Pos (28U)

#define	CAN_F0R1_FB28_Msk (0x1UL << CAN_F0R1_FB28_Pos)

#define	CAN_F0R1_FB28 CAN_F0R1_FB28_Msk

#define	CAN_F0R1_FB29_Pos (29U)

#define	CAN_F0R1_FB29_Msk (0x1UL << CAN_F0R1_FB29_Pos)

#define	CAN_F0R1_FB29 CAN_F0R1_FB29_Msk

#define	CAN_F0R1_FB30_Pos (30U)

#define	CAN_F0R1_FB30_Msk (0x1UL << CAN_F0R1_FB30_Pos)

#define	CAN_F0R1_FB30 CAN_F0R1_FB30_Msk

#define	CAN_F0R1_FB31_Pos (31U)

#define	CAN_F0R1_FB31_Msk (0x1UL << CAN_F0R1_FB31_Pos)

#define	CAN_F0R1_FB31 CAN_F0R1_FB31_Msk

#define	CAN_F1R1_FB0_Pos (0U)

#define	CAN_F1R1_FB0_Msk (0x1UL << CAN_F1R1_FB0_Pos)

#define	CAN_F1R1_FB0 CAN_F1R1_FB0_Msk

#define	CAN_F1R1_FB1_Pos (1U)

#define	CAN_F1R1_FB1_Msk (0x1UL << CAN_F1R1_FB1_Pos)

#define	CAN_F1R1_FB1 CAN_F1R1_FB1_Msk

#define	CAN_F1R1_FB2_Pos (2U)

#define	CAN_F1R1_FB2_Msk (0x1UL << CAN_F1R1_FB2_Pos)

#define	CAN_F1R1_FB2 CAN_F1R1_FB2_Msk

#define	CAN_F1R1_FB3_Pos (3U)

#define	CAN_F1R1_FB3_Msk (0x1UL << CAN_F1R1_FB3_Pos)

#define	CAN_F1R1_FB3 CAN_F1R1_FB3_Msk

#define	CAN_F1R1_FB4_Pos (4U)

#define	CAN_F1R1_FB4_Msk (0x1UL << CAN_F1R1_FB4_Pos)

#define	CAN_F1R1_FB4 CAN_F1R1_FB4_Msk

#define	CAN_F1R1_FB5_Pos (5U)

#define	CAN_F1R1_FB5_Msk (0x1UL << CAN_F1R1_FB5_Pos)

#define	CAN_F1R1_FB5 CAN_F1R1_FB5_Msk

#define	CAN_F1R1_FB6_Pos (6U)

#define	CAN_F1R1_FB6_Msk (0x1UL << CAN_F1R1_FB6_Pos)

#define	CAN_F1R1_FB6 CAN_F1R1_FB6_Msk

#define	CAN_F1R1_FB7_Pos (7U)

#define	CAN_F1R1_FB7_Msk (0x1UL << CAN_F1R1_FB7_Pos)

#define	CAN_F1R1_FB7 CAN_F1R1_FB7_Msk

#define	CAN_F1R1_FB8_Pos (8U)

#define	CAN_F1R1_FB8_Msk (0x1UL << CAN_F1R1_FB8_Pos)

#define	CAN_F1R1_FB8 CAN_F1R1_FB8_Msk

#define	CAN_F1R1_FB9_Pos (9U)

#define	CAN_F1R1_FB9_Msk (0x1UL << CAN_F1R1_FB9_Pos)

#define	CAN_F1R1_FB9 CAN_F1R1_FB9_Msk

#define	CAN_F1R1_FB10_Pos (10U)

#define	CAN_F1R1_FB10_Msk (0x1UL << CAN_F1R1_FB10_Pos)

#define	CAN_F1R1_FB10 CAN_F1R1_FB10_Msk

#define	CAN_F1R1_FB11_Pos (11U)

#define	CAN_F1R1_FB11_Msk (0x1UL << CAN_F1R1_FB11_Pos)

#define	CAN_F1R1_FB11 CAN_F1R1_FB11_Msk

#define	CAN_F1R1_FB12_Pos (12U)

#define	CAN_F1R1_FB12_Msk (0x1UL << CAN_F1R1_FB12_Pos)

#define	CAN_F1R1_FB12 CAN_F1R1_FB12_Msk

#define	CAN_F1R1_FB13_Pos (13U)

#define	CAN_F1R1_FB13_Msk (0x1UL << CAN_F1R1_FB13_Pos)

#define	CAN_F1R1_FB13 CAN_F1R1_FB13_Msk

#define	CAN_F1R1_FB14_Pos (14U)

#define	CAN_F1R1_FB14_Msk (0x1UL << CAN_F1R1_FB14_Pos)

#define	CAN_F1R1_FB14 CAN_F1R1_FB14_Msk

#define	CAN_F1R1_FB15_Pos (15U)

#define	CAN_F1R1_FB15_Msk (0x1UL << CAN_F1R1_FB15_Pos)

#define	CAN_F1R1_FB15 CAN_F1R1_FB15_Msk

#define	CAN_F1R1_FB16_Pos (16U)

#define	CAN_F1R1_FB16_Msk (0x1UL << CAN_F1R1_FB16_Pos)

#define	CAN_F1R1_FB16 CAN_F1R1_FB16_Msk

#define	CAN_F1R1_FB17_Pos (17U)

#define	CAN_F1R1_FB17_Msk (0x1UL << CAN_F1R1_FB17_Pos)

#define	CAN_F1R1_FB17 CAN_F1R1_FB17_Msk

#define	CAN_F1R1_FB18_Pos (18U)

#define	CAN_F1R1_FB18_Msk (0x1UL << CAN_F1R1_FB18_Pos)

#define	CAN_F1R1_FB18 CAN_F1R1_FB18_Msk

#define	CAN_F1R1_FB19_Pos (19U)

#define	CAN_F1R1_FB19_Msk (0x1UL << CAN_F1R1_FB19_Pos)

#define	CAN_F1R1_FB19 CAN_F1R1_FB19_Msk

#define	CAN_F1R1_FB20_Pos (20U)

#define	CAN_F1R1_FB20_Msk (0x1UL << CAN_F1R1_FB20_Pos)

#define	CAN_F1R1_FB20 CAN_F1R1_FB20_Msk

#define	CAN_F1R1_FB21_Pos (21U)

#define	CAN_F1R1_FB21_Msk (0x1UL << CAN_F1R1_FB21_Pos)

#define	CAN_F1R1_FB21 CAN_F1R1_FB21_Msk

#define	CAN_F1R1_FB22_Pos (22U)

#define	CAN_F1R1_FB22_Msk (0x1UL << CAN_F1R1_FB22_Pos)

#define	CAN_F1R1_FB22 CAN_F1R1_FB22_Msk

#define	CAN_F1R1_FB23_Pos (23U)

#define	CAN_F1R1_FB23_Msk (0x1UL << CAN_F1R1_FB23_Pos)

#define	CAN_F1R1_FB23 CAN_F1R1_FB23_Msk

#define	CAN_F1R1_FB24_Pos (24U)

#define	CAN_F1R1_FB24_Msk (0x1UL << CAN_F1R1_FB24_Pos)

#define	CAN_F1R1_FB24 CAN_F1R1_FB24_Msk

#define	CAN_F1R1_FB25_Pos (25U)

#define	CAN_F1R1_FB25_Msk (0x1UL << CAN_F1R1_FB25_Pos)

#define	CAN_F1R1_FB25 CAN_F1R1_FB25_Msk

#define	CAN_F1R1_FB26_Pos (26U)

#define	CAN_F1R1_FB26_Msk (0x1UL << CAN_F1R1_FB26_Pos)

#define	CAN_F1R1_FB26 CAN_F1R1_FB26_Msk

#define	CAN_F1R1_FB27_Pos (27U)

#define	CAN_F1R1_FB27_Msk (0x1UL << CAN_F1R1_FB27_Pos)

#define	CAN_F1R1_FB27 CAN_F1R1_FB27_Msk

#define	CAN_F1R1_FB28_Pos (28U)

#define	CAN_F1R1_FB28_Msk (0x1UL << CAN_F1R1_FB28_Pos)

#define	CAN_F1R1_FB28 CAN_F1R1_FB28_Msk

#define	CAN_F1R1_FB29_Pos (29U)

#define	CAN_F1R1_FB29_Msk (0x1UL << CAN_F1R1_FB29_Pos)

#define	CAN_F1R1_FB29 CAN_F1R1_FB29_Msk

#define	CAN_F1R1_FB30_Pos (30U)

#define	CAN_F1R1_FB30_Msk (0x1UL << CAN_F1R1_FB30_Pos)

#define	CAN_F1R1_FB30 CAN_F1R1_FB30_Msk

#define	CAN_F1R1_FB31_Pos (31U)

#define	CAN_F1R1_FB31_Msk (0x1UL << CAN_F1R1_FB31_Pos)

#define	CAN_F1R1_FB31 CAN_F1R1_FB31_Msk

#define	CAN_F2R1_FB0_Pos (0U)

#define	CAN_F2R1_FB0_Msk (0x1UL << CAN_F2R1_FB0_Pos)

#define	CAN_F2R1_FB0 CAN_F2R1_FB0_Msk

#define	CAN_F2R1_FB1_Pos (1U)

#define	CAN_F2R1_FB1_Msk (0x1UL << CAN_F2R1_FB1_Pos)

#define	CAN_F2R1_FB1 CAN_F2R1_FB1_Msk

#define	CAN_F2R1_FB2_Pos (2U)

#define	CAN_F2R1_FB2_Msk (0x1UL << CAN_F2R1_FB2_Pos)

#define	CAN_F2R1_FB2 CAN_F2R1_FB2_Msk

#define	CAN_F2R1_FB3_Pos (3U)

#define	CAN_F2R1_FB3_Msk (0x1UL << CAN_F2R1_FB3_Pos)

#define	CAN_F2R1_FB3 CAN_F2R1_FB3_Msk

#define	CAN_F2R1_FB4_Pos (4U)

#define	CAN_F2R1_FB4_Msk (0x1UL << CAN_F2R1_FB4_Pos)

#define	CAN_F2R1_FB4 CAN_F2R1_FB4_Msk

#define	CAN_F2R1_FB5_Pos (5U)

#define	CAN_F2R1_FB5_Msk (0x1UL << CAN_F2R1_FB5_Pos)

#define	CAN_F2R1_FB5 CAN_F2R1_FB5_Msk

#define	CAN_F2R1_FB6_Pos (6U)

#define	CAN_F2R1_FB6_Msk (0x1UL << CAN_F2R1_FB6_Pos)

#define	CAN_F2R1_FB6 CAN_F2R1_FB6_Msk

#define	CAN_F2R1_FB7_Pos (7U)

#define	CAN_F2R1_FB7_Msk (0x1UL << CAN_F2R1_FB7_Pos)

#define	CAN_F2R1_FB7 CAN_F2R1_FB7_Msk

#define	CAN_F2R1_FB8_Pos (8U)

#define	CAN_F2R1_FB8_Msk (0x1UL << CAN_F2R1_FB8_Pos)

#define	CAN_F2R1_FB8 CAN_F2R1_FB8_Msk

#define	CAN_F2R1_FB9_Pos (9U)

#define	CAN_F2R1_FB9_Msk (0x1UL << CAN_F2R1_FB9_Pos)

#define	CAN_F2R1_FB9 CAN_F2R1_FB9_Msk

#define	CAN_F2R1_FB10_Pos (10U)

#define	CAN_F2R1_FB10_Msk (0x1UL << CAN_F2R1_FB10_Pos)

#define	CAN_F2R1_FB10 CAN_F2R1_FB10_Msk

#define	CAN_F2R1_FB11_Pos (11U)

#define	CAN_F2R1_FB11_Msk (0x1UL << CAN_F2R1_FB11_Pos)

#define	CAN_F2R1_FB11 CAN_F2R1_FB11_Msk

#define	CAN_F2R1_FB12_Pos (12U)

#define	CAN_F2R1_FB12_Msk (0x1UL << CAN_F2R1_FB12_Pos)

#define	CAN_F2R1_FB12 CAN_F2R1_FB12_Msk

#define	CAN_F2R1_FB13_Pos (13U)

#define	CAN_F2R1_FB13_Msk (0x1UL << CAN_F2R1_FB13_Pos)

#define	CAN_F2R1_FB13 CAN_F2R1_FB13_Msk

#define	CAN_F2R1_FB14_Pos (14U)

#define	CAN_F2R1_FB14_Msk (0x1UL << CAN_F2R1_FB14_Pos)

#define	CAN_F2R1_FB14 CAN_F2R1_FB14_Msk

#define	CAN_F2R1_FB15_Pos (15U)

#define	CAN_F2R1_FB15_Msk (0x1UL << CAN_F2R1_FB15_Pos)

#define	CAN_F2R1_FB15 CAN_F2R1_FB15_Msk

#define	CAN_F2R1_FB16_Pos (16U)

#define	CAN_F2R1_FB16_Msk (0x1UL << CAN_F2R1_FB16_Pos)

#define	CAN_F2R1_FB16 CAN_F2R1_FB16_Msk

#define	CAN_F2R1_FB17_Pos (17U)

#define	CAN_F2R1_FB17_Msk (0x1UL << CAN_F2R1_FB17_Pos)

#define	CAN_F2R1_FB17 CAN_F2R1_FB17_Msk

#define	CAN_F2R1_FB18_Pos (18U)

#define	CAN_F2R1_FB18_Msk (0x1UL << CAN_F2R1_FB18_Pos)

#define	CAN_F2R1_FB18 CAN_F2R1_FB18_Msk

#define	CAN_F2R1_FB19_Pos (19U)

#define	CAN_F2R1_FB19_Msk (0x1UL << CAN_F2R1_FB19_Pos)

#define	CAN_F2R1_FB19 CAN_F2R1_FB19_Msk

#define	CAN_F2R1_FB20_Pos (20U)

#define	CAN_F2R1_FB20_Msk (0x1UL << CAN_F2R1_FB20_Pos)

#define	CAN_F2R1_FB20 CAN_F2R1_FB20_Msk

#define	CAN_F2R1_FB21_Pos (21U)

#define	CAN_F2R1_FB21_Msk (0x1UL << CAN_F2R1_FB21_Pos)

#define	CAN_F2R1_FB21 CAN_F2R1_FB21_Msk

#define	CAN_F2R1_FB22_Pos (22U)

#define	CAN_F2R1_FB22_Msk (0x1UL << CAN_F2R1_FB22_Pos)

#define	CAN_F2R1_FB22 CAN_F2R1_FB22_Msk

#define	CAN_F2R1_FB23_Pos (23U)

#define	CAN_F2R1_FB23_Msk (0x1UL << CAN_F2R1_FB23_Pos)

#define	CAN_F2R1_FB23 CAN_F2R1_FB23_Msk

#define	CAN_F2R1_FB24_Pos (24U)

#define	CAN_F2R1_FB24_Msk (0x1UL << CAN_F2R1_FB24_Pos)

#define	CAN_F2R1_FB24 CAN_F2R1_FB24_Msk

#define	CAN_F2R1_FB25_Pos (25U)

#define	CAN_F2R1_FB25_Msk (0x1UL << CAN_F2R1_FB25_Pos)

#define	CAN_F2R1_FB25 CAN_F2R1_FB25_Msk

#define	CAN_F2R1_FB26_Pos (26U)

#define	CAN_F2R1_FB26_Msk (0x1UL << CAN_F2R1_FB26_Pos)

#define	CAN_F2R1_FB26 CAN_F2R1_FB26_Msk

#define	CAN_F2R1_FB27_Pos (27U)

#define	CAN_F2R1_FB27_Msk (0x1UL << CAN_F2R1_FB27_Pos)

#define	CAN_F2R1_FB27 CAN_F2R1_FB27_Msk

#define	CAN_F2R1_FB28_Pos (28U)

#define	CAN_F2R1_FB28_Msk (0x1UL << CAN_F2R1_FB28_Pos)

#define	CAN_F2R1_FB28 CAN_F2R1_FB28_Msk

#define	CAN_F2R1_FB29_Pos (29U)

#define	CAN_F2R1_FB29_Msk (0x1UL << CAN_F2R1_FB29_Pos)

#define	CAN_F2R1_FB29 CAN_F2R1_FB29_Msk

#define	CAN_F2R1_FB30_Pos (30U)

#define	CAN_F2R1_FB30_Msk (0x1UL << CAN_F2R1_FB30_Pos)

#define	CAN_F2R1_FB30 CAN_F2R1_FB30_Msk

#define	CAN_F2R1_FB31_Pos (31U)

#define	CAN_F2R1_FB31_Msk (0x1UL << CAN_F2R1_FB31_Pos)

#define	CAN_F2R1_FB31 CAN_F2R1_FB31_Msk

#define	CAN_F3R1_FB0_Pos (0U)

#define	CAN_F3R1_FB0_Msk (0x1UL << CAN_F3R1_FB0_Pos)

#define	CAN_F3R1_FB0 CAN_F3R1_FB0_Msk

#define	CAN_F3R1_FB1_Pos (1U)

#define	CAN_F3R1_FB1_Msk (0x1UL << CAN_F3R1_FB1_Pos)

#define	CAN_F3R1_FB1 CAN_F3R1_FB1_Msk

#define	CAN_F3R1_FB2_Pos (2U)

#define	CAN_F3R1_FB2_Msk (0x1UL << CAN_F3R1_FB2_Pos)

#define	CAN_F3R1_FB2 CAN_F3R1_FB2_Msk

#define	CAN_F3R1_FB3_Pos (3U)

#define	CAN_F3R1_FB3_Msk (0x1UL << CAN_F3R1_FB3_Pos)

#define	CAN_F3R1_FB3 CAN_F3R1_FB3_Msk

#define	CAN_F3R1_FB4_Pos (4U)

#define	CAN_F3R1_FB4_Msk (0x1UL << CAN_F3R1_FB4_Pos)

#define	CAN_F3R1_FB4 CAN_F3R1_FB4_Msk

#define	CAN_F3R1_FB5_Pos (5U)

#define	CAN_F3R1_FB5_Msk (0x1UL << CAN_F3R1_FB5_Pos)

#define	CAN_F3R1_FB5 CAN_F3R1_FB5_Msk

#define	CAN_F3R1_FB6_Pos (6U)

#define	CAN_F3R1_FB6_Msk (0x1UL << CAN_F3R1_FB6_Pos)

#define	CAN_F3R1_FB6 CAN_F3R1_FB6_Msk

#define	CAN_F3R1_FB7_Pos (7U)

#define	CAN_F3R1_FB7_Msk (0x1UL << CAN_F3R1_FB7_Pos)

#define	CAN_F3R1_FB7 CAN_F3R1_FB7_Msk

#define	CAN_F3R1_FB8_Pos (8U)

#define	CAN_F3R1_FB8_Msk (0x1UL << CAN_F3R1_FB8_Pos)

#define	CAN_F3R1_FB8 CAN_F3R1_FB8_Msk

#define	CAN_F3R1_FB9_Pos (9U)

#define	CAN_F3R1_FB9_Msk (0x1UL << CAN_F3R1_FB9_Pos)

#define	CAN_F3R1_FB9 CAN_F3R1_FB9_Msk

#define	CAN_F3R1_FB10_Pos (10U)

#define	CAN_F3R1_FB10_Msk (0x1UL << CAN_F3R1_FB10_Pos)

#define	CAN_F3R1_FB10 CAN_F3R1_FB10_Msk

#define	CAN_F3R1_FB11_Pos (11U)

#define	CAN_F3R1_FB11_Msk (0x1UL << CAN_F3R1_FB11_Pos)

#define	CAN_F3R1_FB11 CAN_F3R1_FB11_Msk

#define	CAN_F3R1_FB12_Pos (12U)

#define	CAN_F3R1_FB12_Msk (0x1UL << CAN_F3R1_FB12_Pos)

#define	CAN_F3R1_FB12 CAN_F3R1_FB12_Msk

#define	CAN_F3R1_FB13_Pos (13U)

#define	CAN_F3R1_FB13_Msk (0x1UL << CAN_F3R1_FB13_Pos)

#define	CAN_F3R1_FB13 CAN_F3R1_FB13_Msk

#define	CAN_F3R1_FB14_Pos (14U)

#define	CAN_F3R1_FB14_Msk (0x1UL << CAN_F3R1_FB14_Pos)

#define	CAN_F3R1_FB14 CAN_F3R1_FB14_Msk

#define	CAN_F3R1_FB15_Pos (15U)

#define	CAN_F3R1_FB15_Msk (0x1UL << CAN_F3R1_FB15_Pos)

#define	CAN_F3R1_FB15 CAN_F3R1_FB15_Msk

#define	CAN_F3R1_FB16_Pos (16U)

#define	CAN_F3R1_FB16_Msk (0x1UL << CAN_F3R1_FB16_Pos)

#define	CAN_F3R1_FB16 CAN_F3R1_FB16_Msk

#define	CAN_F3R1_FB17_Pos (17U)

#define	CAN_F3R1_FB17_Msk (0x1UL << CAN_F3R1_FB17_Pos)

#define	CAN_F3R1_FB17 CAN_F3R1_FB17_Msk

#define	CAN_F3R1_FB18_Pos (18U)

#define	CAN_F3R1_FB18_Msk (0x1UL << CAN_F3R1_FB18_Pos)

#define	CAN_F3R1_FB18 CAN_F3R1_FB18_Msk

#define	CAN_F3R1_FB19_Pos (19U)

#define	CAN_F3R1_FB19_Msk (0x1UL << CAN_F3R1_FB19_Pos)

#define	CAN_F3R1_FB19 CAN_F3R1_FB19_Msk

#define	CAN_F3R1_FB20_Pos (20U)

#define	CAN_F3R1_FB20_Msk (0x1UL << CAN_F3R1_FB20_Pos)

#define	CAN_F3R1_FB20 CAN_F3R1_FB20_Msk

#define	CAN_F3R1_FB21_Pos (21U)

#define	CAN_F3R1_FB21_Msk (0x1UL << CAN_F3R1_FB21_Pos)

#define	CAN_F3R1_FB21 CAN_F3R1_FB21_Msk

#define	CAN_F3R1_FB22_Pos (22U)

#define	CAN_F3R1_FB22_Msk (0x1UL << CAN_F3R1_FB22_Pos)

#define	CAN_F3R1_FB22 CAN_F3R1_FB22_Msk

#define	CAN_F3R1_FB23_Pos (23U)

#define	CAN_F3R1_FB23_Msk (0x1UL << CAN_F3R1_FB23_Pos)

#define	CAN_F3R1_FB23 CAN_F3R1_FB23_Msk

#define	CAN_F3R1_FB24_Pos (24U)

#define	CAN_F3R1_FB24_Msk (0x1UL << CAN_F3R1_FB24_Pos)

#define	CAN_F3R1_FB24 CAN_F3R1_FB24_Msk

#define	CAN_F3R1_FB25_Pos (25U)

#define	CAN_F3R1_FB25_Msk (0x1UL << CAN_F3R1_FB25_Pos)

#define	CAN_F3R1_FB25 CAN_F3R1_FB25_Msk

#define	CAN_F3R1_FB26_Pos (26U)

#define	CAN_F3R1_FB26_Msk (0x1UL << CAN_F3R1_FB26_Pos)

#define	CAN_F3R1_FB26 CAN_F3R1_FB26_Msk

#define	CAN_F3R1_FB27_Pos (27U)

#define	CAN_F3R1_FB27_Msk (0x1UL << CAN_F3R1_FB27_Pos)

#define	CAN_F3R1_FB27 CAN_F3R1_FB27_Msk

#define	CAN_F3R1_FB28_Pos (28U)

#define	CAN_F3R1_FB28_Msk (0x1UL << CAN_F3R1_FB28_Pos)

#define	CAN_F3R1_FB28 CAN_F3R1_FB28_Msk

#define	CAN_F3R1_FB29_Pos (29U)

#define	CAN_F3R1_FB29_Msk (0x1UL << CAN_F3R1_FB29_Pos)

#define	CAN_F3R1_FB29 CAN_F3R1_FB29_Msk

#define	CAN_F3R1_FB30_Pos (30U)

#define	CAN_F3R1_FB30_Msk (0x1UL << CAN_F3R1_FB30_Pos)

#define	CAN_F3R1_FB30 CAN_F3R1_FB30_Msk

#define	CAN_F3R1_FB31_Pos (31U)

#define	CAN_F3R1_FB31_Msk (0x1UL << CAN_F3R1_FB31_Pos)

#define	CAN_F3R1_FB31 CAN_F3R1_FB31_Msk

#define	CAN_F4R1_FB0_Pos (0U)

#define	CAN_F4R1_FB0_Msk (0x1UL << CAN_F4R1_FB0_Pos)

#define	CAN_F4R1_FB0 CAN_F4R1_FB0_Msk

#define	CAN_F4R1_FB1_Pos (1U)

#define	CAN_F4R1_FB1_Msk (0x1UL << CAN_F4R1_FB1_Pos)

#define	CAN_F4R1_FB1 CAN_F4R1_FB1_Msk

#define	CAN_F4R1_FB2_Pos (2U)

#define	CAN_F4R1_FB2_Msk (0x1UL << CAN_F4R1_FB2_Pos)

#define	CAN_F4R1_FB2 CAN_F4R1_FB2_Msk

#define	CAN_F4R1_FB3_Pos (3U)

#define	CAN_F4R1_FB3_Msk (0x1UL << CAN_F4R1_FB3_Pos)

#define	CAN_F4R1_FB3 CAN_F4R1_FB3_Msk

#define	CAN_F4R1_FB4_Pos (4U)

#define	CAN_F4R1_FB4_Msk (0x1UL << CAN_F4R1_FB4_Pos)

#define	CAN_F4R1_FB4 CAN_F4R1_FB4_Msk

#define	CAN_F4R1_FB5_Pos (5U)

#define	CAN_F4R1_FB5_Msk (0x1UL << CAN_F4R1_FB5_Pos)

#define	CAN_F4R1_FB5 CAN_F4R1_FB5_Msk

#define	CAN_F4R1_FB6_Pos (6U)

#define	CAN_F4R1_FB6_Msk (0x1UL << CAN_F4R1_FB6_Pos)

#define	CAN_F4R1_FB6 CAN_F4R1_FB6_Msk

#define	CAN_F4R1_FB7_Pos (7U)

#define	CAN_F4R1_FB7_Msk (0x1UL << CAN_F4R1_FB7_Pos)

#define	CAN_F4R1_FB7 CAN_F4R1_FB7_Msk

#define	CAN_F4R1_FB8_Pos (8U)

#define	CAN_F4R1_FB8_Msk (0x1UL << CAN_F4R1_FB8_Pos)

#define	CAN_F4R1_FB8 CAN_F4R1_FB8_Msk

#define	CAN_F4R1_FB9_Pos (9U)

#define	CAN_F4R1_FB9_Msk (0x1UL << CAN_F4R1_FB9_Pos)

#define	CAN_F4R1_FB9 CAN_F4R1_FB9_Msk

#define	CAN_F4R1_FB10_Pos (10U)

#define	CAN_F4R1_FB10_Msk (0x1UL << CAN_F4R1_FB10_Pos)

#define	CAN_F4R1_FB10 CAN_F4R1_FB10_Msk

#define	CAN_F4R1_FB11_Pos (11U)

#define	CAN_F4R1_FB11_Msk (0x1UL << CAN_F4R1_FB11_Pos)

#define	CAN_F4R1_FB11 CAN_F4R1_FB11_Msk

#define	CAN_F4R1_FB12_Pos (12U)

#define	CAN_F4R1_FB12_Msk (0x1UL << CAN_F4R1_FB12_Pos)

#define	CAN_F4R1_FB12 CAN_F4R1_FB12_Msk

#define	CAN_F4R1_FB13_Pos (13U)

#define	CAN_F4R1_FB13_Msk (0x1UL << CAN_F4R1_FB13_Pos)

#define	CAN_F4R1_FB13 CAN_F4R1_FB13_Msk

#define	CAN_F4R1_FB14_Pos (14U)

#define	CAN_F4R1_FB14_Msk (0x1UL << CAN_F4R1_FB14_Pos)

#define	CAN_F4R1_FB14 CAN_F4R1_FB14_Msk

#define	CAN_F4R1_FB15_Pos (15U)

#define	CAN_F4R1_FB15_Msk (0x1UL << CAN_F4R1_FB15_Pos)

#define	CAN_F4R1_FB15 CAN_F4R1_FB15_Msk

#define	CAN_F4R1_FB16_Pos (16U)

#define	CAN_F4R1_FB16_Msk (0x1UL << CAN_F4R1_FB16_Pos)

#define	CAN_F4R1_FB16 CAN_F4R1_FB16_Msk

#define	CAN_F4R1_FB17_Pos (17U)

#define	CAN_F4R1_FB17_Msk (0x1UL << CAN_F4R1_FB17_Pos)

#define	CAN_F4R1_FB17 CAN_F4R1_FB17_Msk

#define	CAN_F4R1_FB18_Pos (18U)

#define	CAN_F4R1_FB18_Msk (0x1UL << CAN_F4R1_FB18_Pos)

#define	CAN_F4R1_FB18 CAN_F4R1_FB18_Msk

#define	CAN_F4R1_FB19_Pos (19U)

#define	CAN_F4R1_FB19_Msk (0x1UL << CAN_F4R1_FB19_Pos)

#define	CAN_F4R1_FB19 CAN_F4R1_FB19_Msk

#define	CAN_F4R1_FB20_Pos (20U)

#define	CAN_F4R1_FB20_Msk (0x1UL << CAN_F4R1_FB20_Pos)

#define	CAN_F4R1_FB20 CAN_F4R1_FB20_Msk

#define	CAN_F4R1_FB21_Pos (21U)

#define	CAN_F4R1_FB21_Msk (0x1UL << CAN_F4R1_FB21_Pos)

#define	CAN_F4R1_FB21 CAN_F4R1_FB21_Msk

#define	CAN_F4R1_FB22_Pos (22U)

#define	CAN_F4R1_FB22_Msk (0x1UL << CAN_F4R1_FB22_Pos)

#define	CAN_F4R1_FB22 CAN_F4R1_FB22_Msk

#define	CAN_F4R1_FB23_Pos (23U)

#define	CAN_F4R1_FB23_Msk (0x1UL << CAN_F4R1_FB23_Pos)

#define	CAN_F4R1_FB23 CAN_F4R1_FB23_Msk

#define	CAN_F4R1_FB24_Pos (24U)

#define	CAN_F4R1_FB24_Msk (0x1UL << CAN_F4R1_FB24_Pos)

#define	CAN_F4R1_FB24 CAN_F4R1_FB24_Msk

#define	CAN_F4R1_FB25_Pos (25U)

#define	CAN_F4R1_FB25_Msk (0x1UL << CAN_F4R1_FB25_Pos)

#define	CAN_F4R1_FB25 CAN_F4R1_FB25_Msk

#define	CAN_F4R1_FB26_Pos (26U)

#define	CAN_F4R1_FB26_Msk (0x1UL << CAN_F4R1_FB26_Pos)

#define	CAN_F4R1_FB26 CAN_F4R1_FB26_Msk

#define	CAN_F4R1_FB27_Pos (27U)

#define	CAN_F4R1_FB27_Msk (0x1UL << CAN_F4R1_FB27_Pos)

#define	CAN_F4R1_FB27 CAN_F4R1_FB27_Msk

#define	CAN_F4R1_FB28_Pos (28U)

#define	CAN_F4R1_FB28_Msk (0x1UL << CAN_F4R1_FB28_Pos)

#define	CAN_F4R1_FB28 CAN_F4R1_FB28_Msk

#define	CAN_F4R1_FB29_Pos (29U)

#define	CAN_F4R1_FB29_Msk (0x1UL << CAN_F4R1_FB29_Pos)

#define	CAN_F4R1_FB29 CAN_F4R1_FB29_Msk

#define	CAN_F4R1_FB30_Pos (30U)

#define	CAN_F4R1_FB30_Msk (0x1UL << CAN_F4R1_FB30_Pos)

#define	CAN_F4R1_FB30 CAN_F4R1_FB30_Msk

#define	CAN_F4R1_FB31_Pos (31U)

#define	CAN_F4R1_FB31_Msk (0x1UL << CAN_F4R1_FB31_Pos)

#define	CAN_F4R1_FB31 CAN_F4R1_FB31_Msk

#define	CAN_F5R1_FB0_Pos (0U)

#define	CAN_F5R1_FB0_Msk (0x1UL << CAN_F5R1_FB0_Pos)

#define	CAN_F5R1_FB0 CAN_F5R1_FB0_Msk

#define	CAN_F5R1_FB1_Pos (1U)

#define	CAN_F5R1_FB1_Msk (0x1UL << CAN_F5R1_FB1_Pos)

#define	CAN_F5R1_FB1 CAN_F5R1_FB1_Msk

#define	CAN_F5R1_FB2_Pos (2U)

#define	CAN_F5R1_FB2_Msk (0x1UL << CAN_F5R1_FB2_Pos)

#define	CAN_F5R1_FB2 CAN_F5R1_FB2_Msk

#define	CAN_F5R1_FB3_Pos (3U)

#define	CAN_F5R1_FB3_Msk (0x1UL << CAN_F5R1_FB3_Pos)

#define	CAN_F5R1_FB3 CAN_F5R1_FB3_Msk

#define	CAN_F5R1_FB4_Pos (4U)

#define	CAN_F5R1_FB4_Msk (0x1UL << CAN_F5R1_FB4_Pos)

#define	CAN_F5R1_FB4 CAN_F5R1_FB4_Msk

#define	CAN_F5R1_FB5_Pos (5U)

#define	CAN_F5R1_FB5_Msk (0x1UL << CAN_F5R1_FB5_Pos)

#define	CAN_F5R1_FB5 CAN_F5R1_FB5_Msk

#define	CAN_F5R1_FB6_Pos (6U)

#define	CAN_F5R1_FB6_Msk (0x1UL << CAN_F5R1_FB6_Pos)

#define	CAN_F5R1_FB6 CAN_F5R1_FB6_Msk

#define	CAN_F5R1_FB7_Pos (7U)

#define	CAN_F5R1_FB7_Msk (0x1UL << CAN_F5R1_FB7_Pos)

#define	CAN_F5R1_FB7 CAN_F5R1_FB7_Msk

#define	CAN_F5R1_FB8_Pos (8U)

#define	CAN_F5R1_FB8_Msk (0x1UL << CAN_F5R1_FB8_Pos)

#define	CAN_F5R1_FB8 CAN_F5R1_FB8_Msk

#define	CAN_F5R1_FB9_Pos (9U)

#define	CAN_F5R1_FB9_Msk (0x1UL << CAN_F5R1_FB9_Pos)

#define	CAN_F5R1_FB9 CAN_F5R1_FB9_Msk

#define	CAN_F5R1_FB10_Pos (10U)

#define	CAN_F5R1_FB10_Msk (0x1UL << CAN_F5R1_FB10_Pos)

#define	CAN_F5R1_FB10 CAN_F5R1_FB10_Msk

#define	CAN_F5R1_FB11_Pos (11U)

#define	CAN_F5R1_FB11_Msk (0x1UL << CAN_F5R1_FB11_Pos)

#define	CAN_F5R1_FB11 CAN_F5R1_FB11_Msk

#define	CAN_F5R1_FB12_Pos (12U)

#define	CAN_F5R1_FB12_Msk (0x1UL << CAN_F5R1_FB12_Pos)

#define	CAN_F5R1_FB12 CAN_F5R1_FB12_Msk

#define	CAN_F5R1_FB13_Pos (13U)

#define	CAN_F5R1_FB13_Msk (0x1UL << CAN_F5R1_FB13_Pos)

#define	CAN_F5R1_FB13 CAN_F5R1_FB13_Msk

#define	CAN_F5R1_FB14_Pos (14U)

#define	CAN_F5R1_FB14_Msk (0x1UL << CAN_F5R1_FB14_Pos)

#define	CAN_F5R1_FB14 CAN_F5R1_FB14_Msk

#define	CAN_F5R1_FB15_Pos (15U)

#define	CAN_F5R1_FB15_Msk (0x1UL << CAN_F5R1_FB15_Pos)

#define	CAN_F5R1_FB15 CAN_F5R1_FB15_Msk

#define	CAN_F5R1_FB16_Pos (16U)

#define	CAN_F5R1_FB16_Msk (0x1UL << CAN_F5R1_FB16_Pos)

#define	CAN_F5R1_FB16 CAN_F5R1_FB16_Msk

#define	CAN_F5R1_FB17_Pos (17U)

#define	CAN_F5R1_FB17_Msk (0x1UL << CAN_F5R1_FB17_Pos)

#define	CAN_F5R1_FB17 CAN_F5R1_FB17_Msk

#define	CAN_F5R1_FB18_Pos (18U)

#define	CAN_F5R1_FB18_Msk (0x1UL << CAN_F5R1_FB18_Pos)

#define	CAN_F5R1_FB18 CAN_F5R1_FB18_Msk

#define	CAN_F5R1_FB19_Pos (19U)

#define	CAN_F5R1_FB19_Msk (0x1UL << CAN_F5R1_FB19_Pos)

#define	CAN_F5R1_FB19 CAN_F5R1_FB19_Msk

#define	CAN_F5R1_FB20_Pos (20U)

#define	CAN_F5R1_FB20_Msk (0x1UL << CAN_F5R1_FB20_Pos)

#define	CAN_F5R1_FB20 CAN_F5R1_FB20_Msk

#define	CAN_F5R1_FB21_Pos (21U)

#define	CAN_F5R1_FB21_Msk (0x1UL << CAN_F5R1_FB21_Pos)

#define	CAN_F5R1_FB21 CAN_F5R1_FB21_Msk

#define	CAN_F5R1_FB22_Pos (22U)

#define	CAN_F5R1_FB22_Msk (0x1UL << CAN_F5R1_FB22_Pos)

#define	CAN_F5R1_FB22 CAN_F5R1_FB22_Msk

#define	CAN_F5R1_FB23_Pos (23U)

#define	CAN_F5R1_FB23_Msk (0x1UL << CAN_F5R1_FB23_Pos)

#define	CAN_F5R1_FB23 CAN_F5R1_FB23_Msk

#define	CAN_F5R1_FB24_Pos (24U)

#define	CAN_F5R1_FB24_Msk (0x1UL << CAN_F5R1_FB24_Pos)

#define	CAN_F5R1_FB24 CAN_F5R1_FB24_Msk

#define	CAN_F5R1_FB25_Pos (25U)

#define	CAN_F5R1_FB25_Msk (0x1UL << CAN_F5R1_FB25_Pos)

#define	CAN_F5R1_FB25 CAN_F5R1_FB25_Msk

#define	CAN_F5R1_FB26_Pos (26U)

#define	CAN_F5R1_FB26_Msk (0x1UL << CAN_F5R1_FB26_Pos)

#define	CAN_F5R1_FB26 CAN_F5R1_FB26_Msk

#define	CAN_F5R1_FB27_Pos (27U)

#define	CAN_F5R1_FB27_Msk (0x1UL << CAN_F5R1_FB27_Pos)

#define	CAN_F5R1_FB27 CAN_F5R1_FB27_Msk

#define	CAN_F5R1_FB28_Pos (28U)

#define	CAN_F5R1_FB28_Msk (0x1UL << CAN_F5R1_FB28_Pos)

#define	CAN_F5R1_FB28 CAN_F5R1_FB28_Msk

#define	CAN_F5R1_FB29_Pos (29U)

#define	CAN_F5R1_FB29_Msk (0x1UL << CAN_F5R1_FB29_Pos)

#define	CAN_F5R1_FB29 CAN_F5R1_FB29_Msk

#define	CAN_F5R1_FB30_Pos (30U)

#define	CAN_F5R1_FB30_Msk (0x1UL << CAN_F5R1_FB30_Pos)

#define	CAN_F5R1_FB30 CAN_F5R1_FB30_Msk

#define	CAN_F5R1_FB31_Pos (31U)

#define	CAN_F5R1_FB31_Msk (0x1UL << CAN_F5R1_FB31_Pos)

#define	CAN_F5R1_FB31 CAN_F5R1_FB31_Msk

#define	CAN_F6R1_FB0_Pos (0U)

#define	CAN_F6R1_FB0_Msk (0x1UL << CAN_F6R1_FB0_Pos)

#define	CAN_F6R1_FB0 CAN_F6R1_FB0_Msk

#define	CAN_F6R1_FB1_Pos (1U)

#define	CAN_F6R1_FB1_Msk (0x1UL << CAN_F6R1_FB1_Pos)

#define	CAN_F6R1_FB1 CAN_F6R1_FB1_Msk

#define	CAN_F6R1_FB2_Pos (2U)

#define	CAN_F6R1_FB2_Msk (0x1UL << CAN_F6R1_FB2_Pos)

#define	CAN_F6R1_FB2 CAN_F6R1_FB2_Msk

#define	CAN_F6R1_FB3_Pos (3U)

#define	CAN_F6R1_FB3_Msk (0x1UL << CAN_F6R1_FB3_Pos)

#define	CAN_F6R1_FB3 CAN_F6R1_FB3_Msk

#define	CAN_F6R1_FB4_Pos (4U)

#define	CAN_F6R1_FB4_Msk (0x1UL << CAN_F6R1_FB4_Pos)

#define	CAN_F6R1_FB4 CAN_F6R1_FB4_Msk

#define	CAN_F6R1_FB5_Pos (5U)

#define	CAN_F6R1_FB5_Msk (0x1UL << CAN_F6R1_FB5_Pos)

#define	CAN_F6R1_FB5 CAN_F6R1_FB5_Msk

#define	CAN_F6R1_FB6_Pos (6U)

#define	CAN_F6R1_FB6_Msk (0x1UL << CAN_F6R1_FB6_Pos)

#define	CAN_F6R1_FB6 CAN_F6R1_FB6_Msk

#define	CAN_F6R1_FB7_Pos (7U)

#define	CAN_F6R1_FB7_Msk (0x1UL << CAN_F6R1_FB7_Pos)

#define	CAN_F6R1_FB7 CAN_F6R1_FB7_Msk

#define	CAN_F6R1_FB8_Pos (8U)

#define	CAN_F6R1_FB8_Msk (0x1UL << CAN_F6R1_FB8_Pos)

#define	CAN_F6R1_FB8 CAN_F6R1_FB8_Msk

#define	CAN_F6R1_FB9_Pos (9U)

#define	CAN_F6R1_FB9_Msk (0x1UL << CAN_F6R1_FB9_Pos)

#define	CAN_F6R1_FB9 CAN_F6R1_FB9_Msk

#define	CAN_F6R1_FB10_Pos (10U)

#define	CAN_F6R1_FB10_Msk (0x1UL << CAN_F6R1_FB10_Pos)

#define	CAN_F6R1_FB10 CAN_F6R1_FB10_Msk

#define	CAN_F6R1_FB11_Pos (11U)

#define	CAN_F6R1_FB11_Msk (0x1UL << CAN_F6R1_FB11_Pos)

#define	CAN_F6R1_FB11 CAN_F6R1_FB11_Msk

#define	CAN_F6R1_FB12_Pos (12U)

#define	CAN_F6R1_FB12_Msk (0x1UL << CAN_F6R1_FB12_Pos)

#define	CAN_F6R1_FB12 CAN_F6R1_FB12_Msk

#define	CAN_F6R1_FB13_Pos (13U)

#define	CAN_F6R1_FB13_Msk (0x1UL << CAN_F6R1_FB13_Pos)

#define	CAN_F6R1_FB13 CAN_F6R1_FB13_Msk

#define	CAN_F6R1_FB14_Pos (14U)

#define	CAN_F6R1_FB14_Msk (0x1UL << CAN_F6R1_FB14_Pos)

#define	CAN_F6R1_FB14 CAN_F6R1_FB14_Msk

#define	CAN_F6R1_FB15_Pos (15U)

#define	CAN_F6R1_FB15_Msk (0x1UL << CAN_F6R1_FB15_Pos)

#define	CAN_F6R1_FB15 CAN_F6R1_FB15_Msk

#define	CAN_F6R1_FB16_Pos (16U)

#define	CAN_F6R1_FB16_Msk (0x1UL << CAN_F6R1_FB16_Pos)

#define	CAN_F6R1_FB16 CAN_F6R1_FB16_Msk

#define	CAN_F6R1_FB17_Pos (17U)

#define	CAN_F6R1_FB17_Msk (0x1UL << CAN_F6R1_FB17_Pos)

#define	CAN_F6R1_FB17 CAN_F6R1_FB17_Msk

#define	CAN_F6R1_FB18_Pos (18U)

#define	CAN_F6R1_FB18_Msk (0x1UL << CAN_F6R1_FB18_Pos)

#define	CAN_F6R1_FB18 CAN_F6R1_FB18_Msk

#define	CAN_F6R1_FB19_Pos (19U)

#define	CAN_F6R1_FB19_Msk (0x1UL << CAN_F6R1_FB19_Pos)

#define	CAN_F6R1_FB19 CAN_F6R1_FB19_Msk

#define	CAN_F6R1_FB20_Pos (20U)

#define	CAN_F6R1_FB20_Msk (0x1UL << CAN_F6R1_FB20_Pos)

#define	CAN_F6R1_FB20 CAN_F6R1_FB20_Msk

#define	CAN_F6R1_FB21_Pos (21U)

#define	CAN_F6R1_FB21_Msk (0x1UL << CAN_F6R1_FB21_Pos)

#define	CAN_F6R1_FB21 CAN_F6R1_FB21_Msk

#define	CAN_F6R1_FB22_Pos (22U)

#define	CAN_F6R1_FB22_Msk (0x1UL << CAN_F6R1_FB22_Pos)

#define	CAN_F6R1_FB22 CAN_F6R1_FB22_Msk

#define	CAN_F6R1_FB23_Pos (23U)

#define	CAN_F6R1_FB23_Msk (0x1UL << CAN_F6R1_FB23_Pos)

#define	CAN_F6R1_FB23 CAN_F6R1_FB23_Msk

#define	CAN_F6R1_FB24_Pos (24U)

#define	CAN_F6R1_FB24_Msk (0x1UL << CAN_F6R1_FB24_Pos)

#define	CAN_F6R1_FB24 CAN_F6R1_FB24_Msk

#define	CAN_F6R1_FB25_Pos (25U)

#define	CAN_F6R1_FB25_Msk (0x1UL << CAN_F6R1_FB25_Pos)

#define	CAN_F6R1_FB25 CAN_F6R1_FB25_Msk

#define	CAN_F6R1_FB26_Pos (26U)

#define	CAN_F6R1_FB26_Msk (0x1UL << CAN_F6R1_FB26_Pos)

#define	CAN_F6R1_FB26 CAN_F6R1_FB26_Msk

#define	CAN_F6R1_FB27_Pos (27U)

#define	CAN_F6R1_FB27_Msk (0x1UL << CAN_F6R1_FB27_Pos)

#define	CAN_F6R1_FB27 CAN_F6R1_FB27_Msk

#define	CAN_F6R1_FB28_Pos (28U)

#define	CAN_F6R1_FB28_Msk (0x1UL << CAN_F6R1_FB28_Pos)

#define	CAN_F6R1_FB28 CAN_F6R1_FB28_Msk

#define	CAN_F6R1_FB29_Pos (29U)

#define	CAN_F6R1_FB29_Msk (0x1UL << CAN_F6R1_FB29_Pos)

#define	CAN_F6R1_FB29 CAN_F6R1_FB29_Msk

#define	CAN_F6R1_FB30_Pos (30U)

#define	CAN_F6R1_FB30_Msk (0x1UL << CAN_F6R1_FB30_Pos)

#define	CAN_F6R1_FB30 CAN_F6R1_FB30_Msk

#define	CAN_F6R1_FB31_Pos (31U)

#define	CAN_F6R1_FB31_Msk (0x1UL << CAN_F6R1_FB31_Pos)

#define	CAN_F6R1_FB31 CAN_F6R1_FB31_Msk

#define	CAN_F7R1_FB0_Pos (0U)

#define	CAN_F7R1_FB0_Msk (0x1UL << CAN_F7R1_FB0_Pos)

#define	CAN_F7R1_FB0 CAN_F7R1_FB0_Msk

#define	CAN_F7R1_FB1_Pos (1U)

#define	CAN_F7R1_FB1_Msk (0x1UL << CAN_F7R1_FB1_Pos)

#define	CAN_F7R1_FB1 CAN_F7R1_FB1_Msk

#define	CAN_F7R1_FB2_Pos (2U)

#define	CAN_F7R1_FB2_Msk (0x1UL << CAN_F7R1_FB2_Pos)

#define	CAN_F7R1_FB2 CAN_F7R1_FB2_Msk

#define	CAN_F7R1_FB3_Pos (3U)

#define	CAN_F7R1_FB3_Msk (0x1UL << CAN_F7R1_FB3_Pos)

#define	CAN_F7R1_FB3 CAN_F7R1_FB3_Msk

#define	CAN_F7R1_FB4_Pos (4U)

#define	CAN_F7R1_FB4_Msk (0x1UL << CAN_F7R1_FB4_Pos)

#define	CAN_F7R1_FB4 CAN_F7R1_FB4_Msk

#define	CAN_F7R1_FB5_Pos (5U)

#define	CAN_F7R1_FB5_Msk (0x1UL << CAN_F7R1_FB5_Pos)

#define	CAN_F7R1_FB5 CAN_F7R1_FB5_Msk

#define	CAN_F7R1_FB6_Pos (6U)

#define	CAN_F7R1_FB6_Msk (0x1UL << CAN_F7R1_FB6_Pos)

#define	CAN_F7R1_FB6 CAN_F7R1_FB6_Msk

#define	CAN_F7R1_FB7_Pos (7U)

#define	CAN_F7R1_FB7_Msk (0x1UL << CAN_F7R1_FB7_Pos)

#define	CAN_F7R1_FB7 CAN_F7R1_FB7_Msk

#define	CAN_F7R1_FB8_Pos (8U)

#define	CAN_F7R1_FB8_Msk (0x1UL << CAN_F7R1_FB8_Pos)

#define	CAN_F7R1_FB8 CAN_F7R1_FB8_Msk

#define	CAN_F7R1_FB9_Pos (9U)

#define	CAN_F7R1_FB9_Msk (0x1UL << CAN_F7R1_FB9_Pos)

#define	CAN_F7R1_FB9 CAN_F7R1_FB9_Msk

#define	CAN_F7R1_FB10_Pos (10U)

#define	CAN_F7R1_FB10_Msk (0x1UL << CAN_F7R1_FB10_Pos)

#define	CAN_F7R1_FB10 CAN_F7R1_FB10_Msk

#define	CAN_F7R1_FB11_Pos (11U)

#define	CAN_F7R1_FB11_Msk (0x1UL << CAN_F7R1_FB11_Pos)

#define	CAN_F7R1_FB11 CAN_F7R1_FB11_Msk

#define	CAN_F7R1_FB12_Pos (12U)

#define	CAN_F7R1_FB12_Msk (0x1UL << CAN_F7R1_FB12_Pos)

#define	CAN_F7R1_FB12 CAN_F7R1_FB12_Msk

#define	CAN_F7R1_FB13_Pos (13U)

#define	CAN_F7R1_FB13_Msk (0x1UL << CAN_F7R1_FB13_Pos)

#define	CAN_F7R1_FB13 CAN_F7R1_FB13_Msk

#define	CAN_F7R1_FB14_Pos (14U)

#define	CAN_F7R1_FB14_Msk (0x1UL << CAN_F7R1_FB14_Pos)

#define	CAN_F7R1_FB14 CAN_F7R1_FB14_Msk

#define	CAN_F7R1_FB15_Pos (15U)

#define	CAN_F7R1_FB15_Msk (0x1UL << CAN_F7R1_FB15_Pos)

#define	CAN_F7R1_FB15 CAN_F7R1_FB15_Msk

#define	CAN_F7R1_FB16_Pos (16U)

#define	CAN_F7R1_FB16_Msk (0x1UL << CAN_F7R1_FB16_Pos)

#define	CAN_F7R1_FB16 CAN_F7R1_FB16_Msk

#define	CAN_F7R1_FB17_Pos (17U)

#define	CAN_F7R1_FB17_Msk (0x1UL << CAN_F7R1_FB17_Pos)

#define	CAN_F7R1_FB17 CAN_F7R1_FB17_Msk

#define	CAN_F7R1_FB18_Pos (18U)

#define	CAN_F7R1_FB18_Msk (0x1UL << CAN_F7R1_FB18_Pos)

#define	CAN_F7R1_FB18 CAN_F7R1_FB18_Msk

#define	CAN_F7R1_FB19_Pos (19U)

#define	CAN_F7R1_FB19_Msk (0x1UL << CAN_F7R1_FB19_Pos)

#define	CAN_F7R1_FB19 CAN_F7R1_FB19_Msk

#define	CAN_F7R1_FB20_Pos (20U)

#define	CAN_F7R1_FB20_Msk (0x1UL << CAN_F7R1_FB20_Pos)

#define	CAN_F7R1_FB20 CAN_F7R1_FB20_Msk

#define	CAN_F7R1_FB21_Pos (21U)

#define	CAN_F7R1_FB21_Msk (0x1UL << CAN_F7R1_FB21_Pos)

#define	CAN_F7R1_FB21 CAN_F7R1_FB21_Msk

#define	CAN_F7R1_FB22_Pos (22U)

#define	CAN_F7R1_FB22_Msk (0x1UL << CAN_F7R1_FB22_Pos)

#define	CAN_F7R1_FB22 CAN_F7R1_FB22_Msk

#define	CAN_F7R1_FB23_Pos (23U)

#define	CAN_F7R1_FB23_Msk (0x1UL << CAN_F7R1_FB23_Pos)

#define	CAN_F7R1_FB23 CAN_F7R1_FB23_Msk

#define	CAN_F7R1_FB24_Pos (24U)

#define	CAN_F7R1_FB24_Msk (0x1UL << CAN_F7R1_FB24_Pos)

#define	CAN_F7R1_FB24 CAN_F7R1_FB24_Msk

#define	CAN_F7R1_FB25_Pos (25U)

#define	CAN_F7R1_FB25_Msk (0x1UL << CAN_F7R1_FB25_Pos)

#define	CAN_F7R1_FB25 CAN_F7R1_FB25_Msk

#define	CAN_F7R1_FB26_Pos (26U)

#define	CAN_F7R1_FB26_Msk (0x1UL << CAN_F7R1_FB26_Pos)

#define	CAN_F7R1_FB26 CAN_F7R1_FB26_Msk

#define	CAN_F7R1_FB27_Pos (27U)

#define	CAN_F7R1_FB27_Msk (0x1UL << CAN_F7R1_FB27_Pos)

#define	CAN_F7R1_FB27 CAN_F7R1_FB27_Msk

#define	CAN_F7R1_FB28_Pos (28U)

#define	CAN_F7R1_FB28_Msk (0x1UL << CAN_F7R1_FB28_Pos)

#define	CAN_F7R1_FB28 CAN_F7R1_FB28_Msk

#define	CAN_F7R1_FB29_Pos (29U)

#define	CAN_F7R1_FB29_Msk (0x1UL << CAN_F7R1_FB29_Pos)

#define	CAN_F7R1_FB29 CAN_F7R1_FB29_Msk

#define	CAN_F7R1_FB30_Pos (30U)

#define	CAN_F7R1_FB30_Msk (0x1UL << CAN_F7R1_FB30_Pos)

#define	CAN_F7R1_FB30 CAN_F7R1_FB30_Msk

#define	CAN_F7R1_FB31_Pos (31U)

#define	CAN_F7R1_FB31_Msk (0x1UL << CAN_F7R1_FB31_Pos)

#define	CAN_F7R1_FB31 CAN_F7R1_FB31_Msk

#define	CAN_F8R1_FB0_Pos (0U)

#define	CAN_F8R1_FB0_Msk (0x1UL << CAN_F8R1_FB0_Pos)

#define	CAN_F8R1_FB0 CAN_F8R1_FB0_Msk

#define	CAN_F8R1_FB1_Pos (1U)

#define	CAN_F8R1_FB1_Msk (0x1UL << CAN_F8R1_FB1_Pos)

#define	CAN_F8R1_FB1 CAN_F8R1_FB1_Msk

#define	CAN_F8R1_FB2_Pos (2U)

#define	CAN_F8R1_FB2_Msk (0x1UL << CAN_F8R1_FB2_Pos)

#define	CAN_F8R1_FB2 CAN_F8R1_FB2_Msk

#define	CAN_F8R1_FB3_Pos (3U)

#define	CAN_F8R1_FB3_Msk (0x1UL << CAN_F8R1_FB3_Pos)

#define	CAN_F8R1_FB3 CAN_F8R1_FB3_Msk

#define	CAN_F8R1_FB4_Pos (4U)

#define	CAN_F8R1_FB4_Msk (0x1UL << CAN_F8R1_FB4_Pos)

#define	CAN_F8R1_FB4 CAN_F8R1_FB4_Msk

#define	CAN_F8R1_FB5_Pos (5U)

#define	CAN_F8R1_FB5_Msk (0x1UL << CAN_F8R1_FB5_Pos)

#define	CAN_F8R1_FB5 CAN_F8R1_FB5_Msk

#define	CAN_F8R1_FB6_Pos (6U)

#define	CAN_F8R1_FB6_Msk (0x1UL << CAN_F8R1_FB6_Pos)

#define	CAN_F8R1_FB6 CAN_F8R1_FB6_Msk

#define	CAN_F8R1_FB7_Pos (7U)

#define	CAN_F8R1_FB7_Msk (0x1UL << CAN_F8R1_FB7_Pos)

#define	CAN_F8R1_FB7 CAN_F8R1_FB7_Msk

#define	CAN_F8R1_FB8_Pos (8U)

#define	CAN_F8R1_FB8_Msk (0x1UL << CAN_F8R1_FB8_Pos)

#define	CAN_F8R1_FB8 CAN_F8R1_FB8_Msk

#define	CAN_F8R1_FB9_Pos (9U)

#define	CAN_F8R1_FB9_Msk (0x1UL << CAN_F8R1_FB9_Pos)

#define	CAN_F8R1_FB9 CAN_F8R1_FB9_Msk

#define	CAN_F8R1_FB10_Pos (10U)

#define	CAN_F8R1_FB10_Msk (0x1UL << CAN_F8R1_FB10_Pos)

#define	CAN_F8R1_FB10 CAN_F8R1_FB10_Msk

#define	CAN_F8R1_FB11_Pos (11U)

#define	CAN_F8R1_FB11_Msk (0x1UL << CAN_F8R1_FB11_Pos)

#define	CAN_F8R1_FB11 CAN_F8R1_FB11_Msk

#define	CAN_F8R1_FB12_Pos (12U)

#define	CAN_F8R1_FB12_Msk (0x1UL << CAN_F8R1_FB12_Pos)

#define	CAN_F8R1_FB12 CAN_F8R1_FB12_Msk

#define	CAN_F8R1_FB13_Pos (13U)

#define	CAN_F8R1_FB13_Msk (0x1UL << CAN_F8R1_FB13_Pos)

#define	CAN_F8R1_FB13 CAN_F8R1_FB13_Msk

#define	CAN_F8R1_FB14_Pos (14U)

#define	CAN_F8R1_FB14_Msk (0x1UL << CAN_F8R1_FB14_Pos)

#define	CAN_F8R1_FB14 CAN_F8R1_FB14_Msk

#define	CAN_F8R1_FB15_Pos (15U)

#define	CAN_F8R1_FB15_Msk (0x1UL << CAN_F8R1_FB15_Pos)

#define	CAN_F8R1_FB15 CAN_F8R1_FB15_Msk

#define	CAN_F8R1_FB16_Pos (16U)

#define	CAN_F8R1_FB16_Msk (0x1UL << CAN_F8R1_FB16_Pos)

#define	CAN_F8R1_FB16 CAN_F8R1_FB16_Msk

#define	CAN_F8R1_FB17_Pos (17U)

#define	CAN_F8R1_FB17_Msk (0x1UL << CAN_F8R1_FB17_Pos)

#define	CAN_F8R1_FB17 CAN_F8R1_FB17_Msk

#define	CAN_F8R1_FB18_Pos (18U)

#define	CAN_F8R1_FB18_Msk (0x1UL << CAN_F8R1_FB18_Pos)

#define	CAN_F8R1_FB18 CAN_F8R1_FB18_Msk

#define	CAN_F8R1_FB19_Pos (19U)

#define	CAN_F8R1_FB19_Msk (0x1UL << CAN_F8R1_FB19_Pos)

#define	CAN_F8R1_FB19 CAN_F8R1_FB19_Msk

#define	CAN_F8R1_FB20_Pos (20U)

#define	CAN_F8R1_FB20_Msk (0x1UL << CAN_F8R1_FB20_Pos)

#define	CAN_F8R1_FB20 CAN_F8R1_FB20_Msk

#define	CAN_F8R1_FB21_Pos (21U)

#define	CAN_F8R1_FB21_Msk (0x1UL << CAN_F8R1_FB21_Pos)

#define	CAN_F8R1_FB21 CAN_F8R1_FB21_Msk

#define	CAN_F8R1_FB22_Pos (22U)

#define	CAN_F8R1_FB22_Msk (0x1UL << CAN_F8R1_FB22_Pos)

#define	CAN_F8R1_FB22 CAN_F8R1_FB22_Msk

#define	CAN_F8R1_FB23_Pos (23U)

#define	CAN_F8R1_FB23_Msk (0x1UL << CAN_F8R1_FB23_Pos)

#define	CAN_F8R1_FB23 CAN_F8R1_FB23_Msk

#define	CAN_F8R1_FB24_Pos (24U)

#define	CAN_F8R1_FB24_Msk (0x1UL << CAN_F8R1_FB24_Pos)

#define	CAN_F8R1_FB24 CAN_F8R1_FB24_Msk

#define	CAN_F8R1_FB25_Pos (25U)

#define	CAN_F8R1_FB25_Msk (0x1UL << CAN_F8R1_FB25_Pos)

#define	CAN_F8R1_FB25 CAN_F8R1_FB25_Msk

#define	CAN_F8R1_FB26_Pos (26U)

#define	CAN_F8R1_FB26_Msk (0x1UL << CAN_F8R1_FB26_Pos)

#define	CAN_F8R1_FB26 CAN_F8R1_FB26_Msk

#define	CAN_F8R1_FB27_Pos (27U)

#define	CAN_F8R1_FB27_Msk (0x1UL << CAN_F8R1_FB27_Pos)

#define	CAN_F8R1_FB27 CAN_F8R1_FB27_Msk

#define	CAN_F8R1_FB28_Pos (28U)

#define	CAN_F8R1_FB28_Msk (0x1UL << CAN_F8R1_FB28_Pos)

#define	CAN_F8R1_FB28 CAN_F8R1_FB28_Msk

#define	CAN_F8R1_FB29_Pos (29U)

#define	CAN_F8R1_FB29_Msk (0x1UL << CAN_F8R1_FB29_Pos)

#define	CAN_F8R1_FB29 CAN_F8R1_FB29_Msk

#define	CAN_F8R1_FB30_Pos (30U)

#define	CAN_F8R1_FB30_Msk (0x1UL << CAN_F8R1_FB30_Pos)

#define	CAN_F8R1_FB30 CAN_F8R1_FB30_Msk

#define	CAN_F8R1_FB31_Pos (31U)

#define	CAN_F8R1_FB31_Msk (0x1UL << CAN_F8R1_FB31_Pos)

#define	CAN_F8R1_FB31 CAN_F8R1_FB31_Msk

#define	CAN_F9R1_FB0_Pos (0U)

#define	CAN_F9R1_FB0_Msk (0x1UL << CAN_F9R1_FB0_Pos)

#define	CAN_F9R1_FB0 CAN_F9R1_FB0_Msk

#define	CAN_F9R1_FB1_Pos (1U)

#define	CAN_F9R1_FB1_Msk (0x1UL << CAN_F9R1_FB1_Pos)

#define	CAN_F9R1_FB1 CAN_F9R1_FB1_Msk

#define	CAN_F9R1_FB2_Pos (2U)

#define	CAN_F9R1_FB2_Msk (0x1UL << CAN_F9R1_FB2_Pos)

#define	CAN_F9R1_FB2 CAN_F9R1_FB2_Msk

#define	CAN_F9R1_FB3_Pos (3U)

#define	CAN_F9R1_FB3_Msk (0x1UL << CAN_F9R1_FB3_Pos)

#define	CAN_F9R1_FB3 CAN_F9R1_FB3_Msk

#define	CAN_F9R1_FB4_Pos (4U)

#define	CAN_F9R1_FB4_Msk (0x1UL << CAN_F9R1_FB4_Pos)

#define	CAN_F9R1_FB4 CAN_F9R1_FB4_Msk

#define	CAN_F9R1_FB5_Pos (5U)

#define	CAN_F9R1_FB5_Msk (0x1UL << CAN_F9R1_FB5_Pos)

#define	CAN_F9R1_FB5 CAN_F9R1_FB5_Msk

#define	CAN_F9R1_FB6_Pos (6U)

#define	CAN_F9R1_FB6_Msk (0x1UL << CAN_F9R1_FB6_Pos)

#define	CAN_F9R1_FB6 CAN_F9R1_FB6_Msk

#define	CAN_F9R1_FB7_Pos (7U)

#define	CAN_F9R1_FB7_Msk (0x1UL << CAN_F9R1_FB7_Pos)

#define	CAN_F9R1_FB7 CAN_F9R1_FB7_Msk

#define	CAN_F9R1_FB8_Pos (8U)

#define	CAN_F9R1_FB8_Msk (0x1UL << CAN_F9R1_FB8_Pos)

#define	CAN_F9R1_FB8 CAN_F9R1_FB8_Msk

#define	CAN_F9R1_FB9_Pos (9U)

#define	CAN_F9R1_FB9_Msk (0x1UL << CAN_F9R1_FB9_Pos)

#define	CAN_F9R1_FB9 CAN_F9R1_FB9_Msk

#define	CAN_F9R1_FB10_Pos (10U)

#define	CAN_F9R1_FB10_Msk (0x1UL << CAN_F9R1_FB10_Pos)

#define	CAN_F9R1_FB10 CAN_F9R1_FB10_Msk

#define	CAN_F9R1_FB11_Pos (11U)

#define	CAN_F9R1_FB11_Msk (0x1UL << CAN_F9R1_FB11_Pos)

#define	CAN_F9R1_FB11 CAN_F9R1_FB11_Msk

#define	CAN_F9R1_FB12_Pos (12U)

#define	CAN_F9R1_FB12_Msk (0x1UL << CAN_F9R1_FB12_Pos)

#define	CAN_F9R1_FB12 CAN_F9R1_FB12_Msk

#define	CAN_F9R1_FB13_Pos (13U)

#define	CAN_F9R1_FB13_Msk (0x1UL << CAN_F9R1_FB13_Pos)

#define	CAN_F9R1_FB13 CAN_F9R1_FB13_Msk

#define	CAN_F9R1_FB14_Pos (14U)

#define	CAN_F9R1_FB14_Msk (0x1UL << CAN_F9R1_FB14_Pos)

#define	CAN_F9R1_FB14 CAN_F9R1_FB14_Msk

#define	CAN_F9R1_FB15_Pos (15U)

#define	CAN_F9R1_FB15_Msk (0x1UL << CAN_F9R1_FB15_Pos)

#define	CAN_F9R1_FB15 CAN_F9R1_FB15_Msk

#define	CAN_F9R1_FB16_Pos (16U)

#define	CAN_F9R1_FB16_Msk (0x1UL << CAN_F9R1_FB16_Pos)

#define	CAN_F9R1_FB16 CAN_F9R1_FB16_Msk

#define	CAN_F9R1_FB17_Pos (17U)

#define	CAN_F9R1_FB17_Msk (0x1UL << CAN_F9R1_FB17_Pos)

#define	CAN_F9R1_FB17 CAN_F9R1_FB17_Msk

#define	CAN_F9R1_FB18_Pos (18U)

#define	CAN_F9R1_FB18_Msk (0x1UL << CAN_F9R1_FB18_Pos)

#define	CAN_F9R1_FB18 CAN_F9R1_FB18_Msk

#define	CAN_F9R1_FB19_Pos (19U)

#define	CAN_F9R1_FB19_Msk (0x1UL << CAN_F9R1_FB19_Pos)

#define	CAN_F9R1_FB19 CAN_F9R1_FB19_Msk

#define	CAN_F9R1_FB20_Pos (20U)

#define	CAN_F9R1_FB20_Msk (0x1UL << CAN_F9R1_FB20_Pos)

#define	CAN_F9R1_FB20 CAN_F9R1_FB20_Msk

#define	CAN_F9R1_FB21_Pos (21U)

#define	CAN_F9R1_FB21_Msk (0x1UL << CAN_F9R1_FB21_Pos)

#define	CAN_F9R1_FB21 CAN_F9R1_FB21_Msk

#define	CAN_F9R1_FB22_Pos (22U)

#define	CAN_F9R1_FB22_Msk (0x1UL << CAN_F9R1_FB22_Pos)

#define	CAN_F9R1_FB22 CAN_F9R1_FB22_Msk

#define	CAN_F9R1_FB23_Pos (23U)

#define	CAN_F9R1_FB23_Msk (0x1UL << CAN_F9R1_FB23_Pos)

#define	CAN_F9R1_FB23 CAN_F9R1_FB23_Msk

#define	CAN_F9R1_FB24_Pos (24U)

#define	CAN_F9R1_FB24_Msk (0x1UL << CAN_F9R1_FB24_Pos)

#define	CAN_F9R1_FB24 CAN_F9R1_FB24_Msk

#define	CAN_F9R1_FB25_Pos (25U)

#define	CAN_F9R1_FB25_Msk (0x1UL << CAN_F9R1_FB25_Pos)

#define	CAN_F9R1_FB25 CAN_F9R1_FB25_Msk

#define	CAN_F9R1_FB26_Pos (26U)

#define	CAN_F9R1_FB26_Msk (0x1UL << CAN_F9R1_FB26_Pos)

#define	CAN_F9R1_FB26 CAN_F9R1_FB26_Msk

#define	CAN_F9R1_FB27_Pos (27U)

#define	CAN_F9R1_FB27_Msk (0x1UL << CAN_F9R1_FB27_Pos)

#define	CAN_F9R1_FB27 CAN_F9R1_FB27_Msk

#define	CAN_F9R1_FB28_Pos (28U)

#define	CAN_F9R1_FB28_Msk (0x1UL << CAN_F9R1_FB28_Pos)

#define	CAN_F9R1_FB28 CAN_F9R1_FB28_Msk

#define	CAN_F9R1_FB29_Pos (29U)

#define	CAN_F9R1_FB29_Msk (0x1UL << CAN_F9R1_FB29_Pos)

#define	CAN_F9R1_FB29 CAN_F9R1_FB29_Msk

#define	CAN_F9R1_FB30_Pos (30U)

#define	CAN_F9R1_FB30_Msk (0x1UL << CAN_F9R1_FB30_Pos)

#define	CAN_F9R1_FB30 CAN_F9R1_FB30_Msk

#define	CAN_F9R1_FB31_Pos (31U)

#define	CAN_F9R1_FB31_Msk (0x1UL << CAN_F9R1_FB31_Pos)

#define	CAN_F9R1_FB31 CAN_F9R1_FB31_Msk

#define	CAN_F10R1_FB0_Pos (0U)

#define	CAN_F10R1_FB0_Msk (0x1UL << CAN_F10R1_FB0_Pos)

#define	CAN_F10R1_FB0 CAN_F10R1_FB0_Msk

#define	CAN_F10R1_FB1_Pos (1U)

#define	CAN_F10R1_FB1_Msk (0x1UL << CAN_F10R1_FB1_Pos)

#define	CAN_F10R1_FB1 CAN_F10R1_FB1_Msk

#define	CAN_F10R1_FB2_Pos (2U)

#define	CAN_F10R1_FB2_Msk (0x1UL << CAN_F10R1_FB2_Pos)

#define	CAN_F10R1_FB2 CAN_F10R1_FB2_Msk

#define	CAN_F10R1_FB3_Pos (3U)

#define	CAN_F10R1_FB3_Msk (0x1UL << CAN_F10R1_FB3_Pos)

#define	CAN_F10R1_FB3 CAN_F10R1_FB3_Msk

#define	CAN_F10R1_FB4_Pos (4U)

#define	CAN_F10R1_FB4_Msk (0x1UL << CAN_F10R1_FB4_Pos)

#define	CAN_F10R1_FB4 CAN_F10R1_FB4_Msk

#define	CAN_F10R1_FB5_Pos (5U)

#define	CAN_F10R1_FB5_Msk (0x1UL << CAN_F10R1_FB5_Pos)

#define	CAN_F10R1_FB5 CAN_F10R1_FB5_Msk

#define	CAN_F10R1_FB6_Pos (6U)

#define	CAN_F10R1_FB6_Msk (0x1UL << CAN_F10R1_FB6_Pos)

#define	CAN_F10R1_FB6 CAN_F10R1_FB6_Msk

#define	CAN_F10R1_FB7_Pos (7U)

#define	CAN_F10R1_FB7_Msk (0x1UL << CAN_F10R1_FB7_Pos)

#define	CAN_F10R1_FB7 CAN_F10R1_FB7_Msk

#define	CAN_F10R1_FB8_Pos (8U)

#define	CAN_F10R1_FB8_Msk (0x1UL << CAN_F10R1_FB8_Pos)

#define	CAN_F10R1_FB8 CAN_F10R1_FB8_Msk

#define	CAN_F10R1_FB9_Pos (9U)

#define	CAN_F10R1_FB9_Msk (0x1UL << CAN_F10R1_FB9_Pos)

#define	CAN_F10R1_FB9 CAN_F10R1_FB9_Msk

#define	CAN_F10R1_FB10_Pos (10U)

#define	CAN_F10R1_FB10_Msk (0x1UL << CAN_F10R1_FB10_Pos)

#define	CAN_F10R1_FB10 CAN_F10R1_FB10_Msk

#define	CAN_F10R1_FB11_Pos (11U)

#define	CAN_F10R1_FB11_Msk (0x1UL << CAN_F10R1_FB11_Pos)

#define	CAN_F10R1_FB11 CAN_F10R1_FB11_Msk

#define	CAN_F10R1_FB12_Pos (12U)

#define	CAN_F10R1_FB12_Msk (0x1UL << CAN_F10R1_FB12_Pos)

#define	CAN_F10R1_FB12 CAN_F10R1_FB12_Msk

#define	CAN_F10R1_FB13_Pos (13U)

#define	CAN_F10R1_FB13_Msk (0x1UL << CAN_F10R1_FB13_Pos)

#define	CAN_F10R1_FB13 CAN_F10R1_FB13_Msk

#define	CAN_F10R1_FB14_Pos (14U)

#define	CAN_F10R1_FB14_Msk (0x1UL << CAN_F10R1_FB14_Pos)

#define	CAN_F10R1_FB14 CAN_F10R1_FB14_Msk

#define	CAN_F10R1_FB15_Pos (15U)

#define	CAN_F10R1_FB15_Msk (0x1UL << CAN_F10R1_FB15_Pos)

#define	CAN_F10R1_FB15 CAN_F10R1_FB15_Msk

#define	CAN_F10R1_FB16_Pos (16U)

#define	CAN_F10R1_FB16_Msk (0x1UL << CAN_F10R1_FB16_Pos)

#define	CAN_F10R1_FB16 CAN_F10R1_FB16_Msk

#define	CAN_F10R1_FB17_Pos (17U)

#define	CAN_F10R1_FB17_Msk (0x1UL << CAN_F10R1_FB17_Pos)

#define	CAN_F10R1_FB17 CAN_F10R1_FB17_Msk

#define	CAN_F10R1_FB18_Pos (18U)

#define	CAN_F10R1_FB18_Msk (0x1UL << CAN_F10R1_FB18_Pos)

#define	CAN_F10R1_FB18 CAN_F10R1_FB18_Msk

#define	CAN_F10R1_FB19_Pos (19U)

#define	CAN_F10R1_FB19_Msk (0x1UL << CAN_F10R1_FB19_Pos)

#define	CAN_F10R1_FB19 CAN_F10R1_FB19_Msk

#define	CAN_F10R1_FB20_Pos (20U)

#define	CAN_F10R1_FB20_Msk (0x1UL << CAN_F10R1_FB20_Pos)

#define	CAN_F10R1_FB20 CAN_F10R1_FB20_Msk

#define	CAN_F10R1_FB21_Pos (21U)

#define	CAN_F10R1_FB21_Msk (0x1UL << CAN_F10R1_FB21_Pos)

#define	CAN_F10R1_FB21 CAN_F10R1_FB21_Msk

#define	CAN_F10R1_FB22_Pos (22U)

#define	CAN_F10R1_FB22_Msk (0x1UL << CAN_F10R1_FB22_Pos)

#define	CAN_F10R1_FB22 CAN_F10R1_FB22_Msk

#define	CAN_F10R1_FB23_Pos (23U)

#define	CAN_F10R1_FB23_Msk (0x1UL << CAN_F10R1_FB23_Pos)

#define	CAN_F10R1_FB23 CAN_F10R1_FB23_Msk

#define	CAN_F10R1_FB24_Pos (24U)

#define	CAN_F10R1_FB24_Msk (0x1UL << CAN_F10R1_FB24_Pos)

#define	CAN_F10R1_FB24 CAN_F10R1_FB24_Msk

#define	CAN_F10R1_FB25_Pos (25U)

#define	CAN_F10R1_FB25_Msk (0x1UL << CAN_F10R1_FB25_Pos)

#define	CAN_F10R1_FB25 CAN_F10R1_FB25_Msk

#define	CAN_F10R1_FB26_Pos (26U)

#define	CAN_F10R1_FB26_Msk (0x1UL << CAN_F10R1_FB26_Pos)

#define	CAN_F10R1_FB26 CAN_F10R1_FB26_Msk

#define	CAN_F10R1_FB27_Pos (27U)

#define	CAN_F10R1_FB27_Msk (0x1UL << CAN_F10R1_FB27_Pos)

#define	CAN_F10R1_FB27 CAN_F10R1_FB27_Msk

#define	CAN_F10R1_FB28_Pos (28U)

#define	CAN_F10R1_FB28_Msk (0x1UL << CAN_F10R1_FB28_Pos)

#define	CAN_F10R1_FB28 CAN_F10R1_FB28_Msk

#define	CAN_F10R1_FB29_Pos (29U)

#define	CAN_F10R1_FB29_Msk (0x1UL << CAN_F10R1_FB29_Pos)

#define	CAN_F10R1_FB29 CAN_F10R1_FB29_Msk

#define	CAN_F10R1_FB30_Pos (30U)

#define	CAN_F10R1_FB30_Msk (0x1UL << CAN_F10R1_FB30_Pos)

#define	CAN_F10R1_FB30 CAN_F10R1_FB30_Msk

#define	CAN_F10R1_FB31_Pos (31U)

#define	CAN_F10R1_FB31_Msk (0x1UL << CAN_F10R1_FB31_Pos)

#define	CAN_F10R1_FB31 CAN_F10R1_FB31_Msk

#define	CAN_F11R1_FB0_Pos (0U)

#define	CAN_F11R1_FB0_Msk (0x1UL << CAN_F11R1_FB0_Pos)

#define	CAN_F11R1_FB0 CAN_F11R1_FB0_Msk

#define	CAN_F11R1_FB1_Pos (1U)

#define	CAN_F11R1_FB1_Msk (0x1UL << CAN_F11R1_FB1_Pos)

#define	CAN_F11R1_FB1 CAN_F11R1_FB1_Msk

#define	CAN_F11R1_FB2_Pos (2U)

#define	CAN_F11R1_FB2_Msk (0x1UL << CAN_F11R1_FB2_Pos)

#define	CAN_F11R1_FB2 CAN_F11R1_FB2_Msk

#define	CAN_F11R1_FB3_Pos (3U)

#define	CAN_F11R1_FB3_Msk (0x1UL << CAN_F11R1_FB3_Pos)

#define	CAN_F11R1_FB3 CAN_F11R1_FB3_Msk

#define	CAN_F11R1_FB4_Pos (4U)

#define	CAN_F11R1_FB4_Msk (0x1UL << CAN_F11R1_FB4_Pos)

#define	CAN_F11R1_FB4 CAN_F11R1_FB4_Msk

#define	CAN_F11R1_FB5_Pos (5U)

#define	CAN_F11R1_FB5_Msk (0x1UL << CAN_F11R1_FB5_Pos)

#define	CAN_F11R1_FB5 CAN_F11R1_FB5_Msk

#define	CAN_F11R1_FB6_Pos (6U)

#define	CAN_F11R1_FB6_Msk (0x1UL << CAN_F11R1_FB6_Pos)

#define	CAN_F11R1_FB6 CAN_F11R1_FB6_Msk

#define	CAN_F11R1_FB7_Pos (7U)

#define	CAN_F11R1_FB7_Msk (0x1UL << CAN_F11R1_FB7_Pos)

#define	CAN_F11R1_FB7 CAN_F11R1_FB7_Msk

#define	CAN_F11R1_FB8_Pos (8U)

#define	CAN_F11R1_FB8_Msk (0x1UL << CAN_F11R1_FB8_Pos)

#define	CAN_F11R1_FB8 CAN_F11R1_FB8_Msk

#define	CAN_F11R1_FB9_Pos (9U)

#define	CAN_F11R1_FB9_Msk (0x1UL << CAN_F11R1_FB9_Pos)

#define	CAN_F11R1_FB9 CAN_F11R1_FB9_Msk

#define	CAN_F11R1_FB10_Pos (10U)

#define	CAN_F11R1_FB10_Msk (0x1UL << CAN_F11R1_FB10_Pos)

#define	CAN_F11R1_FB10 CAN_F11R1_FB10_Msk

#define	CAN_F11R1_FB11_Pos (11U)

#define	CAN_F11R1_FB11_Msk (0x1UL << CAN_F11R1_FB11_Pos)

#define	CAN_F11R1_FB11 CAN_F11R1_FB11_Msk

#define	CAN_F11R1_FB12_Pos (12U)

#define	CAN_F11R1_FB12_Msk (0x1UL << CAN_F11R1_FB12_Pos)

#define	CAN_F11R1_FB12 CAN_F11R1_FB12_Msk

#define	CAN_F11R1_FB13_Pos (13U)

#define	CAN_F11R1_FB13_Msk (0x1UL << CAN_F11R1_FB13_Pos)

#define	CAN_F11R1_FB13 CAN_F11R1_FB13_Msk

#define	CAN_F11R1_FB14_Pos (14U)

#define	CAN_F11R1_FB14_Msk (0x1UL << CAN_F11R1_FB14_Pos)

#define	CAN_F11R1_FB14 CAN_F11R1_FB14_Msk

#define	CAN_F11R1_FB15_Pos (15U)

#define	CAN_F11R1_FB15_Msk (0x1UL << CAN_F11R1_FB15_Pos)

#define	CAN_F11R1_FB15 CAN_F11R1_FB15_Msk

#define	CAN_F11R1_FB16_Pos (16U)

#define	CAN_F11R1_FB16_Msk (0x1UL << CAN_F11R1_FB16_Pos)

#define	CAN_F11R1_FB16 CAN_F11R1_FB16_Msk

#define	CAN_F11R1_FB17_Pos (17U)

#define	CAN_F11R1_FB17_Msk (0x1UL << CAN_F11R1_FB17_Pos)

#define	CAN_F11R1_FB17 CAN_F11R1_FB17_Msk

#define	CAN_F11R1_FB18_Pos (18U)

#define	CAN_F11R1_FB18_Msk (0x1UL << CAN_F11R1_FB18_Pos)

#define	CAN_F11R1_FB18 CAN_F11R1_FB18_Msk

#define	CAN_F11R1_FB19_Pos (19U)

#define	CAN_F11R1_FB19_Msk (0x1UL << CAN_F11R1_FB19_Pos)

#define	CAN_F11R1_FB19 CAN_F11R1_FB19_Msk

#define	CAN_F11R1_FB20_Pos (20U)

#define	CAN_F11R1_FB20_Msk (0x1UL << CAN_F11R1_FB20_Pos)

#define	CAN_F11R1_FB20 CAN_F11R1_FB20_Msk

#define	CAN_F11R1_FB21_Pos (21U)

#define	CAN_F11R1_FB21_Msk (0x1UL << CAN_F11R1_FB21_Pos)

#define	CAN_F11R1_FB21 CAN_F11R1_FB21_Msk

#define	CAN_F11R1_FB22_Pos (22U)

#define	CAN_F11R1_FB22_Msk (0x1UL << CAN_F11R1_FB22_Pos)

#define	CAN_F11R1_FB22 CAN_F11R1_FB22_Msk

#define	CAN_F11R1_FB23_Pos (23U)

#define	CAN_F11R1_FB23_Msk (0x1UL << CAN_F11R1_FB23_Pos)

#define	CAN_F11R1_FB23 CAN_F11R1_FB23_Msk

#define	CAN_F11R1_FB24_Pos (24U)

#define	CAN_F11R1_FB24_Msk (0x1UL << CAN_F11R1_FB24_Pos)

#define	CAN_F11R1_FB24 CAN_F11R1_FB24_Msk

#define	CAN_F11R1_FB25_Pos (25U)

#define	CAN_F11R1_FB25_Msk (0x1UL << CAN_F11R1_FB25_Pos)

#define	CAN_F11R1_FB25 CAN_F11R1_FB25_Msk

#define	CAN_F11R1_FB26_Pos (26U)

#define	CAN_F11R1_FB26_Msk (0x1UL << CAN_F11R1_FB26_Pos)

#define	CAN_F11R1_FB26 CAN_F11R1_FB26_Msk

#define	CAN_F11R1_FB27_Pos (27U)

#define	CAN_F11R1_FB27_Msk (0x1UL << CAN_F11R1_FB27_Pos)

#define	CAN_F11R1_FB27 CAN_F11R1_FB27_Msk

#define	CAN_F11R1_FB28_Pos (28U)

#define	CAN_F11R1_FB28_Msk (0x1UL << CAN_F11R1_FB28_Pos)

#define	CAN_F11R1_FB28 CAN_F11R1_FB28_Msk

#define	CAN_F11R1_FB29_Pos (29U)

#define	CAN_F11R1_FB29_Msk (0x1UL << CAN_F11R1_FB29_Pos)

#define	CAN_F11R1_FB29 CAN_F11R1_FB29_Msk

#define	CAN_F11R1_FB30_Pos (30U)

#define	CAN_F11R1_FB30_Msk (0x1UL << CAN_F11R1_FB30_Pos)

#define	CAN_F11R1_FB30 CAN_F11R1_FB30_Msk

#define	CAN_F11R1_FB31_Pos (31U)

#define	CAN_F11R1_FB31_Msk (0x1UL << CAN_F11R1_FB31_Pos)

#define	CAN_F11R1_FB31 CAN_F11R1_FB31_Msk

#define	CAN_F12R1_FB0_Pos (0U)

#define	CAN_F12R1_FB0_Msk (0x1UL << CAN_F12R1_FB0_Pos)

#define	CAN_F12R1_FB0 CAN_F12R1_FB0_Msk

#define	CAN_F12R1_FB1_Pos (1U)

#define	CAN_F12R1_FB1_Msk (0x1UL << CAN_F12R1_FB1_Pos)

#define	CAN_F12R1_FB1 CAN_F12R1_FB1_Msk

#define	CAN_F12R1_FB2_Pos (2U)

#define	CAN_F12R1_FB2_Msk (0x1UL << CAN_F12R1_FB2_Pos)

#define	CAN_F12R1_FB2 CAN_F12R1_FB2_Msk

#define	CAN_F12R1_FB3_Pos (3U)

#define	CAN_F12R1_FB3_Msk (0x1UL << CAN_F12R1_FB3_Pos)

#define	CAN_F12R1_FB3 CAN_F12R1_FB3_Msk

#define	CAN_F12R1_FB4_Pos (4U)

#define	CAN_F12R1_FB4_Msk (0x1UL << CAN_F12R1_FB4_Pos)

#define	CAN_F12R1_FB4 CAN_F12R1_FB4_Msk

#define	CAN_F12R1_FB5_Pos (5U)

#define	CAN_F12R1_FB5_Msk (0x1UL << CAN_F12R1_FB5_Pos)

#define	CAN_F12R1_FB5 CAN_F12R1_FB5_Msk

#define	CAN_F12R1_FB6_Pos (6U)

#define	CAN_F12R1_FB6_Msk (0x1UL << CAN_F12R1_FB6_Pos)

#define	CAN_F12R1_FB6 CAN_F12R1_FB6_Msk

#define	CAN_F12R1_FB7_Pos (7U)

#define	CAN_F12R1_FB7_Msk (0x1UL << CAN_F12R1_FB7_Pos)

#define	CAN_F12R1_FB7 CAN_F12R1_FB7_Msk

#define	CAN_F12R1_FB8_Pos (8U)

#define	CAN_F12R1_FB8_Msk (0x1UL << CAN_F12R1_FB8_Pos)

#define	CAN_F12R1_FB8 CAN_F12R1_FB8_Msk

#define	CAN_F12R1_FB9_Pos (9U)

#define	CAN_F12R1_FB9_Msk (0x1UL << CAN_F12R1_FB9_Pos)

#define	CAN_F12R1_FB9 CAN_F12R1_FB9_Msk

#define	CAN_F12R1_FB10_Pos (10U)

#define	CAN_F12R1_FB10_Msk (0x1UL << CAN_F12R1_FB10_Pos)

#define	CAN_F12R1_FB10 CAN_F12R1_FB10_Msk

#define	CAN_F12R1_FB11_Pos (11U)

#define	CAN_F12R1_FB11_Msk (0x1UL << CAN_F12R1_FB11_Pos)

#define	CAN_F12R1_FB11 CAN_F12R1_FB11_Msk

#define	CAN_F12R1_FB12_Pos (12U)

#define	CAN_F12R1_FB12_Msk (0x1UL << CAN_F12R1_FB12_Pos)

#define	CAN_F12R1_FB12 CAN_F12R1_FB12_Msk

#define	CAN_F12R1_FB13_Pos (13U)

#define	CAN_F12R1_FB13_Msk (0x1UL << CAN_F12R1_FB13_Pos)

#define	CAN_F12R1_FB13 CAN_F12R1_FB13_Msk

#define	CAN_F12R1_FB14_Pos (14U)

#define	CAN_F12R1_FB14_Msk (0x1UL << CAN_F12R1_FB14_Pos)

#define	CAN_F12R1_FB14 CAN_F12R1_FB14_Msk

#define	CAN_F12R1_FB15_Pos (15U)

#define	CAN_F12R1_FB15_Msk (0x1UL << CAN_F12R1_FB15_Pos)

#define	CAN_F12R1_FB15 CAN_F12R1_FB15_Msk

#define	CAN_F12R1_FB16_Pos (16U)

#define	CAN_F12R1_FB16_Msk (0x1UL << CAN_F12R1_FB16_Pos)

#define	CAN_F12R1_FB16 CAN_F12R1_FB16_Msk

#define	CAN_F12R1_FB17_Pos (17U)

#define	CAN_F12R1_FB17_Msk (0x1UL << CAN_F12R1_FB17_Pos)

#define	CAN_F12R1_FB17 CAN_F12R1_FB17_Msk

#define	CAN_F12R1_FB18_Pos (18U)

#define	CAN_F12R1_FB18_Msk (0x1UL << CAN_F12R1_FB18_Pos)

#define	CAN_F12R1_FB18 CAN_F12R1_FB18_Msk

#define	CAN_F12R1_FB19_Pos (19U)

#define	CAN_F12R1_FB19_Msk (0x1UL << CAN_F12R1_FB19_Pos)

#define	CAN_F12R1_FB19 CAN_F12R1_FB19_Msk

#define	CAN_F12R1_FB20_Pos (20U)

#define	CAN_F12R1_FB20_Msk (0x1UL << CAN_F12R1_FB20_Pos)

#define	CAN_F12R1_FB20 CAN_F12R1_FB20_Msk

#define	CAN_F12R1_FB21_Pos (21U)

#define	CAN_F12R1_FB21_Msk (0x1UL << CAN_F12R1_FB21_Pos)

#define	CAN_F12R1_FB21 CAN_F12R1_FB21_Msk

#define	CAN_F12R1_FB22_Pos (22U)

#define	CAN_F12R1_FB22_Msk (0x1UL << CAN_F12R1_FB22_Pos)

#define	CAN_F12R1_FB22 CAN_F12R1_FB22_Msk

#define	CAN_F12R1_FB23_Pos (23U)

#define	CAN_F12R1_FB23_Msk (0x1UL << CAN_F12R1_FB23_Pos)

#define	CAN_F12R1_FB23 CAN_F12R1_FB23_Msk

#define	CAN_F12R1_FB24_Pos (24U)

#define	CAN_F12R1_FB24_Msk (0x1UL << CAN_F12R1_FB24_Pos)

#define	CAN_F12R1_FB24 CAN_F12R1_FB24_Msk

#define	CAN_F12R1_FB25_Pos (25U)

#define	CAN_F12R1_FB25_Msk (0x1UL << CAN_F12R1_FB25_Pos)

#define	CAN_F12R1_FB25 CAN_F12R1_FB25_Msk

#define	CAN_F12R1_FB26_Pos (26U)

#define	CAN_F12R1_FB26_Msk (0x1UL << CAN_F12R1_FB26_Pos)

#define	CAN_F12R1_FB26 CAN_F12R1_FB26_Msk

#define	CAN_F12R1_FB27_Pos (27U)

#define	CAN_F12R1_FB27_Msk (0x1UL << CAN_F12R1_FB27_Pos)

#define	CAN_F12R1_FB27 CAN_F12R1_FB27_Msk

#define	CAN_F12R1_FB28_Pos (28U)

#define	CAN_F12R1_FB28_Msk (0x1UL << CAN_F12R1_FB28_Pos)

#define	CAN_F12R1_FB28 CAN_F12R1_FB28_Msk

#define	CAN_F12R1_FB29_Pos (29U)

#define	CAN_F12R1_FB29_Msk (0x1UL << CAN_F12R1_FB29_Pos)

#define	CAN_F12R1_FB29 CAN_F12R1_FB29_Msk

#define	CAN_F12R1_FB30_Pos (30U)

#define	CAN_F12R1_FB30_Msk (0x1UL << CAN_F12R1_FB30_Pos)

#define	CAN_F12R1_FB30 CAN_F12R1_FB30_Msk

#define	CAN_F12R1_FB31_Pos (31U)

#define	CAN_F12R1_FB31_Msk (0x1UL << CAN_F12R1_FB31_Pos)

#define	CAN_F12R1_FB31 CAN_F12R1_FB31_Msk

#define	CAN_F13R1_FB0_Pos (0U)

#define	CAN_F13R1_FB0_Msk (0x1UL << CAN_F13R1_FB0_Pos)

#define	CAN_F13R1_FB0 CAN_F13R1_FB0_Msk

#define	CAN_F13R1_FB1_Pos (1U)

#define	CAN_F13R1_FB1_Msk (0x1UL << CAN_F13R1_FB1_Pos)

#define	CAN_F13R1_FB1 CAN_F13R1_FB1_Msk

#define	CAN_F13R1_FB2_Pos (2U)

#define	CAN_F13R1_FB2_Msk (0x1UL << CAN_F13R1_FB2_Pos)

#define	CAN_F13R1_FB2 CAN_F13R1_FB2_Msk

#define	CAN_F13R1_FB3_Pos (3U)

#define	CAN_F13R1_FB3_Msk (0x1UL << CAN_F13R1_FB3_Pos)

#define	CAN_F13R1_FB3 CAN_F13R1_FB3_Msk

#define	CAN_F13R1_FB4_Pos (4U)

#define	CAN_F13R1_FB4_Msk (0x1UL << CAN_F13R1_FB4_Pos)

#define	CAN_F13R1_FB4 CAN_F13R1_FB4_Msk

#define	CAN_F13R1_FB5_Pos (5U)

#define	CAN_F13R1_FB5_Msk (0x1UL << CAN_F13R1_FB5_Pos)

#define	CAN_F13R1_FB5 CAN_F13R1_FB5_Msk

#define	CAN_F13R1_FB6_Pos (6U)

#define	CAN_F13R1_FB6_Msk (0x1UL << CAN_F13R1_FB6_Pos)

#define	CAN_F13R1_FB6 CAN_F13R1_FB6_Msk

#define	CAN_F13R1_FB7_Pos (7U)

#define	CAN_F13R1_FB7_Msk (0x1UL << CAN_F13R1_FB7_Pos)

#define	CAN_F13R1_FB7 CAN_F13R1_FB7_Msk

#define	CAN_F13R1_FB8_Pos (8U)

#define	CAN_F13R1_FB8_Msk (0x1UL << CAN_F13R1_FB8_Pos)

#define	CAN_F13R1_FB8 CAN_F13R1_FB8_Msk

#define	CAN_F13R1_FB9_Pos (9U)

#define	CAN_F13R1_FB9_Msk (0x1UL << CAN_F13R1_FB9_Pos)

#define	CAN_F13R1_FB9 CAN_F13R1_FB9_Msk

#define	CAN_F13R1_FB10_Pos (10U)

#define	CAN_F13R1_FB10_Msk (0x1UL << CAN_F13R1_FB10_Pos)

#define	CAN_F13R1_FB10 CAN_F13R1_FB10_Msk

#define	CAN_F13R1_FB11_Pos (11U)

#define	CAN_F13R1_FB11_Msk (0x1UL << CAN_F13R1_FB11_Pos)

#define	CAN_F13R1_FB11 CAN_F13R1_FB11_Msk

#define	CAN_F13R1_FB12_Pos (12U)

#define	CAN_F13R1_FB12_Msk (0x1UL << CAN_F13R1_FB12_Pos)

#define	CAN_F13R1_FB12 CAN_F13R1_FB12_Msk

#define	CAN_F13R1_FB13_Pos (13U)

#define	CAN_F13R1_FB13_Msk (0x1UL << CAN_F13R1_FB13_Pos)

#define	CAN_F13R1_FB13 CAN_F13R1_FB13_Msk

#define	CAN_F13R1_FB14_Pos (14U)

#define	CAN_F13R1_FB14_Msk (0x1UL << CAN_F13R1_FB14_Pos)

#define	CAN_F13R1_FB14 CAN_F13R1_FB14_Msk

#define	CAN_F13R1_FB15_Pos (15U)

#define	CAN_F13R1_FB15_Msk (0x1UL << CAN_F13R1_FB15_Pos)

#define	CAN_F13R1_FB15 CAN_F13R1_FB15_Msk

#define	CAN_F13R1_FB16_Pos (16U)

#define	CAN_F13R1_FB16_Msk (0x1UL << CAN_F13R1_FB16_Pos)

#define	CAN_F13R1_FB16 CAN_F13R1_FB16_Msk

#define	CAN_F13R1_FB17_Pos (17U)

#define	CAN_F13R1_FB17_Msk (0x1UL << CAN_F13R1_FB17_Pos)

#define	CAN_F13R1_FB17 CAN_F13R1_FB17_Msk

#define	CAN_F13R1_FB18_Pos (18U)

#define	CAN_F13R1_FB18_Msk (0x1UL << CAN_F13R1_FB18_Pos)

#define	CAN_F13R1_FB18 CAN_F13R1_FB18_Msk

#define	CAN_F13R1_FB19_Pos (19U)

#define	CAN_F13R1_FB19_Msk (0x1UL << CAN_F13R1_FB19_Pos)

#define	CAN_F13R1_FB19 CAN_F13R1_FB19_Msk

#define	CAN_F13R1_FB20_Pos (20U)

#define	CAN_F13R1_FB20_Msk (0x1UL << CAN_F13R1_FB20_Pos)

#define	CAN_F13R1_FB20 CAN_F13R1_FB20_Msk

#define	CAN_F13R1_FB21_Pos (21U)

#define	CAN_F13R1_FB21_Msk (0x1UL << CAN_F13R1_FB21_Pos)

#define	CAN_F13R1_FB21 CAN_F13R1_FB21_Msk

#define	CAN_F13R1_FB22_Pos (22U)

#define	CAN_F13R1_FB22_Msk (0x1UL << CAN_F13R1_FB22_Pos)

#define	CAN_F13R1_FB22 CAN_F13R1_FB22_Msk

#define	CAN_F13R1_FB23_Pos (23U)

#define	CAN_F13R1_FB23_Msk (0x1UL << CAN_F13R1_FB23_Pos)

#define	CAN_F13R1_FB23 CAN_F13R1_FB23_Msk

#define	CAN_F13R1_FB24_Pos (24U)

#define	CAN_F13R1_FB24_Msk (0x1UL << CAN_F13R1_FB24_Pos)

#define	CAN_F13R1_FB24 CAN_F13R1_FB24_Msk

#define	CAN_F13R1_FB25_Pos (25U)

#define	CAN_F13R1_FB25_Msk (0x1UL << CAN_F13R1_FB25_Pos)

#define	CAN_F13R1_FB25 CAN_F13R1_FB25_Msk

#define	CAN_F13R1_FB26_Pos (26U)

#define	CAN_F13R1_FB26_Msk (0x1UL << CAN_F13R1_FB26_Pos)

#define	CAN_F13R1_FB26 CAN_F13R1_FB26_Msk

#define	CAN_F13R1_FB27_Pos (27U)

#define	CAN_F13R1_FB27_Msk (0x1UL << CAN_F13R1_FB27_Pos)

#define	CAN_F13R1_FB27 CAN_F13R1_FB27_Msk

#define	CAN_F13R1_FB28_Pos (28U)

#define	CAN_F13R1_FB28_Msk (0x1UL << CAN_F13R1_FB28_Pos)

#define	CAN_F13R1_FB28 CAN_F13R1_FB28_Msk

#define	CAN_F13R1_FB29_Pos (29U)

#define	CAN_F13R1_FB29_Msk (0x1UL << CAN_F13R1_FB29_Pos)

#define	CAN_F13R1_FB29 CAN_F13R1_FB29_Msk

#define	CAN_F13R1_FB30_Pos (30U)

#define	CAN_F13R1_FB30_Msk (0x1UL << CAN_F13R1_FB30_Pos)

#define	CAN_F13R1_FB30 CAN_F13R1_FB30_Msk

#define	CAN_F13R1_FB31_Pos (31U)

#define	CAN_F13R1_FB31_Msk (0x1UL << CAN_F13R1_FB31_Pos)

#define	CAN_F13R1_FB31 CAN_F13R1_FB31_Msk

#define	CAN_F14R1_FB0_Pos (0U)

#define	CAN_F14R1_FB0_Msk (0x1UL << CAN_F14R1_FB0_Pos)

#define	CAN_F14R1_FB0 CAN_F14R1_FB0_Msk

#define	CAN_F14R1_FB1_Pos (1U)

#define	CAN_F14R1_FB1_Msk (0x1UL << CAN_F14R1_FB1_Pos)

#define	CAN_F14R1_FB1 CAN_F14R1_FB1_Msk

#define	CAN_F14R1_FB2_Pos (2U)

#define	CAN_F14R1_FB2_Msk (0x1UL << CAN_F14R1_FB2_Pos)

#define	CAN_F14R1_FB2 CAN_F14R1_FB2_Msk

#define	CAN_F14R1_FB3_Pos (3U)

#define	CAN_F14R1_FB3_Msk (0x1UL << CAN_F14R1_FB3_Pos)

#define	CAN_F14R1_FB3 CAN_F14R1_FB3_Msk

#define	CAN_F14R1_FB4_Pos (4U)

#define	CAN_F14R1_FB4_Msk (0x1UL << CAN_F14R1_FB4_Pos)

#define	CAN_F14R1_FB4 CAN_F14R1_FB4_Msk

#define	CAN_F14R1_FB5_Pos (5U)

#define	CAN_F14R1_FB5_Msk (0x1UL << CAN_F14R1_FB5_Pos)

#define	CAN_F14R1_FB5 CAN_F14R1_FB5_Msk

#define	CAN_F14R1_FB6_Pos (6U)

#define	CAN_F14R1_FB6_Msk (0x1UL << CAN_F14R1_FB6_Pos)

#define	CAN_F14R1_FB6 CAN_F14R1_FB6_Msk

#define	CAN_F14R1_FB7_Pos (7U)

#define	CAN_F14R1_FB7_Msk (0x1UL << CAN_F14R1_FB7_Pos)

#define	CAN_F14R1_FB7 CAN_F14R1_FB7_Msk

#define	CAN_F14R1_FB8_Pos (8U)

#define	CAN_F14R1_FB8_Msk (0x1UL << CAN_F14R1_FB8_Pos)

#define	CAN_F14R1_FB8 CAN_F14R1_FB8_Msk

#define	CAN_F14R1_FB9_Pos (9U)

#define	CAN_F14R1_FB9_Msk (0x1UL << CAN_F14R1_FB9_Pos)

#define	CAN_F14R1_FB9 CAN_F14R1_FB9_Msk

#define	CAN_F14R1_FB10_Pos (10U)

#define	CAN_F14R1_FB10_Msk (0x1UL << CAN_F14R1_FB10_Pos)

#define	CAN_F14R1_FB10 CAN_F14R1_FB10_Msk

#define	CAN_F14R1_FB11_Pos (11U)

#define	CAN_F14R1_FB11_Msk (0x1UL << CAN_F14R1_FB11_Pos)

#define	CAN_F14R1_FB11 CAN_F14R1_FB11_Msk

#define	CAN_F14R1_FB12_Pos (12U)

#define	CAN_F14R1_FB12_Msk (0x1UL << CAN_F14R1_FB12_Pos)

#define	CAN_F14R1_FB12 CAN_F14R1_FB12_Msk

#define	CAN_F14R1_FB13_Pos (13U)

#define	CAN_F14R1_FB13_Msk (0x1UL << CAN_F14R1_FB13_Pos)

#define	CAN_F14R1_FB13 CAN_F14R1_FB13_Msk

#define	CAN_F14R1_FB14_Pos (14U)

#define	CAN_F14R1_FB14_Msk (0x1UL << CAN_F14R1_FB14_Pos)

#define	CAN_F14R1_FB14 CAN_F14R1_FB14_Msk

#define	CAN_F14R1_FB15_Pos (15U)

#define	CAN_F14R1_FB15_Msk (0x1UL << CAN_F14R1_FB15_Pos)

#define	CAN_F14R1_FB15 CAN_F14R1_FB15_Msk

#define	CAN_F14R1_FB16_Pos (16U)

#define	CAN_F14R1_FB16_Msk (0x1UL << CAN_F14R1_FB16_Pos)

#define	CAN_F14R1_FB16 CAN_F14R1_FB16_Msk

#define	CAN_F14R1_FB17_Pos (17U)

#define	CAN_F14R1_FB17_Msk (0x1UL << CAN_F14R1_FB17_Pos)

#define	CAN_F14R1_FB17 CAN_F14R1_FB17_Msk

#define	CAN_F14R1_FB18_Pos (18U)

#define	CAN_F14R1_FB18_Msk (0x1UL << CAN_F14R1_FB18_Pos)

#define	CAN_F14R1_FB18 CAN_F14R1_FB18_Msk

#define	CAN_F14R1_FB19_Pos (19U)

#define	CAN_F14R1_FB19_Msk (0x1UL << CAN_F14R1_FB19_Pos)

#define	CAN_F14R1_FB19 CAN_F14R1_FB19_Msk

#define	CAN_F14R1_FB20_Pos (20U)

#define	CAN_F14R1_FB20_Msk (0x1UL << CAN_F14R1_FB20_Pos)

#define	CAN_F14R1_FB20 CAN_F14R1_FB20_Msk

#define	CAN_F14R1_FB21_Pos (21U)

#define	CAN_F14R1_FB21_Msk (0x1UL << CAN_F14R1_FB21_Pos)

#define	CAN_F14R1_FB21 CAN_F14R1_FB21_Msk

#define	CAN_F14R1_FB22_Pos (22U)

#define	CAN_F14R1_FB22_Msk (0x1UL << CAN_F14R1_FB22_Pos)

#define	CAN_F14R1_FB22 CAN_F14R1_FB22_Msk

#define	CAN_F14R1_FB23_Pos (23U)

#define	CAN_F14R1_FB23_Msk (0x1UL << CAN_F14R1_FB23_Pos)

#define	CAN_F14R1_FB23 CAN_F14R1_FB23_Msk

#define	CAN_F14R1_FB24_Pos (24U)

#define	CAN_F14R1_FB24_Msk (0x1UL << CAN_F14R1_FB24_Pos)

#define	CAN_F14R1_FB24 CAN_F14R1_FB24_Msk

#define	CAN_F14R1_FB25_Pos (25U)

#define	CAN_F14R1_FB25_Msk (0x1UL << CAN_F14R1_FB25_Pos)

#define	CAN_F14R1_FB25 CAN_F14R1_FB25_Msk

#define	CAN_F14R1_FB26_Pos (26U)

#define	CAN_F14R1_FB26_Msk (0x1UL << CAN_F14R1_FB26_Pos)

#define	CAN_F14R1_FB26 CAN_F14R1_FB26_Msk

#define	CAN_F14R1_FB27_Pos (27U)

#define	CAN_F14R1_FB27_Msk (0x1UL << CAN_F14R1_FB27_Pos)

#define	CAN_F14R1_FB27 CAN_F14R1_FB27_Msk

#define	CAN_F14R1_FB28_Pos (28U)

#define	CAN_F14R1_FB28_Msk (0x1UL << CAN_F14R1_FB28_Pos)

#define	CAN_F14R1_FB28 CAN_F14R1_FB28_Msk

#define	CAN_F14R1_FB29_Pos (29U)

#define	CAN_F14R1_FB29_Msk (0x1UL << CAN_F14R1_FB29_Pos)

#define	CAN_F14R1_FB29 CAN_F14R1_FB29_Msk

#define	CAN_F14R1_FB30_Pos (30U)

#define	CAN_F14R1_FB30_Msk (0x1UL << CAN_F14R1_FB30_Pos)

#define	CAN_F14R1_FB30 CAN_F14R1_FB30_Msk

#define	CAN_F14R1_FB31_Pos (31U)

#define	CAN_F14R1_FB31_Msk (0x1UL << CAN_F14R1_FB31_Pos)

#define	CAN_F14R1_FB31 CAN_F14R1_FB31_Msk

#define	CAN_F15R1_FB0_Pos (0U)

#define	CAN_F15R1_FB0_Msk (0x1UL << CAN_F15R1_FB0_Pos)

#define	CAN_F15R1_FB0 CAN_F15R1_FB0_Msk

#define	CAN_F15R1_FB1_Pos (1U)

#define	CAN_F15R1_FB1_Msk (0x1UL << CAN_F15R1_FB1_Pos)

#define	CAN_F15R1_FB1 CAN_F15R1_FB1_Msk

#define	CAN_F15R1_FB2_Pos (2U)

#define	CAN_F15R1_FB2_Msk (0x1UL << CAN_F15R1_FB2_Pos)

#define	CAN_F15R1_FB2 CAN_F15R1_FB2_Msk

#define	CAN_F15R1_FB3_Pos (3U)

#define	CAN_F15R1_FB3_Msk (0x1UL << CAN_F15R1_FB3_Pos)

#define	CAN_F15R1_FB3 CAN_F15R1_FB3_Msk

#define	CAN_F15R1_FB4_Pos (4U)

#define	CAN_F15R1_FB4_Msk (0x1UL << CAN_F15R1_FB4_Pos)

#define	CAN_F15R1_FB4 CAN_F15R1_FB4_Msk

#define	CAN_F15R1_FB5_Pos (5U)

#define	CAN_F15R1_FB5_Msk (0x1UL << CAN_F15R1_FB5_Pos)

#define	CAN_F15R1_FB5 CAN_F15R1_FB5_Msk

#define	CAN_F15R1_FB6_Pos (6U)

#define	CAN_F15R1_FB6_Msk (0x1UL << CAN_F15R1_FB6_Pos)

#define	CAN_F15R1_FB6 CAN_F15R1_FB6_Msk

#define	CAN_F15R1_FB7_Pos (7U)

#define	CAN_F15R1_FB7_Msk (0x1UL << CAN_F15R1_FB7_Pos)

#define	CAN_F15R1_FB7 CAN_F15R1_FB7_Msk

#define	CAN_F15R1_FB8_Pos (8U)

#define	CAN_F15R1_FB8_Msk (0x1UL << CAN_F15R1_FB8_Pos)

#define	CAN_F15R1_FB8 CAN_F15R1_FB8_Msk

#define	CAN_F15R1_FB9_Pos (9U)

#define	CAN_F15R1_FB9_Msk (0x1UL << CAN_F15R1_FB9_Pos)

#define	CAN_F15R1_FB9 CAN_F15R1_FB9_Msk

#define	CAN_F15R1_FB10_Pos (10U)

#define	CAN_F15R1_FB10_Msk (0x1UL << CAN_F15R1_FB10_Pos)

#define	CAN_F15R1_FB10 CAN_F15R1_FB10_Msk

#define	CAN_F15R1_FB11_Pos (11U)

#define	CAN_F15R1_FB11_Msk (0x1UL << CAN_F15R1_FB11_Pos)

#define	CAN_F15R1_FB11 CAN_F15R1_FB11_Msk

#define	CAN_F15R1_FB12_Pos (12U)

#define	CAN_F15R1_FB12_Msk (0x1UL << CAN_F15R1_FB12_Pos)

#define	CAN_F15R1_FB12 CAN_F15R1_FB12_Msk

#define	CAN_F15R1_FB13_Pos (13U)

#define	CAN_F15R1_FB13_Msk (0x1UL << CAN_F15R1_FB13_Pos)

#define	CAN_F15R1_FB13 CAN_F15R1_FB13_Msk

#define	CAN_F15R1_FB14_Pos (14U)

#define	CAN_F15R1_FB14_Msk (0x1UL << CAN_F15R1_FB14_Pos)

#define	CAN_F15R1_FB14 CAN_F15R1_FB14_Msk

#define	CAN_F15R1_FB15_Pos (15U)

#define	CAN_F15R1_FB15_Msk (0x1UL << CAN_F15R1_FB15_Pos)

#define	CAN_F15R1_FB15 CAN_F15R1_FB15_Msk

#define	CAN_F15R1_FB16_Pos (16U)

#define	CAN_F15R1_FB16_Msk (0x1UL << CAN_F15R1_FB16_Pos)

#define	CAN_F15R1_FB16 CAN_F15R1_FB16_Msk

#define	CAN_F15R1_FB17_Pos (17U)

#define	CAN_F15R1_FB17_Msk (0x1UL << CAN_F15R1_FB17_Pos)

#define	CAN_F15R1_FB17 CAN_F15R1_FB17_Msk

#define	CAN_F15R1_FB18_Pos (18U)

#define	CAN_F15R1_FB18_Msk (0x1UL << CAN_F15R1_FB18_Pos)

#define	CAN_F15R1_FB18 CAN_F15R1_FB18_Msk

#define	CAN_F15R1_FB19_Pos (19U)

#define	CAN_F15R1_FB19_Msk (0x1UL << CAN_F15R1_FB19_Pos)

#define	CAN_F15R1_FB19 CAN_F15R1_FB19_Msk

#define	CAN_F15R1_FB20_Pos (20U)

#define	CAN_F15R1_FB20_Msk (0x1UL << CAN_F15R1_FB20_Pos)

#define	CAN_F15R1_FB20 CAN_F15R1_FB20_Msk

#define	CAN_F15R1_FB21_Pos (21U)

#define	CAN_F15R1_FB21_Msk (0x1UL << CAN_F15R1_FB21_Pos)

#define	CAN_F15R1_FB21 CAN_F15R1_FB21_Msk

#define	CAN_F15R1_FB22_Pos (22U)

#define	CAN_F15R1_FB22_Msk (0x1UL << CAN_F15R1_FB22_Pos)

#define	CAN_F15R1_FB22 CAN_F15R1_FB22_Msk

#define	CAN_F15R1_FB23_Pos (23U)

#define	CAN_F15R1_FB23_Msk (0x1UL << CAN_F15R1_FB23_Pos)

#define	CAN_F15R1_FB23 CAN_F15R1_FB23_Msk

#define	CAN_F15R1_FB24_Pos (24U)

#define	CAN_F15R1_FB24_Msk (0x1UL << CAN_F15R1_FB24_Pos)

#define	CAN_F15R1_FB24 CAN_F15R1_FB24_Msk

#define	CAN_F15R1_FB25_Pos (25U)

#define	CAN_F15R1_FB25_Msk (0x1UL << CAN_F15R1_FB25_Pos)

#define	CAN_F15R1_FB25 CAN_F15R1_FB25_Msk

#define	CAN_F15R1_FB26_Pos (26U)

#define	CAN_F15R1_FB26_Msk (0x1UL << CAN_F15R1_FB26_Pos)

#define	CAN_F15R1_FB26 CAN_F15R1_FB26_Msk

#define	CAN_F15R1_FB27_Pos (27U)

#define	CAN_F15R1_FB27_Msk (0x1UL << CAN_F15R1_FB27_Pos)

#define	CAN_F15R1_FB27 CAN_F15R1_FB27_Msk

#define	CAN_F15R1_FB28_Pos (28U)

#define	CAN_F15R1_FB28_Msk (0x1UL << CAN_F15R1_FB28_Pos)

#define	CAN_F15R1_FB28 CAN_F15R1_FB28_Msk

#define	CAN_F15R1_FB29_Pos (29U)

#define	CAN_F15R1_FB29_Msk (0x1UL << CAN_F15R1_FB29_Pos)

#define	CAN_F15R1_FB29 CAN_F15R1_FB29_Msk

#define	CAN_F15R1_FB30_Pos (30U)

#define	CAN_F15R1_FB30_Msk (0x1UL << CAN_F15R1_FB30_Pos)

#define	CAN_F15R1_FB30 CAN_F15R1_FB30_Msk

#define	CAN_F15R1_FB31_Pos (31U)

#define	CAN_F15R1_FB31_Msk (0x1UL << CAN_F15R1_FB31_Pos)

#define	CAN_F15R1_FB31 CAN_F15R1_FB31_Msk

#define	CAN_F16R1_FB0_Pos (0U)

#define	CAN_F16R1_FB0_Msk (0x1UL << CAN_F16R1_FB0_Pos)

#define	CAN_F16R1_FB0 CAN_F16R1_FB0_Msk

#define	CAN_F16R1_FB1_Pos (1U)

#define	CAN_F16R1_FB1_Msk (0x1UL << CAN_F16R1_FB1_Pos)

#define	CAN_F16R1_FB1 CAN_F16R1_FB1_Msk

#define	CAN_F16R1_FB2_Pos (2U)

#define	CAN_F16R1_FB2_Msk (0x1UL << CAN_F16R1_FB2_Pos)

#define	CAN_F16R1_FB2 CAN_F16R1_FB2_Msk

#define	CAN_F16R1_FB3_Pos (3U)

#define	CAN_F16R1_FB3_Msk (0x1UL << CAN_F16R1_FB3_Pos)

#define	CAN_F16R1_FB3 CAN_F16R1_FB3_Msk

#define	CAN_F16R1_FB4_Pos (4U)

#define	CAN_F16R1_FB4_Msk (0x1UL << CAN_F16R1_FB4_Pos)

#define	CAN_F16R1_FB4 CAN_F16R1_FB4_Msk

#define	CAN_F16R1_FB5_Pos (5U)

#define	CAN_F16R1_FB5_Msk (0x1UL << CAN_F16R1_FB5_Pos)

#define	CAN_F16R1_FB5 CAN_F16R1_FB5_Msk

#define	CAN_F16R1_FB6_Pos (6U)

#define	CAN_F16R1_FB6_Msk (0x1UL << CAN_F16R1_FB6_Pos)

#define	CAN_F16R1_FB6 CAN_F16R1_FB6_Msk

#define	CAN_F16R1_FB7_Pos (7U)

#define	CAN_F16R1_FB7_Msk (0x1UL << CAN_F16R1_FB7_Pos)

#define	CAN_F16R1_FB7 CAN_F16R1_FB7_Msk

#define	CAN_F16R1_FB8_Pos (8U)

#define	CAN_F16R1_FB8_Msk (0x1UL << CAN_F16R1_FB8_Pos)

#define	CAN_F16R1_FB8 CAN_F16R1_FB8_Msk

#define	CAN_F16R1_FB9_Pos (9U)

#define	CAN_F16R1_FB9_Msk (0x1UL << CAN_F16R1_FB9_Pos)

#define	CAN_F16R1_FB9 CAN_F16R1_FB9_Msk

#define	CAN_F16R1_FB10_Pos (10U)

#define	CAN_F16R1_FB10_Msk (0x1UL << CAN_F16R1_FB10_Pos)

#define	CAN_F16R1_FB10 CAN_F16R1_FB10_Msk

#define	CAN_F16R1_FB11_Pos (11U)

#define	CAN_F16R1_FB11_Msk (0x1UL << CAN_F16R1_FB11_Pos)

#define	CAN_F16R1_FB11 CAN_F16R1_FB11_Msk

#define	CAN_F16R1_FB12_Pos (12U)

#define	CAN_F16R1_FB12_Msk (0x1UL << CAN_F16R1_FB12_Pos)

#define	CAN_F16R1_FB12 CAN_F16R1_FB12_Msk

#define	CAN_F16R1_FB13_Pos (13U)

#define	CAN_F16R1_FB13_Msk (0x1UL << CAN_F16R1_FB13_Pos)

#define	CAN_F16R1_FB13 CAN_F16R1_FB13_Msk

#define	CAN_F16R1_FB14_Pos (14U)

#define	CAN_F16R1_FB14_Msk (0x1UL << CAN_F16R1_FB14_Pos)

#define	CAN_F16R1_FB14 CAN_F16R1_FB14_Msk

#define	CAN_F16R1_FB15_Pos (15U)

#define	CAN_F16R1_FB15_Msk (0x1UL << CAN_F16R1_FB15_Pos)

#define	CAN_F16R1_FB15 CAN_F16R1_FB15_Msk

#define	CAN_F16R1_FB16_Pos (16U)

#define	CAN_F16R1_FB16_Msk (0x1UL << CAN_F16R1_FB16_Pos)

#define	CAN_F16R1_FB16 CAN_F16R1_FB16_Msk

#define	CAN_F16R1_FB17_Pos (17U)

#define	CAN_F16R1_FB17_Msk (0x1UL << CAN_F16R1_FB17_Pos)

#define	CAN_F16R1_FB17 CAN_F16R1_FB17_Msk

#define	CAN_F16R1_FB18_Pos (18U)

#define	CAN_F16R1_FB18_Msk (0x1UL << CAN_F16R1_FB18_Pos)

#define	CAN_F16R1_FB18 CAN_F16R1_FB18_Msk

#define	CAN_F16R1_FB19_Pos (19U)

#define	CAN_F16R1_FB19_Msk (0x1UL << CAN_F16R1_FB19_Pos)

#define	CAN_F16R1_FB19 CAN_F16R1_FB19_Msk

#define	CAN_F16R1_FB20_Pos (20U)

#define	CAN_F16R1_FB20_Msk (0x1UL << CAN_F16R1_FB20_Pos)

#define	CAN_F16R1_FB20 CAN_F16R1_FB20_Msk

#define	CAN_F16R1_FB21_Pos (21U)

#define	CAN_F16R1_FB21_Msk (0x1UL << CAN_F16R1_FB21_Pos)

#define	CAN_F16R1_FB21 CAN_F16R1_FB21_Msk

#define	CAN_F16R1_FB22_Pos (22U)

#define	CAN_F16R1_FB22_Msk (0x1UL << CAN_F16R1_FB22_Pos)

#define	CAN_F16R1_FB22 CAN_F16R1_FB22_Msk

#define	CAN_F16R1_FB23_Pos (23U)

#define	CAN_F16R1_FB23_Msk (0x1UL << CAN_F16R1_FB23_Pos)

#define	CAN_F16R1_FB23 CAN_F16R1_FB23_Msk

#define	CAN_F16R1_FB24_Pos (24U)

#define	CAN_F16R1_FB24_Msk (0x1UL << CAN_F16R1_FB24_Pos)

#define	CAN_F16R1_FB24 CAN_F16R1_FB24_Msk

#define	CAN_F16R1_FB25_Pos (25U)

#define	CAN_F16R1_FB25_Msk (0x1UL << CAN_F16R1_FB25_Pos)

#define	CAN_F16R1_FB25 CAN_F16R1_FB25_Msk

#define	CAN_F16R1_FB26_Pos (26U)

#define	CAN_F16R1_FB26_Msk (0x1UL << CAN_F16R1_FB26_Pos)

#define	CAN_F16R1_FB26 CAN_F16R1_FB26_Msk

#define	CAN_F16R1_FB27_Pos (27U)

#define	CAN_F16R1_FB27_Msk (0x1UL << CAN_F16R1_FB27_Pos)

#define	CAN_F16R1_FB27 CAN_F16R1_FB27_Msk

#define	CAN_F16R1_FB28_Pos (28U)

#define	CAN_F16R1_FB28_Msk (0x1UL << CAN_F16R1_FB28_Pos)

#define	CAN_F16R1_FB28 CAN_F16R1_FB28_Msk

#define	CAN_F16R1_FB29_Pos (29U)

#define	CAN_F16R1_FB29_Msk (0x1UL << CAN_F16R1_FB29_Pos)

#define	CAN_F16R1_FB29 CAN_F16R1_FB29_Msk

#define	CAN_F16R1_FB30_Pos (30U)

#define	CAN_F16R1_FB30_Msk (0x1UL << CAN_F16R1_FB30_Pos)

#define	CAN_F16R1_FB30 CAN_F16R1_FB30_Msk

#define	CAN_F16R1_FB31_Pos (31U)

#define	CAN_F16R1_FB31_Msk (0x1UL << CAN_F16R1_FB31_Pos)

#define	CAN_F16R1_FB31 CAN_F16R1_FB31_Msk

#define	CAN_F17R1_FB0_Pos (0U)

#define	CAN_F17R1_FB0_Msk (0x1UL << CAN_F17R1_FB0_Pos)

#define	CAN_F17R1_FB0 CAN_F17R1_FB0_Msk

#define	CAN_F17R1_FB1_Pos (1U)

#define	CAN_F17R1_FB1_Msk (0x1UL << CAN_F17R1_FB1_Pos)

#define	CAN_F17R1_FB1 CAN_F17R1_FB1_Msk

#define	CAN_F17R1_FB2_Pos (2U)

#define	CAN_F17R1_FB2_Msk (0x1UL << CAN_F17R1_FB2_Pos)

#define	CAN_F17R1_FB2 CAN_F17R1_FB2_Msk

#define	CAN_F17R1_FB3_Pos (3U)

#define	CAN_F17R1_FB3_Msk (0x1UL << CAN_F17R1_FB3_Pos)

#define	CAN_F17R1_FB3 CAN_F17R1_FB3_Msk

#define	CAN_F17R1_FB4_Pos (4U)

#define	CAN_F17R1_FB4_Msk (0x1UL << CAN_F17R1_FB4_Pos)

#define	CAN_F17R1_FB4 CAN_F17R1_FB4_Msk

#define	CAN_F17R1_FB5_Pos (5U)

#define	CAN_F17R1_FB5_Msk (0x1UL << CAN_F17R1_FB5_Pos)

#define	CAN_F17R1_FB5 CAN_F17R1_FB5_Msk

#define	CAN_F17R1_FB6_Pos (6U)

#define	CAN_F17R1_FB6_Msk (0x1UL << CAN_F17R1_FB6_Pos)

#define	CAN_F17R1_FB6 CAN_F17R1_FB6_Msk

#define	CAN_F17R1_FB7_Pos (7U)

#define	CAN_F17R1_FB7_Msk (0x1UL << CAN_F17R1_FB7_Pos)

#define	CAN_F17R1_FB7 CAN_F17R1_FB7_Msk

#define	CAN_F17R1_FB8_Pos (8U)

#define	CAN_F17R1_FB8_Msk (0x1UL << CAN_F17R1_FB8_Pos)

#define	CAN_F17R1_FB8 CAN_F17R1_FB8_Msk

#define	CAN_F17R1_FB9_Pos (9U)

#define	CAN_F17R1_FB9_Msk (0x1UL << CAN_F17R1_FB9_Pos)

#define	CAN_F17R1_FB9 CAN_F17R1_FB9_Msk

#define	CAN_F17R1_FB10_Pos (10U)

#define	CAN_F17R1_FB10_Msk (0x1UL << CAN_F17R1_FB10_Pos)

#define	CAN_F17R1_FB10 CAN_F17R1_FB10_Msk

#define	CAN_F17R1_FB11_Pos (11U)

#define	CAN_F17R1_FB11_Msk (0x1UL << CAN_F17R1_FB11_Pos)

#define	CAN_F17R1_FB11 CAN_F17R1_FB11_Msk

#define	CAN_F17R1_FB12_Pos (12U)

#define	CAN_F17R1_FB12_Msk (0x1UL << CAN_F17R1_FB12_Pos)

#define	CAN_F17R1_FB12 CAN_F17R1_FB12_Msk

#define	CAN_F17R1_FB13_Pos (13U)

#define	CAN_F17R1_FB13_Msk (0x1UL << CAN_F17R1_FB13_Pos)

#define	CAN_F17R1_FB13 CAN_F17R1_FB13_Msk

#define	CAN_F17R1_FB14_Pos (14U)

#define	CAN_F17R1_FB14_Msk (0x1UL << CAN_F17R1_FB14_Pos)

#define	CAN_F17R1_FB14 CAN_F17R1_FB14_Msk

#define	CAN_F17R1_FB15_Pos (15U)

#define	CAN_F17R1_FB15_Msk (0x1UL << CAN_F17R1_FB15_Pos)

#define	CAN_F17R1_FB15 CAN_F17R1_FB15_Msk

#define	CAN_F17R1_FB16_Pos (16U)

#define	CAN_F17R1_FB16_Msk (0x1UL << CAN_F17R1_FB16_Pos)

#define	CAN_F17R1_FB16 CAN_F17R1_FB16_Msk

#define	CAN_F17R1_FB17_Pos (17U)

#define	CAN_F17R1_FB17_Msk (0x1UL << CAN_F17R1_FB17_Pos)

#define	CAN_F17R1_FB17 CAN_F17R1_FB17_Msk

#define	CAN_F17R1_FB18_Pos (18U)

#define	CAN_F17R1_FB18_Msk (0x1UL << CAN_F17R1_FB18_Pos)

#define	CAN_F17R1_FB18 CAN_F17R1_FB18_Msk

#define	CAN_F17R1_FB19_Pos (19U)

#define	CAN_F17R1_FB19_Msk (0x1UL << CAN_F17R1_FB19_Pos)

#define	CAN_F17R1_FB19 CAN_F17R1_FB19_Msk

#define	CAN_F17R1_FB20_Pos (20U)

#define	CAN_F17R1_FB20_Msk (0x1UL << CAN_F17R1_FB20_Pos)

#define	CAN_F17R1_FB20 CAN_F17R1_FB20_Msk

#define	CAN_F17R1_FB21_Pos (21U)

#define	CAN_F17R1_FB21_Msk (0x1UL << CAN_F17R1_FB21_Pos)

#define	CAN_F17R1_FB21 CAN_F17R1_FB21_Msk

#define	CAN_F17R1_FB22_Pos (22U)

#define	CAN_F17R1_FB22_Msk (0x1UL << CAN_F17R1_FB22_Pos)

#define	CAN_F17R1_FB22 CAN_F17R1_FB22_Msk

#define	CAN_F17R1_FB23_Pos (23U)

#define	CAN_F17R1_FB23_Msk (0x1UL << CAN_F17R1_FB23_Pos)

#define	CAN_F17R1_FB23 CAN_F17R1_FB23_Msk

#define	CAN_F17R1_FB24_Pos (24U)

#define	CAN_F17R1_FB24_Msk (0x1UL << CAN_F17R1_FB24_Pos)

#define	CAN_F17R1_FB24 CAN_F17R1_FB24_Msk

#define	CAN_F17R1_FB25_Pos (25U)

#define	CAN_F17R1_FB25_Msk (0x1UL << CAN_F17R1_FB25_Pos)

#define	CAN_F17R1_FB25 CAN_F17R1_FB25_Msk

#define	CAN_F17R1_FB26_Pos (26U)

#define	CAN_F17R1_FB26_Msk (0x1UL << CAN_F17R1_FB26_Pos)

#define	CAN_F17R1_FB26 CAN_F17R1_FB26_Msk

#define	CAN_F17R1_FB27_Pos (27U)

#define	CAN_F17R1_FB27_Msk (0x1UL << CAN_F17R1_FB27_Pos)

#define	CAN_F17R1_FB27 CAN_F17R1_FB27_Msk

#define	CAN_F17R1_FB28_Pos (28U)

#define	CAN_F17R1_FB28_Msk (0x1UL << CAN_F17R1_FB28_Pos)

#define	CAN_F17R1_FB28 CAN_F17R1_FB28_Msk

#define	CAN_F17R1_FB29_Pos (29U)

#define	CAN_F17R1_FB29_Msk (0x1UL << CAN_F17R1_FB29_Pos)

#define	CAN_F17R1_FB29 CAN_F17R1_FB29_Msk

#define	CAN_F17R1_FB30_Pos (30U)

#define	CAN_F17R1_FB30_Msk (0x1UL << CAN_F17R1_FB30_Pos)

#define	CAN_F17R1_FB30 CAN_F17R1_FB30_Msk

#define	CAN_F17R1_FB31_Pos (31U)

#define	CAN_F17R1_FB31_Msk (0x1UL << CAN_F17R1_FB31_Pos)

#define	CAN_F17R1_FB31 CAN_F17R1_FB31_Msk

#define	CAN_F18R1_FB0_Pos (0U)

#define	CAN_F18R1_FB0_Msk (0x1UL << CAN_F18R1_FB0_Pos)

#define	CAN_F18R1_FB0 CAN_F18R1_FB0_Msk

#define	CAN_F18R1_FB1_Pos (1U)

#define	CAN_F18R1_FB1_Msk (0x1UL << CAN_F18R1_FB1_Pos)

#define	CAN_F18R1_FB1 CAN_F18R1_FB1_Msk

#define	CAN_F18R1_FB2_Pos (2U)

#define	CAN_F18R1_FB2_Msk (0x1UL << CAN_F18R1_FB2_Pos)

#define	CAN_F18R1_FB2 CAN_F18R1_FB2_Msk

#define	CAN_F18R1_FB3_Pos (3U)

#define	CAN_F18R1_FB3_Msk (0x1UL << CAN_F18R1_FB3_Pos)

#define	CAN_F18R1_FB3 CAN_F18R1_FB3_Msk

#define	CAN_F18R1_FB4_Pos (4U)

#define	CAN_F18R1_FB4_Msk (0x1UL << CAN_F18R1_FB4_Pos)

#define	CAN_F18R1_FB4 CAN_F18R1_FB4_Msk

#define	CAN_F18R1_FB5_Pos (5U)

#define	CAN_F18R1_FB5_Msk (0x1UL << CAN_F18R1_FB5_Pos)

#define	CAN_F18R1_FB5 CAN_F18R1_FB5_Msk

#define	CAN_F18R1_FB6_Pos (6U)

#define	CAN_F18R1_FB6_Msk (0x1UL << CAN_F18R1_FB6_Pos)

#define	CAN_F18R1_FB6 CAN_F18R1_FB6_Msk

#define	CAN_F18R1_FB7_Pos (7U)

#define	CAN_F18R1_FB7_Msk (0x1UL << CAN_F18R1_FB7_Pos)

#define	CAN_F18R1_FB7 CAN_F18R1_FB7_Msk

#define	CAN_F18R1_FB8_Pos (8U)

#define	CAN_F18R1_FB8_Msk (0x1UL << CAN_F18R1_FB8_Pos)

#define	CAN_F18R1_FB8 CAN_F18R1_FB8_Msk

#define	CAN_F18R1_FB9_Pos (9U)

#define	CAN_F18R1_FB9_Msk (0x1UL << CAN_F18R1_FB9_Pos)

#define	CAN_F18R1_FB9 CAN_F18R1_FB9_Msk

#define	CAN_F18R1_FB10_Pos (10U)

#define	CAN_F18R1_FB10_Msk (0x1UL << CAN_F18R1_FB10_Pos)

#define	CAN_F18R1_FB10 CAN_F18R1_FB10_Msk

#define	CAN_F18R1_FB11_Pos (11U)

#define	CAN_F18R1_FB11_Msk (0x1UL << CAN_F18R1_FB11_Pos)

#define	CAN_F18R1_FB11 CAN_F18R1_FB11_Msk

#define	CAN_F18R1_FB12_Pos (12U)

#define	CAN_F18R1_FB12_Msk (0x1UL << CAN_F18R1_FB12_Pos)

#define	CAN_F18R1_FB12 CAN_F18R1_FB12_Msk

#define	CAN_F18R1_FB13_Pos (13U)

#define	CAN_F18R1_FB13_Msk (0x1UL << CAN_F18R1_FB13_Pos)

#define	CAN_F18R1_FB13 CAN_F18R1_FB13_Msk

#define	CAN_F18R1_FB14_Pos (14U)

#define	CAN_F18R1_FB14_Msk (0x1UL << CAN_F18R1_FB14_Pos)

#define	CAN_F18R1_FB14 CAN_F18R1_FB14_Msk

#define	CAN_F18R1_FB15_Pos (15U)

#define	CAN_F18R1_FB15_Msk (0x1UL << CAN_F18R1_FB15_Pos)

#define	CAN_F18R1_FB15 CAN_F18R1_FB15_Msk

#define	CAN_F18R1_FB16_Pos (16U)

#define	CAN_F18R1_FB16_Msk (0x1UL << CAN_F18R1_FB16_Pos)

#define	CAN_F18R1_FB16 CAN_F18R1_FB16_Msk

#define	CAN_F18R1_FB17_Pos (17U)

#define	CAN_F18R1_FB17_Msk (0x1UL << CAN_F18R1_FB17_Pos)

#define	CAN_F18R1_FB17 CAN_F18R1_FB17_Msk

#define	CAN_F18R1_FB18_Pos (18U)

#define	CAN_F18R1_FB18_Msk (0x1UL << CAN_F18R1_FB18_Pos)

#define	CAN_F18R1_FB18 CAN_F18R1_FB18_Msk

#define	CAN_F18R1_FB19_Pos (19U)

#define	CAN_F18R1_FB19_Msk (0x1UL << CAN_F18R1_FB19_Pos)

#define	CAN_F18R1_FB19 CAN_F18R1_FB19_Msk

#define	CAN_F18R1_FB20_Pos (20U)

#define	CAN_F18R1_FB20_Msk (0x1UL << CAN_F18R1_FB20_Pos)

#define	CAN_F18R1_FB20 CAN_F18R1_FB20_Msk

#define	CAN_F18R1_FB21_Pos (21U)

#define	CAN_F18R1_FB21_Msk (0x1UL << CAN_F18R1_FB21_Pos)

#define	CAN_F18R1_FB21 CAN_F18R1_FB21_Msk

#define	CAN_F18R1_FB22_Pos (22U)

#define	CAN_F18R1_FB22_Msk (0x1UL << CAN_F18R1_FB22_Pos)

#define	CAN_F18R1_FB22 CAN_F18R1_FB22_Msk

#define	CAN_F18R1_FB23_Pos (23U)

#define	CAN_F18R1_FB23_Msk (0x1UL << CAN_F18R1_FB23_Pos)

#define	CAN_F18R1_FB23 CAN_F18R1_FB23_Msk

#define	CAN_F18R1_FB24_Pos (24U)

#define	CAN_F18R1_FB24_Msk (0x1UL << CAN_F18R1_FB24_Pos)

#define	CAN_F18R1_FB24 CAN_F18R1_FB24_Msk

#define	CAN_F18R1_FB25_Pos (25U)

#define	CAN_F18R1_FB25_Msk (0x1UL << CAN_F18R1_FB25_Pos)

#define	CAN_F18R1_FB25 CAN_F18R1_FB25_Msk

#define	CAN_F18R1_FB26_Pos (26U)

#define	CAN_F18R1_FB26_Msk (0x1UL << CAN_F18R1_FB26_Pos)

#define	CAN_F18R1_FB26 CAN_F18R1_FB26_Msk

#define	CAN_F18R1_FB27_Pos (27U)

#define	CAN_F18R1_FB27_Msk (0x1UL << CAN_F18R1_FB27_Pos)

#define	CAN_F18R1_FB27 CAN_F18R1_FB27_Msk

#define	CAN_F18R1_FB28_Pos (28U)

#define	CAN_F18R1_FB28_Msk (0x1UL << CAN_F18R1_FB28_Pos)

#define	CAN_F18R1_FB28 CAN_F18R1_FB28_Msk

#define	CAN_F18R1_FB29_Pos (29U)

#define	CAN_F18R1_FB29_Msk (0x1UL << CAN_F18R1_FB29_Pos)

#define	CAN_F18R1_FB29 CAN_F18R1_FB29_Msk

#define	CAN_F18R1_FB30_Pos (30U)

#define	CAN_F18R1_FB30_Msk (0x1UL << CAN_F18R1_FB30_Pos)

#define	CAN_F18R1_FB30 CAN_F18R1_FB30_Msk

#define	CAN_F18R1_FB31_Pos (31U)

#define	CAN_F18R1_FB31_Msk (0x1UL << CAN_F18R1_FB31_Pos)

#define	CAN_F18R1_FB31 CAN_F18R1_FB31_Msk

#define	CAN_F19R1_FB0_Pos (0U)

#define	CAN_F19R1_FB0_Msk (0x1UL << CAN_F19R1_FB0_Pos)

#define	CAN_F19R1_FB0 CAN_F19R1_FB0_Msk

#define	CAN_F19R1_FB1_Pos (1U)

#define	CAN_F19R1_FB1_Msk (0x1UL << CAN_F19R1_FB1_Pos)

#define	CAN_F19R1_FB1 CAN_F19R1_FB1_Msk

#define	CAN_F19R1_FB2_Pos (2U)

#define	CAN_F19R1_FB2_Msk (0x1UL << CAN_F19R1_FB2_Pos)

#define	CAN_F19R1_FB2 CAN_F19R1_FB2_Msk

#define	CAN_F19R1_FB3_Pos (3U)

#define	CAN_F19R1_FB3_Msk (0x1UL << CAN_F19R1_FB3_Pos)

#define	CAN_F19R1_FB3 CAN_F19R1_FB3_Msk

#define	CAN_F19R1_FB4_Pos (4U)

#define	CAN_F19R1_FB4_Msk (0x1UL << CAN_F19R1_FB4_Pos)

#define	CAN_F19R1_FB4 CAN_F19R1_FB4_Msk

#define	CAN_F19R1_FB5_Pos (5U)

#define	CAN_F19R1_FB5_Msk (0x1UL << CAN_F19R1_FB5_Pos)

#define	CAN_F19R1_FB5 CAN_F19R1_FB5_Msk

#define	CAN_F19R1_FB6_Pos (6U)

#define	CAN_F19R1_FB6_Msk (0x1UL << CAN_F19R1_FB6_Pos)

#define	CAN_F19R1_FB6 CAN_F19R1_FB6_Msk

#define	CAN_F19R1_FB7_Pos (7U)

#define	CAN_F19R1_FB7_Msk (0x1UL << CAN_F19R1_FB7_Pos)

#define	CAN_F19R1_FB7 CAN_F19R1_FB7_Msk

#define	CAN_F19R1_FB8_Pos (8U)

#define	CAN_F19R1_FB8_Msk (0x1UL << CAN_F19R1_FB8_Pos)

#define	CAN_F19R1_FB8 CAN_F19R1_FB8_Msk

#define	CAN_F19R1_FB9_Pos (9U)

#define	CAN_F19R1_FB9_Msk (0x1UL << CAN_F19R1_FB9_Pos)

#define	CAN_F19R1_FB9 CAN_F19R1_FB9_Msk

#define	CAN_F19R1_FB10_Pos (10U)

#define	CAN_F19R1_FB10_Msk (0x1UL << CAN_F19R1_FB10_Pos)

#define	CAN_F19R1_FB10 CAN_F19R1_FB10_Msk

#define	CAN_F19R1_FB11_Pos (11U)

#define	CAN_F19R1_FB11_Msk (0x1UL << CAN_F19R1_FB11_Pos)

#define	CAN_F19R1_FB11 CAN_F19R1_FB11_Msk

#define	CAN_F19R1_FB12_Pos (12U)

#define	CAN_F19R1_FB12_Msk (0x1UL << CAN_F19R1_FB12_Pos)

#define	CAN_F19R1_FB12 CAN_F19R1_FB12_Msk

#define	CAN_F19R1_FB13_Pos (13U)

#define	CAN_F19R1_FB13_Msk (0x1UL << CAN_F19R1_FB13_Pos)

#define	CAN_F19R1_FB13 CAN_F19R1_FB13_Msk

#define	CAN_F19R1_FB14_Pos (14U)

#define	CAN_F19R1_FB14_Msk (0x1UL << CAN_F19R1_FB14_Pos)

#define	CAN_F19R1_FB14 CAN_F19R1_FB14_Msk

#define	CAN_F19R1_FB15_Pos (15U)

#define	CAN_F19R1_FB15_Msk (0x1UL << CAN_F19R1_FB15_Pos)

#define	CAN_F19R1_FB15 CAN_F19R1_FB15_Msk

#define	CAN_F19R1_FB16_Pos (16U)

#define	CAN_F19R1_FB16_Msk (0x1UL << CAN_F19R1_FB16_Pos)

#define	CAN_F19R1_FB16 CAN_F19R1_FB16_Msk

#define	CAN_F19R1_FB17_Pos (17U)

#define	CAN_F19R1_FB17_Msk (0x1UL << CAN_F19R1_FB17_Pos)

#define	CAN_F19R1_FB17 CAN_F19R1_FB17_Msk

#define	CAN_F19R1_FB18_Pos (18U)

#define	CAN_F19R1_FB18_Msk (0x1UL << CAN_F19R1_FB18_Pos)

#define	CAN_F19R1_FB18 CAN_F19R1_FB18_Msk

#define	CAN_F19R1_FB19_Pos (19U)

#define	CAN_F19R1_FB19_Msk (0x1UL << CAN_F19R1_FB19_Pos)

#define	CAN_F19R1_FB19 CAN_F19R1_FB19_Msk

#define	CAN_F19R1_FB20_Pos (20U)

#define	CAN_F19R1_FB20_Msk (0x1UL << CAN_F19R1_FB20_Pos)

#define	CAN_F19R1_FB20 CAN_F19R1_FB20_Msk

#define	CAN_F19R1_FB21_Pos (21U)

#define	CAN_F19R1_FB21_Msk (0x1UL << CAN_F19R1_FB21_Pos)

#define	CAN_F19R1_FB21 CAN_F19R1_FB21_Msk

#define	CAN_F19R1_FB22_Pos (22U)

#define	CAN_F19R1_FB22_Msk (0x1UL << CAN_F19R1_FB22_Pos)

#define	CAN_F19R1_FB22 CAN_F19R1_FB22_Msk

#define	CAN_F19R1_FB23_Pos (23U)

#define	CAN_F19R1_FB23_Msk (0x1UL << CAN_F19R1_FB23_Pos)

#define	CAN_F19R1_FB23 CAN_F19R1_FB23_Msk

#define	CAN_F19R1_FB24_Pos (24U)

#define	CAN_F19R1_FB24_Msk (0x1UL << CAN_F19R1_FB24_Pos)

#define	CAN_F19R1_FB24 CAN_F19R1_FB24_Msk

#define	CAN_F19R1_FB25_Pos (25U)

#define	CAN_F19R1_FB25_Msk (0x1UL << CAN_F19R1_FB25_Pos)

#define	CAN_F19R1_FB25 CAN_F19R1_FB25_Msk

#define	CAN_F19R1_FB26_Pos (26U)

#define	CAN_F19R1_FB26_Msk (0x1UL << CAN_F19R1_FB26_Pos)

#define	CAN_F19R1_FB26 CAN_F19R1_FB26_Msk

#define	CAN_F19R1_FB27_Pos (27U)

#define	CAN_F19R1_FB27_Msk (0x1UL << CAN_F19R1_FB27_Pos)

#define	CAN_F19R1_FB27 CAN_F19R1_FB27_Msk

#define	CAN_F19R1_FB28_Pos (28U)

#define	CAN_F19R1_FB28_Msk (0x1UL << CAN_F19R1_FB28_Pos)

#define	CAN_F19R1_FB28 CAN_F19R1_FB28_Msk

#define	CAN_F19R1_FB29_Pos (29U)

#define	CAN_F19R1_FB29_Msk (0x1UL << CAN_F19R1_FB29_Pos)

#define	CAN_F19R1_FB29 CAN_F19R1_FB29_Msk

#define	CAN_F19R1_FB30_Pos (30U)

#define	CAN_F19R1_FB30_Msk (0x1UL << CAN_F19R1_FB30_Pos)

#define	CAN_F19R1_FB30 CAN_F19R1_FB30_Msk

#define	CAN_F19R1_FB31_Pos (31U)

#define	CAN_F19R1_FB31_Msk (0x1UL << CAN_F19R1_FB31_Pos)

#define	CAN_F19R1_FB31 CAN_F19R1_FB31_Msk

#define	CAN_F20R1_FB0_Pos (0U)

#define	CAN_F20R1_FB0_Msk (0x1UL << CAN_F20R1_FB0_Pos)

#define	CAN_F20R1_FB0 CAN_F20R1_FB0_Msk

#define	CAN_F20R1_FB1_Pos (1U)

#define	CAN_F20R1_FB1_Msk (0x1UL << CAN_F20R1_FB1_Pos)

#define	CAN_F20R1_FB1 CAN_F20R1_FB1_Msk

#define	CAN_F20R1_FB2_Pos (2U)

#define	CAN_F20R1_FB2_Msk (0x1UL << CAN_F20R1_FB2_Pos)

#define	CAN_F20R1_FB2 CAN_F20R1_FB2_Msk

#define	CAN_F20R1_FB3_Pos (3U)

#define	CAN_F20R1_FB3_Msk (0x1UL << CAN_F20R1_FB3_Pos)

#define	CAN_F20R1_FB3 CAN_F20R1_FB3_Msk

#define	CAN_F20R1_FB4_Pos (4U)

#define	CAN_F20R1_FB4_Msk (0x1UL << CAN_F20R1_FB4_Pos)

#define	CAN_F20R1_FB4 CAN_F20R1_FB4_Msk

#define	CAN_F20R1_FB5_Pos (5U)

#define	CAN_F20R1_FB5_Msk (0x1UL << CAN_F20R1_FB5_Pos)

#define	CAN_F20R1_FB5 CAN_F20R1_FB5_Msk

#define	CAN_F20R1_FB6_Pos (6U)

#define	CAN_F20R1_FB6_Msk (0x1UL << CAN_F20R1_FB6_Pos)

#define	CAN_F20R1_FB6 CAN_F20R1_FB6_Msk

#define	CAN_F20R1_FB7_Pos (7U)

#define	CAN_F20R1_FB7_Msk (0x1UL << CAN_F20R1_FB7_Pos)

#define	CAN_F20R1_FB7 CAN_F20R1_FB7_Msk

#define	CAN_F20R1_FB8_Pos (8U)

#define	CAN_F20R1_FB8_Msk (0x1UL << CAN_F20R1_FB8_Pos)

#define	CAN_F20R1_FB8 CAN_F20R1_FB8_Msk

#define	CAN_F20R1_FB9_Pos (9U)

#define	CAN_F20R1_FB9_Msk (0x1UL << CAN_F20R1_FB9_Pos)

#define	CAN_F20R1_FB9 CAN_F20R1_FB9_Msk

#define	CAN_F20R1_FB10_Pos (10U)

#define	CAN_F20R1_FB10_Msk (0x1UL << CAN_F20R1_FB10_Pos)

#define	CAN_F20R1_FB10 CAN_F20R1_FB10_Msk

#define	CAN_F20R1_FB11_Pos (11U)

#define	CAN_F20R1_FB11_Msk (0x1UL << CAN_F20R1_FB11_Pos)

#define	CAN_F20R1_FB11 CAN_F20R1_FB11_Msk

#define	CAN_F20R1_FB12_Pos (12U)

#define	CAN_F20R1_FB12_Msk (0x1UL << CAN_F20R1_FB12_Pos)

#define	CAN_F20R1_FB12 CAN_F20R1_FB12_Msk

#define	CAN_F20R1_FB13_Pos (13U)

#define	CAN_F20R1_FB13_Msk (0x1UL << CAN_F20R1_FB13_Pos)

#define	CAN_F20R1_FB13 CAN_F20R1_FB13_Msk

#define	CAN_F20R1_FB14_Pos (14U)

#define	CAN_F20R1_FB14_Msk (0x1UL << CAN_F20R1_FB14_Pos)

#define	CAN_F20R1_FB14 CAN_F20R1_FB14_Msk

#define	CAN_F20R1_FB15_Pos (15U)

#define	CAN_F20R1_FB15_Msk (0x1UL << CAN_F20R1_FB15_Pos)

#define	CAN_F20R1_FB15 CAN_F20R1_FB15_Msk

#define	CAN_F20R1_FB16_Pos (16U)

#define	CAN_F20R1_FB16_Msk (0x1UL << CAN_F20R1_FB16_Pos)

#define	CAN_F20R1_FB16 CAN_F20R1_FB16_Msk

#define	CAN_F20R1_FB17_Pos (17U)

#define	CAN_F20R1_FB17_Msk (0x1UL << CAN_F20R1_FB17_Pos)

#define	CAN_F20R1_FB17 CAN_F20R1_FB17_Msk

#define	CAN_F20R1_FB18_Pos (18U)

#define	CAN_F20R1_FB18_Msk (0x1UL << CAN_F20R1_FB18_Pos)

#define	CAN_F20R1_FB18 CAN_F20R1_FB18_Msk

#define	CAN_F20R1_FB19_Pos (19U)

#define	CAN_F20R1_FB19_Msk (0x1UL << CAN_F20R1_FB19_Pos)

#define	CAN_F20R1_FB19 CAN_F20R1_FB19_Msk

#define	CAN_F20R1_FB20_Pos (20U)

#define	CAN_F20R1_FB20_Msk (0x1UL << CAN_F20R1_FB20_Pos)

#define	CAN_F20R1_FB20 CAN_F20R1_FB20_Msk

#define	CAN_F20R1_FB21_Pos (21U)

#define	CAN_F20R1_FB21_Msk (0x1UL << CAN_F20R1_FB21_Pos)

#define	CAN_F20R1_FB21 CAN_F20R1_FB21_Msk

#define	CAN_F20R1_FB22_Pos (22U)

#define	CAN_F20R1_FB22_Msk (0x1UL << CAN_F20R1_FB22_Pos)

#define	CAN_F20R1_FB22 CAN_F20R1_FB22_Msk

#define	CAN_F20R1_FB23_Pos (23U)

#define	CAN_F20R1_FB23_Msk (0x1UL << CAN_F20R1_FB23_Pos)

#define	CAN_F20R1_FB23 CAN_F20R1_FB23_Msk

#define	CAN_F20R1_FB24_Pos (24U)

#define	CAN_F20R1_FB24_Msk (0x1UL << CAN_F20R1_FB24_Pos)

#define	CAN_F20R1_FB24 CAN_F20R1_FB24_Msk

#define	CAN_F20R1_FB25_Pos (25U)

#define	CAN_F20R1_FB25_Msk (0x1UL << CAN_F20R1_FB25_Pos)

#define	CAN_F20R1_FB25 CAN_F20R1_FB25_Msk

#define	CAN_F20R1_FB26_Pos (26U)

#define	CAN_F20R1_FB26_Msk (0x1UL << CAN_F20R1_FB26_Pos)

#define	CAN_F20R1_FB26 CAN_F20R1_FB26_Msk

#define	CAN_F20R1_FB27_Pos (27U)

#define	CAN_F20R1_FB27_Msk (0x1UL << CAN_F20R1_FB27_Pos)

#define	CAN_F20R1_FB27 CAN_F20R1_FB27_Msk

#define	CAN_F20R1_FB28_Pos (28U)

#define	CAN_F20R1_FB28_Msk (0x1UL << CAN_F20R1_FB28_Pos)

#define	CAN_F20R1_FB28 CAN_F20R1_FB28_Msk

#define	CAN_F20R1_FB29_Pos (29U)

#define	CAN_F20R1_FB29_Msk (0x1UL << CAN_F20R1_FB29_Pos)

#define	CAN_F20R1_FB29 CAN_F20R1_FB29_Msk

#define	CAN_F20R1_FB30_Pos (30U)

#define	CAN_F20R1_FB30_Msk (0x1UL << CAN_F20R1_FB30_Pos)

#define	CAN_F20R1_FB30 CAN_F20R1_FB30_Msk

#define	CAN_F20R1_FB31_Pos (31U)

#define	CAN_F20R1_FB31_Msk (0x1UL << CAN_F20R1_FB31_Pos)

#define	CAN_F20R1_FB31 CAN_F20R1_FB31_Msk

#define	CAN_F21R1_FB0_Pos (0U)

#define	CAN_F21R1_FB0_Msk (0x1UL << CAN_F21R1_FB0_Pos)

#define	CAN_F21R1_FB0 CAN_F21R1_FB0_Msk

#define	CAN_F21R1_FB1_Pos (1U)

#define	CAN_F21R1_FB1_Msk (0x1UL << CAN_F21R1_FB1_Pos)

#define	CAN_F21R1_FB1 CAN_F21R1_FB1_Msk

#define	CAN_F21R1_FB2_Pos (2U)

#define	CAN_F21R1_FB2_Msk (0x1UL << CAN_F21R1_FB2_Pos)

#define	CAN_F21R1_FB2 CAN_F21R1_FB2_Msk

#define	CAN_F21R1_FB3_Pos (3U)

#define	CAN_F21R1_FB3_Msk (0x1UL << CAN_F21R1_FB3_Pos)

#define	CAN_F21R1_FB3 CAN_F21R1_FB3_Msk

#define	CAN_F21R1_FB4_Pos (4U)

#define	CAN_F21R1_FB4_Msk (0x1UL << CAN_F21R1_FB4_Pos)

#define	CAN_F21R1_FB4 CAN_F21R1_FB4_Msk

#define	CAN_F21R1_FB5_Pos (5U)

#define	CAN_F21R1_FB5_Msk (0x1UL << CAN_F21R1_FB5_Pos)

#define	CAN_F21R1_FB5 CAN_F21R1_FB5_Msk

#define	CAN_F21R1_FB6_Pos (6U)

#define	CAN_F21R1_FB6_Msk (0x1UL << CAN_F21R1_FB6_Pos)

#define	CAN_F21R1_FB6 CAN_F21R1_FB6_Msk

#define	CAN_F21R1_FB7_Pos (7U)

#define	CAN_F21R1_FB7_Msk (0x1UL << CAN_F21R1_FB7_Pos)

#define	CAN_F21R1_FB7 CAN_F21R1_FB7_Msk

#define	CAN_F21R1_FB8_Pos (8U)

#define	CAN_F21R1_FB8_Msk (0x1UL << CAN_F21R1_FB8_Pos)

#define	CAN_F21R1_FB8 CAN_F21R1_FB8_Msk

#define	CAN_F21R1_FB9_Pos (9U)

#define	CAN_F21R1_FB9_Msk (0x1UL << CAN_F21R1_FB9_Pos)

#define	CAN_F21R1_FB9 CAN_F21R1_FB9_Msk

#define	CAN_F21R1_FB10_Pos (10U)

#define	CAN_F21R1_FB10_Msk (0x1UL << CAN_F21R1_FB10_Pos)

#define	CAN_F21R1_FB10 CAN_F21R1_FB10_Msk

#define	CAN_F21R1_FB11_Pos (11U)

#define	CAN_F21R1_FB11_Msk (0x1UL << CAN_F21R1_FB11_Pos)

#define	CAN_F21R1_FB11 CAN_F21R1_FB11_Msk

#define	CAN_F21R1_FB12_Pos (12U)

#define	CAN_F21R1_FB12_Msk (0x1UL << CAN_F21R1_FB12_Pos)

#define	CAN_F21R1_FB12 CAN_F21R1_FB12_Msk

#define	CAN_F21R1_FB13_Pos (13U)

#define	CAN_F21R1_FB13_Msk (0x1UL << CAN_F21R1_FB13_Pos)

#define	CAN_F21R1_FB13 CAN_F21R1_FB13_Msk

#define	CAN_F21R1_FB14_Pos (14U)

#define	CAN_F21R1_FB14_Msk (0x1UL << CAN_F21R1_FB14_Pos)

#define	CAN_F21R1_FB14 CAN_F21R1_FB14_Msk

#define	CAN_F21R1_FB15_Pos (15U)

#define	CAN_F21R1_FB15_Msk (0x1UL << CAN_F21R1_FB15_Pos)

#define	CAN_F21R1_FB15 CAN_F21R1_FB15_Msk

#define	CAN_F21R1_FB16_Pos (16U)

#define	CAN_F21R1_FB16_Msk (0x1UL << CAN_F21R1_FB16_Pos)

#define	CAN_F21R1_FB16 CAN_F21R1_FB16_Msk

#define	CAN_F21R1_FB17_Pos (17U)

#define	CAN_F21R1_FB17_Msk (0x1UL << CAN_F21R1_FB17_Pos)

#define	CAN_F21R1_FB17 CAN_F21R1_FB17_Msk

#define	CAN_F21R1_FB18_Pos (18U)

#define	CAN_F21R1_FB18_Msk (0x1UL << CAN_F21R1_FB18_Pos)

#define	CAN_F21R1_FB18 CAN_F21R1_FB18_Msk

#define	CAN_F21R1_FB19_Pos (19U)

#define	CAN_F21R1_FB19_Msk (0x1UL << CAN_F21R1_FB19_Pos)

#define	CAN_F21R1_FB19 CAN_F21R1_FB19_Msk

#define	CAN_F21R1_FB20_Pos (20U)

#define	CAN_F21R1_FB20_Msk (0x1UL << CAN_F21R1_FB20_Pos)

#define	CAN_F21R1_FB20 CAN_F21R1_FB20_Msk

#define	CAN_F21R1_FB21_Pos (21U)

#define	CAN_F21R1_FB21_Msk (0x1UL << CAN_F21R1_FB21_Pos)

#define	CAN_F21R1_FB21 CAN_F21R1_FB21_Msk

#define	CAN_F21R1_FB22_Pos (22U)

#define	CAN_F21R1_FB22_Msk (0x1UL << CAN_F21R1_FB22_Pos)

#define	CAN_F21R1_FB22 CAN_F21R1_FB22_Msk

#define	CAN_F21R1_FB23_Pos (23U)

#define	CAN_F21R1_FB23_Msk (0x1UL << CAN_F21R1_FB23_Pos)

#define	CAN_F21R1_FB23 CAN_F21R1_FB23_Msk

#define	CAN_F21R1_FB24_Pos (24U)

#define	CAN_F21R1_FB24_Msk (0x1UL << CAN_F21R1_FB24_Pos)

#define	CAN_F21R1_FB24 CAN_F21R1_FB24_Msk

#define	CAN_F21R1_FB25_Pos (25U)

#define	CAN_F21R1_FB25_Msk (0x1UL << CAN_F21R1_FB25_Pos)

#define	CAN_F21R1_FB25 CAN_F21R1_FB25_Msk

#define	CAN_F21R1_FB26_Pos (26U)

#define	CAN_F21R1_FB26_Msk (0x1UL << CAN_F21R1_FB26_Pos)

#define	CAN_F21R1_FB26 CAN_F21R1_FB26_Msk

#define	CAN_F21R1_FB27_Pos (27U)

#define	CAN_F21R1_FB27_Msk (0x1UL << CAN_F21R1_FB27_Pos)

#define	CAN_F21R1_FB27 CAN_F21R1_FB27_Msk

#define	CAN_F21R1_FB28_Pos (28U)

#define	CAN_F21R1_FB28_Msk (0x1UL << CAN_F21R1_FB28_Pos)

#define	CAN_F21R1_FB28 CAN_F21R1_FB28_Msk

#define	CAN_F21R1_FB29_Pos (29U)

#define	CAN_F21R1_FB29_Msk (0x1UL << CAN_F21R1_FB29_Pos)

#define	CAN_F21R1_FB29 CAN_F21R1_FB29_Msk

#define	CAN_F21R1_FB30_Pos (30U)

#define	CAN_F21R1_FB30_Msk (0x1UL << CAN_F21R1_FB30_Pos)

#define	CAN_F21R1_FB30 CAN_F21R1_FB30_Msk

#define	CAN_F21R1_FB31_Pos (31U)

#define	CAN_F21R1_FB31_Msk (0x1UL << CAN_F21R1_FB31_Pos)

#define	CAN_F21R1_FB31 CAN_F21R1_FB31_Msk

#define	CAN_F22R1_FB0_Pos (0U)

#define	CAN_F22R1_FB0_Msk (0x1UL << CAN_F22R1_FB0_Pos)

#define	CAN_F22R1_FB0 CAN_F22R1_FB0_Msk

#define	CAN_F22R1_FB1_Pos (1U)

#define	CAN_F22R1_FB1_Msk (0x1UL << CAN_F22R1_FB1_Pos)

#define	CAN_F22R1_FB1 CAN_F22R1_FB1_Msk

#define	CAN_F22R1_FB2_Pos (2U)

#define	CAN_F22R1_FB2_Msk (0x1UL << CAN_F22R1_FB2_Pos)

#define	CAN_F22R1_FB2 CAN_F22R1_FB2_Msk

#define	CAN_F22R1_FB3_Pos (3U)

#define	CAN_F22R1_FB3_Msk (0x1UL << CAN_F22R1_FB3_Pos)

#define	CAN_F22R1_FB3 CAN_F22R1_FB3_Msk

#define	CAN_F22R1_FB4_Pos (4U)

#define	CAN_F22R1_FB4_Msk (0x1UL << CAN_F22R1_FB4_Pos)

#define	CAN_F22R1_FB4 CAN_F22R1_FB4_Msk

#define	CAN_F22R1_FB5_Pos (5U)

#define	CAN_F22R1_FB5_Msk (0x1UL << CAN_F22R1_FB5_Pos)

#define	CAN_F22R1_FB5 CAN_F22R1_FB5_Msk

#define	CAN_F22R1_FB6_Pos (6U)

#define	CAN_F22R1_FB6_Msk (0x1UL << CAN_F22R1_FB6_Pos)

#define	CAN_F22R1_FB6 CAN_F22R1_FB6_Msk

#define	CAN_F22R1_FB7_Pos (7U)

#define	CAN_F22R1_FB7_Msk (0x1UL << CAN_F22R1_FB7_Pos)

#define	CAN_F22R1_FB7 CAN_F22R1_FB7_Msk

#define	CAN_F22R1_FB8_Pos (8U)

#define	CAN_F22R1_FB8_Msk (0x1UL << CAN_F22R1_FB8_Pos)

#define	CAN_F22R1_FB8 CAN_F22R1_FB8_Msk

#define	CAN_F22R1_FB9_Pos (9U)

#define	CAN_F22R1_FB9_Msk (0x1UL << CAN_F22R1_FB9_Pos)

#define	CAN_F22R1_FB9 CAN_F22R1_FB9_Msk

#define	CAN_F22R1_FB10_Pos (10U)

#define	CAN_F22R1_FB10_Msk (0x1UL << CAN_F22R1_FB10_Pos)

#define	CAN_F22R1_FB10 CAN_F22R1_FB10_Msk

#define	CAN_F22R1_FB11_Pos (11U)

#define	CAN_F22R1_FB11_Msk (0x1UL << CAN_F22R1_FB11_Pos)

#define	CAN_F22R1_FB11 CAN_F22R1_FB11_Msk

#define	CAN_F22R1_FB12_Pos (12U)

#define	CAN_F22R1_FB12_Msk (0x1UL << CAN_F22R1_FB12_Pos)

#define	CAN_F22R1_FB12 CAN_F22R1_FB12_Msk

#define	CAN_F22R1_FB13_Pos (13U)

#define	CAN_F22R1_FB13_Msk (0x1UL << CAN_F22R1_FB13_Pos)

#define	CAN_F22R1_FB13 CAN_F22R1_FB13_Msk

#define	CAN_F22R1_FB14_Pos (14U)

#define	CAN_F22R1_FB14_Msk (0x1UL << CAN_F22R1_FB14_Pos)

#define	CAN_F22R1_FB14 CAN_F22R1_FB14_Msk

#define	CAN_F22R1_FB15_Pos (15U)

#define	CAN_F22R1_FB15_Msk (0x1UL << CAN_F22R1_FB15_Pos)

#define	CAN_F22R1_FB15 CAN_F22R1_FB15_Msk

#define	CAN_F22R1_FB16_Pos (16U)

#define	CAN_F22R1_FB16_Msk (0x1UL << CAN_F22R1_FB16_Pos)

#define	CAN_F22R1_FB16 CAN_F22R1_FB16_Msk

#define	CAN_F22R1_FB17_Pos (17U)

#define	CAN_F22R1_FB17_Msk (0x1UL << CAN_F22R1_FB17_Pos)

#define	CAN_F22R1_FB17 CAN_F22R1_FB17_Msk

#define	CAN_F22R1_FB18_Pos (18U)

#define	CAN_F22R1_FB18_Msk (0x1UL << CAN_F22R1_FB18_Pos)

#define	CAN_F22R1_FB18 CAN_F22R1_FB18_Msk

#define	CAN_F22R1_FB19_Pos (19U)

#define	CAN_F22R1_FB19_Msk (0x1UL << CAN_F22R1_FB19_Pos)

#define	CAN_F22R1_FB19 CAN_F22R1_FB19_Msk

#define	CAN_F22R1_FB20_Pos (20U)

#define	CAN_F22R1_FB20_Msk (0x1UL << CAN_F22R1_FB20_Pos)

#define	CAN_F22R1_FB20 CAN_F22R1_FB20_Msk

#define	CAN_F22R1_FB21_Pos (21U)

#define	CAN_F22R1_FB21_Msk (0x1UL << CAN_F22R1_FB21_Pos)

#define	CAN_F22R1_FB21 CAN_F22R1_FB21_Msk

#define	CAN_F22R1_FB22_Pos (22U)

#define	CAN_F22R1_FB22_Msk (0x1UL << CAN_F22R1_FB22_Pos)

#define	CAN_F22R1_FB22 CAN_F22R1_FB22_Msk

#define	CAN_F22R1_FB23_Pos (23U)

#define	CAN_F22R1_FB23_Msk (0x1UL << CAN_F22R1_FB23_Pos)

#define	CAN_F22R1_FB23 CAN_F22R1_FB23_Msk

#define	CAN_F22R1_FB24_Pos (24U)

#define	CAN_F22R1_FB24_Msk (0x1UL << CAN_F22R1_FB24_Pos)

#define	CAN_F22R1_FB24 CAN_F22R1_FB24_Msk

#define	CAN_F22R1_FB25_Pos (25U)

#define	CAN_F22R1_FB25_Msk (0x1UL << CAN_F22R1_FB25_Pos)

#define	CAN_F22R1_FB25 CAN_F22R1_FB25_Msk

#define	CAN_F22R1_FB26_Pos (26U)

#define	CAN_F22R1_FB26_Msk (0x1UL << CAN_F22R1_FB26_Pos)

#define	CAN_F22R1_FB26 CAN_F22R1_FB26_Msk

#define	CAN_F22R1_FB27_Pos (27U)

#define	CAN_F22R1_FB27_Msk (0x1UL << CAN_F22R1_FB27_Pos)

#define	CAN_F22R1_FB27 CAN_F22R1_FB27_Msk

#define	CAN_F22R1_FB28_Pos (28U)

#define	CAN_F22R1_FB28_Msk (0x1UL << CAN_F22R1_FB28_Pos)

#define	CAN_F22R1_FB28 CAN_F22R1_FB28_Msk

#define	CAN_F22R1_FB29_Pos (29U)

#define	CAN_F22R1_FB29_Msk (0x1UL << CAN_F22R1_FB29_Pos)

#define	CAN_F22R1_FB29 CAN_F22R1_FB29_Msk

#define	CAN_F22R1_FB30_Pos (30U)

#define	CAN_F22R1_FB30_Msk (0x1UL << CAN_F22R1_FB30_Pos)

#define	CAN_F22R1_FB30 CAN_F22R1_FB30_Msk

#define	CAN_F22R1_FB31_Pos (31U)

#define	CAN_F22R1_FB31_Msk (0x1UL << CAN_F22R1_FB31_Pos)

#define	CAN_F22R1_FB31 CAN_F22R1_FB31_Msk

#define	CAN_F23R1_FB0_Pos (0U)

#define	CAN_F23R1_FB0_Msk (0x1UL << CAN_F23R1_FB0_Pos)

#define	CAN_F23R1_FB0 CAN_F23R1_FB0_Msk

#define	CAN_F23R1_FB1_Pos (1U)

#define	CAN_F23R1_FB1_Msk (0x1UL << CAN_F23R1_FB1_Pos)

#define	CAN_F23R1_FB1 CAN_F23R1_FB1_Msk

#define	CAN_F23R1_FB2_Pos (2U)

#define	CAN_F23R1_FB2_Msk (0x1UL << CAN_F23R1_FB2_Pos)

#define	CAN_F23R1_FB2 CAN_F23R1_FB2_Msk

#define	CAN_F23R1_FB3_Pos (3U)

#define	CAN_F23R1_FB3_Msk (0x1UL << CAN_F23R1_FB3_Pos)

#define	CAN_F23R1_FB3 CAN_F23R1_FB3_Msk

#define	CAN_F23R1_FB4_Pos (4U)

#define	CAN_F23R1_FB4_Msk (0x1UL << CAN_F23R1_FB4_Pos)

#define	CAN_F23R1_FB4 CAN_F23R1_FB4_Msk

#define	CAN_F23R1_FB5_Pos (5U)

#define	CAN_F23R1_FB5_Msk (0x1UL << CAN_F23R1_FB5_Pos)

#define	CAN_F23R1_FB5 CAN_F23R1_FB5_Msk

#define	CAN_F23R1_FB6_Pos (6U)

#define	CAN_F23R1_FB6_Msk (0x1UL << CAN_F23R1_FB6_Pos)

#define	CAN_F23R1_FB6 CAN_F23R1_FB6_Msk

#define	CAN_F23R1_FB7_Pos (7U)

#define	CAN_F23R1_FB7_Msk (0x1UL << CAN_F23R1_FB7_Pos)

#define	CAN_F23R1_FB7 CAN_F23R1_FB7_Msk

#define	CAN_F23R1_FB8_Pos (8U)

#define	CAN_F23R1_FB8_Msk (0x1UL << CAN_F23R1_FB8_Pos)

#define	CAN_F23R1_FB8 CAN_F23R1_FB8_Msk

#define	CAN_F23R1_FB9_Pos (9U)

#define	CAN_F23R1_FB9_Msk (0x1UL << CAN_F23R1_FB9_Pos)

#define	CAN_F23R1_FB9 CAN_F23R1_FB9_Msk

#define	CAN_F23R1_FB10_Pos (10U)

#define	CAN_F23R1_FB10_Msk (0x1UL << CAN_F23R1_FB10_Pos)

#define	CAN_F23R1_FB10 CAN_F23R1_FB10_Msk

#define	CAN_F23R1_FB11_Pos (11U)

#define	CAN_F23R1_FB11_Msk (0x1UL << CAN_F23R1_FB11_Pos)

#define	CAN_F23R1_FB11 CAN_F23R1_FB11_Msk

#define	CAN_F23R1_FB12_Pos (12U)

#define	CAN_F23R1_FB12_Msk (0x1UL << CAN_F23R1_FB12_Pos)

#define	CAN_F23R1_FB12 CAN_F23R1_FB12_Msk

#define	CAN_F23R1_FB13_Pos (13U)

#define	CAN_F23R1_FB13_Msk (0x1UL << CAN_F23R1_FB13_Pos)

#define	CAN_F23R1_FB13 CAN_F23R1_FB13_Msk

#define	CAN_F23R1_FB14_Pos (14U)

#define	CAN_F23R1_FB14_Msk (0x1UL << CAN_F23R1_FB14_Pos)

#define	CAN_F23R1_FB14 CAN_F23R1_FB14_Msk

#define	CAN_F23R1_FB15_Pos (15U)

#define	CAN_F23R1_FB15_Msk (0x1UL << CAN_F23R1_FB15_Pos)

#define	CAN_F23R1_FB15 CAN_F23R1_FB15_Msk

#define	CAN_F23R1_FB16_Pos (16U)

#define	CAN_F23R1_FB16_Msk (0x1UL << CAN_F23R1_FB16_Pos)

#define	CAN_F23R1_FB16 CAN_F23R1_FB16_Msk

#define	CAN_F23R1_FB17_Pos (17U)

#define	CAN_F23R1_FB17_Msk (0x1UL << CAN_F23R1_FB17_Pos)

#define	CAN_F23R1_FB17 CAN_F23R1_FB17_Msk

#define	CAN_F23R1_FB18_Pos (18U)

#define	CAN_F23R1_FB18_Msk (0x1UL << CAN_F23R1_FB18_Pos)

#define	CAN_F23R1_FB18 CAN_F23R1_FB18_Msk

#define	CAN_F23R1_FB19_Pos (19U)

#define	CAN_F23R1_FB19_Msk (0x1UL << CAN_F23R1_FB19_Pos)

#define	CAN_F23R1_FB19 CAN_F23R1_FB19_Msk

#define	CAN_F23R1_FB20_Pos (20U)

#define	CAN_F23R1_FB20_Msk (0x1UL << CAN_F23R1_FB20_Pos)

#define	CAN_F23R1_FB20 CAN_F23R1_FB20_Msk

#define	CAN_F23R1_FB21_Pos (21U)

#define	CAN_F23R1_FB21_Msk (0x1UL << CAN_F23R1_FB21_Pos)

#define	CAN_F23R1_FB21 CAN_F23R1_FB21_Msk

#define	CAN_F23R1_FB22_Pos (22U)

#define	CAN_F23R1_FB22_Msk (0x1UL << CAN_F23R1_FB22_Pos)

#define	CAN_F23R1_FB22 CAN_F23R1_FB22_Msk

#define	CAN_F23R1_FB23_Pos (23U)

#define	CAN_F23R1_FB23_Msk (0x1UL << CAN_F23R1_FB23_Pos)

#define	CAN_F23R1_FB23 CAN_F23R1_FB23_Msk

#define	CAN_F23R1_FB24_Pos (24U)

#define	CAN_F23R1_FB24_Msk (0x1UL << CAN_F23R1_FB24_Pos)

#define	CAN_F23R1_FB24 CAN_F23R1_FB24_Msk

#define	CAN_F23R1_FB25_Pos (25U)

#define	CAN_F23R1_FB25_Msk (0x1UL << CAN_F23R1_FB25_Pos)

#define	CAN_F23R1_FB25 CAN_F23R1_FB25_Msk

#define	CAN_F23R1_FB26_Pos (26U)

#define	CAN_F23R1_FB26_Msk (0x1UL << CAN_F23R1_FB26_Pos)

#define	CAN_F23R1_FB26 CAN_F23R1_FB26_Msk

#define	CAN_F23R1_FB27_Pos (27U)

#define	CAN_F23R1_FB27_Msk (0x1UL << CAN_F23R1_FB27_Pos)

#define	CAN_F23R1_FB27 CAN_F23R1_FB27_Msk

#define	CAN_F23R1_FB28_Pos (28U)

#define	CAN_F23R1_FB28_Msk (0x1UL << CAN_F23R1_FB28_Pos)

#define	CAN_F23R1_FB28 CAN_F23R1_FB28_Msk

#define	CAN_F23R1_FB29_Pos (29U)

#define	CAN_F23R1_FB29_Msk (0x1UL << CAN_F23R1_FB29_Pos)

#define	CAN_F23R1_FB29 CAN_F23R1_FB29_Msk

#define	CAN_F23R1_FB30_Pos (30U)

#define	CAN_F23R1_FB30_Msk (0x1UL << CAN_F23R1_FB30_Pos)

#define	CAN_F23R1_FB30 CAN_F23R1_FB30_Msk

#define	CAN_F23R1_FB31_Pos (31U)

#define	CAN_F23R1_FB31_Msk (0x1UL << CAN_F23R1_FB31_Pos)

#define	CAN_F23R1_FB31 CAN_F23R1_FB31_Msk

#define	CAN_F24R1_FB0_Pos (0U)

#define	CAN_F24R1_FB0_Msk (0x1UL << CAN_F24R1_FB0_Pos)

#define	CAN_F24R1_FB0 CAN_F24R1_FB0_Msk

#define	CAN_F24R1_FB1_Pos (1U)

#define	CAN_F24R1_FB1_Msk (0x1UL << CAN_F24R1_FB1_Pos)

#define	CAN_F24R1_FB1 CAN_F24R1_FB1_Msk

#define	CAN_F24R1_FB2_Pos (2U)

#define	CAN_F24R1_FB2_Msk (0x1UL << CAN_F24R1_FB2_Pos)

#define	CAN_F24R1_FB2 CAN_F24R1_FB2_Msk

#define	CAN_F24R1_FB3_Pos (3U)

#define	CAN_F24R1_FB3_Msk (0x1UL << CAN_F24R1_FB3_Pos)

#define	CAN_F24R1_FB3 CAN_F24R1_FB3_Msk

#define	CAN_F24R1_FB4_Pos (4U)

#define	CAN_F24R1_FB4_Msk (0x1UL << CAN_F24R1_FB4_Pos)

#define	CAN_F24R1_FB4 CAN_F24R1_FB4_Msk

#define	CAN_F24R1_FB5_Pos (5U)

#define	CAN_F24R1_FB5_Msk (0x1UL << CAN_F24R1_FB5_Pos)

#define	CAN_F24R1_FB5 CAN_F24R1_FB5_Msk

#define	CAN_F24R1_FB6_Pos (6U)

#define	CAN_F24R1_FB6_Msk (0x1UL << CAN_F24R1_FB6_Pos)

#define	CAN_F24R1_FB6 CAN_F24R1_FB6_Msk

#define	CAN_F24R1_FB7_Pos (7U)

#define	CAN_F24R1_FB7_Msk (0x1UL << CAN_F24R1_FB7_Pos)

#define	CAN_F24R1_FB7 CAN_F24R1_FB7_Msk

#define	CAN_F24R1_FB8_Pos (8U)

#define	CAN_F24R1_FB8_Msk (0x1UL << CAN_F24R1_FB8_Pos)

#define	CAN_F24R1_FB8 CAN_F24R1_FB8_Msk

#define	CAN_F24R1_FB9_Pos (9U)

#define	CAN_F24R1_FB9_Msk (0x1UL << CAN_F24R1_FB9_Pos)

#define	CAN_F24R1_FB9 CAN_F24R1_FB9_Msk

#define	CAN_F24R1_FB10_Pos (10U)

#define	CAN_F24R1_FB10_Msk (0x1UL << CAN_F24R1_FB10_Pos)

#define	CAN_F24R1_FB10 CAN_F24R1_FB10_Msk

#define	CAN_F24R1_FB11_Pos (11U)

#define	CAN_F24R1_FB11_Msk (0x1UL << CAN_F24R1_FB11_Pos)

#define	CAN_F24R1_FB11 CAN_F24R1_FB11_Msk

#define	CAN_F24R1_FB12_Pos (12U)

#define	CAN_F24R1_FB12_Msk (0x1UL << CAN_F24R1_FB12_Pos)

#define	CAN_F24R1_FB12 CAN_F24R1_FB12_Msk

#define	CAN_F24R1_FB13_Pos (13U)

#define	CAN_F24R1_FB13_Msk (0x1UL << CAN_F24R1_FB13_Pos)

#define	CAN_F24R1_FB13 CAN_F24R1_FB13_Msk

#define	CAN_F24R1_FB14_Pos (14U)

#define	CAN_F24R1_FB14_Msk (0x1UL << CAN_F24R1_FB14_Pos)

#define	CAN_F24R1_FB14 CAN_F24R1_FB14_Msk

#define	CAN_F24R1_FB15_Pos (15U)

#define	CAN_F24R1_FB15_Msk (0x1UL << CAN_F24R1_FB15_Pos)

#define	CAN_F24R1_FB15 CAN_F24R1_FB15_Msk

#define	CAN_F24R1_FB16_Pos (16U)

#define	CAN_F24R1_FB16_Msk (0x1UL << CAN_F24R1_FB16_Pos)

#define	CAN_F24R1_FB16 CAN_F24R1_FB16_Msk

#define	CAN_F24R1_FB17_Pos (17U)

#define	CAN_F24R1_FB17_Msk (0x1UL << CAN_F24R1_FB17_Pos)

#define	CAN_F24R1_FB17 CAN_F24R1_FB17_Msk

#define	CAN_F24R1_FB18_Pos (18U)

#define	CAN_F24R1_FB18_Msk (0x1UL << CAN_F24R1_FB18_Pos)

#define	CAN_F24R1_FB18 CAN_F24R1_FB18_Msk

#define	CAN_F24R1_FB19_Pos (19U)

#define	CAN_F24R1_FB19_Msk (0x1UL << CAN_F24R1_FB19_Pos)

#define	CAN_F24R1_FB19 CAN_F24R1_FB19_Msk

#define	CAN_F24R1_FB20_Pos (20U)

#define	CAN_F24R1_FB20_Msk (0x1UL << CAN_F24R1_FB20_Pos)

#define	CAN_F24R1_FB20 CAN_F24R1_FB20_Msk

#define	CAN_F24R1_FB21_Pos (21U)

#define	CAN_F24R1_FB21_Msk (0x1UL << CAN_F24R1_FB21_Pos)

#define	CAN_F24R1_FB21 CAN_F24R1_FB21_Msk

#define	CAN_F24R1_FB22_Pos (22U)

#define	CAN_F24R1_FB22_Msk (0x1UL << CAN_F24R1_FB22_Pos)

#define	CAN_F24R1_FB22 CAN_F24R1_FB22_Msk

#define	CAN_F24R1_FB23_Pos (23U)

#define	CAN_F24R1_FB23_Msk (0x1UL << CAN_F24R1_FB23_Pos)

#define	CAN_F24R1_FB23 CAN_F24R1_FB23_Msk

#define	CAN_F24R1_FB24_Pos (24U)

#define	CAN_F24R1_FB24_Msk (0x1UL << CAN_F24R1_FB24_Pos)

#define	CAN_F24R1_FB24 CAN_F24R1_FB24_Msk

#define	CAN_F24R1_FB25_Pos (25U)

#define	CAN_F24R1_FB25_Msk (0x1UL << CAN_F24R1_FB25_Pos)

#define	CAN_F24R1_FB25 CAN_F24R1_FB25_Msk

#define	CAN_F24R1_FB26_Pos (26U)

#define	CAN_F24R1_FB26_Msk (0x1UL << CAN_F24R1_FB26_Pos)

#define	CAN_F24R1_FB26 CAN_F24R1_FB26_Msk

#define	CAN_F24R1_FB27_Pos (27U)

#define	CAN_F24R1_FB27_Msk (0x1UL << CAN_F24R1_FB27_Pos)

#define	CAN_F24R1_FB27 CAN_F24R1_FB27_Msk

#define	CAN_F24R1_FB28_Pos (28U)

#define	CAN_F24R1_FB28_Msk (0x1UL << CAN_F24R1_FB28_Pos)

#define	CAN_F24R1_FB28 CAN_F24R1_FB28_Msk

#define	CAN_F24R1_FB29_Pos (29U)

#define	CAN_F24R1_FB29_Msk (0x1UL << CAN_F24R1_FB29_Pos)

#define	CAN_F24R1_FB29 CAN_F24R1_FB29_Msk

#define	CAN_F24R1_FB30_Pos (30U)

#define	CAN_F24R1_FB30_Msk (0x1UL << CAN_F24R1_FB30_Pos)

#define	CAN_F24R1_FB30 CAN_F24R1_FB30_Msk

#define	CAN_F24R1_FB31_Pos (31U)

#define	CAN_F24R1_FB31_Msk (0x1UL << CAN_F24R1_FB31_Pos)

#define	CAN_F24R1_FB31 CAN_F24R1_FB31_Msk

#define	CAN_F25R1_FB0_Pos (0U)

#define	CAN_F25R1_FB0_Msk (0x1UL << CAN_F25R1_FB0_Pos)

#define	CAN_F25R1_FB0 CAN_F25R1_FB0_Msk

#define	CAN_F25R1_FB1_Pos (1U)

#define	CAN_F25R1_FB1_Msk (0x1UL << CAN_F25R1_FB1_Pos)

#define	CAN_F25R1_FB1 CAN_F25R1_FB1_Msk

#define	CAN_F25R1_FB2_Pos (2U)

#define	CAN_F25R1_FB2_Msk (0x1UL << CAN_F25R1_FB2_Pos)

#define	CAN_F25R1_FB2 CAN_F25R1_FB2_Msk

#define	CAN_F25R1_FB3_Pos (3U)

#define	CAN_F25R1_FB3_Msk (0x1UL << CAN_F25R1_FB3_Pos)

#define	CAN_F25R1_FB3 CAN_F25R1_FB3_Msk

#define	CAN_F25R1_FB4_Pos (4U)

#define	CAN_F25R1_FB4_Msk (0x1UL << CAN_F25R1_FB4_Pos)

#define	CAN_F25R1_FB4 CAN_F25R1_FB4_Msk

#define	CAN_F25R1_FB5_Pos (5U)

#define	CAN_F25R1_FB5_Msk (0x1UL << CAN_F25R1_FB5_Pos)

#define	CAN_F25R1_FB5 CAN_F25R1_FB5_Msk

#define	CAN_F25R1_FB6_Pos (6U)

#define	CAN_F25R1_FB6_Msk (0x1UL << CAN_F25R1_FB6_Pos)

#define	CAN_F25R1_FB6 CAN_F25R1_FB6_Msk

#define	CAN_F25R1_FB7_Pos (7U)

#define	CAN_F25R1_FB7_Msk (0x1UL << CAN_F25R1_FB7_Pos)

#define	CAN_F25R1_FB7 CAN_F25R1_FB7_Msk

#define	CAN_F25R1_FB8_Pos (8U)

#define	CAN_F25R1_FB8_Msk (0x1UL << CAN_F25R1_FB8_Pos)

#define	CAN_F25R1_FB8 CAN_F25R1_FB8_Msk

#define	CAN_F25R1_FB9_Pos (9U)

#define	CAN_F25R1_FB9_Msk (0x1UL << CAN_F25R1_FB9_Pos)

#define	CAN_F25R1_FB9 CAN_F25R1_FB9_Msk

#define	CAN_F25R1_FB10_Pos (10U)

#define	CAN_F25R1_FB10_Msk (0x1UL << CAN_F25R1_FB10_Pos)

#define	CAN_F25R1_FB10 CAN_F25R1_FB10_Msk

#define	CAN_F25R1_FB11_Pos (11U)

#define	CAN_F25R1_FB11_Msk (0x1UL << CAN_F25R1_FB11_Pos)

#define	CAN_F25R1_FB11 CAN_F25R1_FB11_Msk

#define	CAN_F25R1_FB12_Pos (12U)

#define	CAN_F25R1_FB12_Msk (0x1UL << CAN_F25R1_FB12_Pos)

#define	CAN_F25R1_FB12 CAN_F25R1_FB12_Msk

#define	CAN_F25R1_FB13_Pos (13U)

#define	CAN_F25R1_FB13_Msk (0x1UL << CAN_F25R1_FB13_Pos)

#define	CAN_F25R1_FB13 CAN_F25R1_FB13_Msk

#define	CAN_F25R1_FB14_Pos (14U)

#define	CAN_F25R1_FB14_Msk (0x1UL << CAN_F25R1_FB14_Pos)

#define	CAN_F25R1_FB14 CAN_F25R1_FB14_Msk

#define	CAN_F25R1_FB15_Pos (15U)

#define	CAN_F25R1_FB15_Msk (0x1UL << CAN_F25R1_FB15_Pos)

#define	CAN_F25R1_FB15 CAN_F25R1_FB15_Msk

#define	CAN_F25R1_FB16_Pos (16U)

#define	CAN_F25R1_FB16_Msk (0x1UL << CAN_F25R1_FB16_Pos)

#define	CAN_F25R1_FB16 CAN_F25R1_FB16_Msk

#define	CAN_F25R1_FB17_Pos (17U)

#define	CAN_F25R1_FB17_Msk (0x1UL << CAN_F25R1_FB17_Pos)

#define	CAN_F25R1_FB17 CAN_F25R1_FB17_Msk

#define	CAN_F25R1_FB18_Pos (18U)

#define	CAN_F25R1_FB18_Msk (0x1UL << CAN_F25R1_FB18_Pos)

#define	CAN_F25R1_FB18 CAN_F25R1_FB18_Msk

#define	CAN_F25R1_FB19_Pos (19U)

#define	CAN_F25R1_FB19_Msk (0x1UL << CAN_F25R1_FB19_Pos)

#define	CAN_F25R1_FB19 CAN_F25R1_FB19_Msk

#define	CAN_F25R1_FB20_Pos (20U)

#define	CAN_F25R1_FB20_Msk (0x1UL << CAN_F25R1_FB20_Pos)

#define	CAN_F25R1_FB20 CAN_F25R1_FB20_Msk

#define	CAN_F25R1_FB21_Pos (21U)

#define	CAN_F25R1_FB21_Msk (0x1UL << CAN_F25R1_FB21_Pos)

#define	CAN_F25R1_FB21 CAN_F25R1_FB21_Msk

#define	CAN_F25R1_FB22_Pos (22U)

#define	CAN_F25R1_FB22_Msk (0x1UL << CAN_F25R1_FB22_Pos)

#define	CAN_F25R1_FB22 CAN_F25R1_FB22_Msk

#define	CAN_F25R1_FB23_Pos (23U)

#define	CAN_F25R1_FB23_Msk (0x1UL << CAN_F25R1_FB23_Pos)

#define	CAN_F25R1_FB23 CAN_F25R1_FB23_Msk

#define	CAN_F25R1_FB24_Pos (24U)

#define	CAN_F25R1_FB24_Msk (0x1UL << CAN_F25R1_FB24_Pos)

#define	CAN_F25R1_FB24 CAN_F25R1_FB24_Msk

#define	CAN_F25R1_FB25_Pos (25U)

#define	CAN_F25R1_FB25_Msk (0x1UL << CAN_F25R1_FB25_Pos)

#define	CAN_F25R1_FB25 CAN_F25R1_FB25_Msk

#define	CAN_F25R1_FB26_Pos (26U)

#define	CAN_F25R1_FB26_Msk (0x1UL << CAN_F25R1_FB26_Pos)

#define	CAN_F25R1_FB26 CAN_F25R1_FB26_Msk

#define	CAN_F25R1_FB27_Pos (27U)

#define	CAN_F25R1_FB27_Msk (0x1UL << CAN_F25R1_FB27_Pos)

#define	CAN_F25R1_FB27 CAN_F25R1_FB27_Msk

#define	CAN_F25R1_FB28_Pos (28U)

#define	CAN_F25R1_FB28_Msk (0x1UL << CAN_F25R1_FB28_Pos)

#define	CAN_F25R1_FB28 CAN_F25R1_FB28_Msk

#define	CAN_F25R1_FB29_Pos (29U)

#define	CAN_F25R1_FB29_Msk (0x1UL << CAN_F25R1_FB29_Pos)

#define	CAN_F25R1_FB29 CAN_F25R1_FB29_Msk

#define	CAN_F25R1_FB30_Pos (30U)

#define	CAN_F25R1_FB30_Msk (0x1UL << CAN_F25R1_FB30_Pos)

#define	CAN_F25R1_FB30 CAN_F25R1_FB30_Msk

#define	CAN_F25R1_FB31_Pos (31U)

#define	CAN_F25R1_FB31_Msk (0x1UL << CAN_F25R1_FB31_Pos)

#define	CAN_F25R1_FB31 CAN_F25R1_FB31_Msk

#define	CAN_F26R1_FB0_Pos (0U)

#define	CAN_F26R1_FB0_Msk (0x1UL << CAN_F26R1_FB0_Pos)

#define	CAN_F26R1_FB0 CAN_F26R1_FB0_Msk

#define	CAN_F26R1_FB1_Pos (1U)

#define	CAN_F26R1_FB1_Msk (0x1UL << CAN_F26R1_FB1_Pos)

#define	CAN_F26R1_FB1 CAN_F26R1_FB1_Msk

#define	CAN_F26R1_FB2_Pos (2U)

#define	CAN_F26R1_FB2_Msk (0x1UL << CAN_F26R1_FB2_Pos)

#define	CAN_F26R1_FB2 CAN_F26R1_FB2_Msk

#define	CAN_F26R1_FB3_Pos (3U)

#define	CAN_F26R1_FB3_Msk (0x1UL << CAN_F26R1_FB3_Pos)

#define	CAN_F26R1_FB3 CAN_F26R1_FB3_Msk

#define	CAN_F26R1_FB4_Pos (4U)

#define	CAN_F26R1_FB4_Msk (0x1UL << CAN_F26R1_FB4_Pos)

#define	CAN_F26R1_FB4 CAN_F26R1_FB4_Msk

#define	CAN_F26R1_FB5_Pos (5U)

#define	CAN_F26R1_FB5_Msk (0x1UL << CAN_F26R1_FB5_Pos)

#define	CAN_F26R1_FB5 CAN_F26R1_FB5_Msk

#define	CAN_F26R1_FB6_Pos (6U)

#define	CAN_F26R1_FB6_Msk (0x1UL << CAN_F26R1_FB6_Pos)

#define	CAN_F26R1_FB6 CAN_F26R1_FB6_Msk

#define	CAN_F26R1_FB7_Pos (7U)

#define	CAN_F26R1_FB7_Msk (0x1UL << CAN_F26R1_FB7_Pos)

#define	CAN_F26R1_FB7 CAN_F26R1_FB7_Msk

#define	CAN_F26R1_FB8_Pos (8U)

#define	CAN_F26R1_FB8_Msk (0x1UL << CAN_F26R1_FB8_Pos)

#define	CAN_F26R1_FB8 CAN_F26R1_FB8_Msk

#define	CAN_F26R1_FB9_Pos (9U)

#define	CAN_F26R1_FB9_Msk (0x1UL << CAN_F26R1_FB9_Pos)

#define	CAN_F26R1_FB9 CAN_F26R1_FB9_Msk

#define	CAN_F26R1_FB10_Pos (10U)

#define	CAN_F26R1_FB10_Msk (0x1UL << CAN_F26R1_FB10_Pos)

#define	CAN_F26R1_FB10 CAN_F26R1_FB10_Msk

#define	CAN_F26R1_FB11_Pos (11U)

#define	CAN_F26R1_FB11_Msk (0x1UL << CAN_F26R1_FB11_Pos)

#define	CAN_F26R1_FB11 CAN_F26R1_FB11_Msk

#define	CAN_F26R1_FB12_Pos (12U)

#define	CAN_F26R1_FB12_Msk (0x1UL << CAN_F26R1_FB12_Pos)

#define	CAN_F26R1_FB12 CAN_F26R1_FB12_Msk

#define	CAN_F26R1_FB13_Pos (13U)

#define	CAN_F26R1_FB13_Msk (0x1UL << CAN_F26R1_FB13_Pos)

#define	CAN_F26R1_FB13 CAN_F26R1_FB13_Msk

#define	CAN_F26R1_FB14_Pos (14U)

#define	CAN_F26R1_FB14_Msk (0x1UL << CAN_F26R1_FB14_Pos)

#define	CAN_F26R1_FB14 CAN_F26R1_FB14_Msk

#define	CAN_F26R1_FB15_Pos (15U)

#define	CAN_F26R1_FB15_Msk (0x1UL << CAN_F26R1_FB15_Pos)

#define	CAN_F26R1_FB15 CAN_F26R1_FB15_Msk

#define	CAN_F26R1_FB16_Pos (16U)

#define	CAN_F26R1_FB16_Msk (0x1UL << CAN_F26R1_FB16_Pos)

#define	CAN_F26R1_FB16 CAN_F26R1_FB16_Msk

#define	CAN_F26R1_FB17_Pos (17U)

#define	CAN_F26R1_FB17_Msk (0x1UL << CAN_F26R1_FB17_Pos)

#define	CAN_F26R1_FB17 CAN_F26R1_FB17_Msk

#define	CAN_F26R1_FB18_Pos (18U)

#define	CAN_F26R1_FB18_Msk (0x1UL << CAN_F26R1_FB18_Pos)

#define	CAN_F26R1_FB18 CAN_F26R1_FB18_Msk

#define	CAN_F26R1_FB19_Pos (19U)

#define	CAN_F26R1_FB19_Msk (0x1UL << CAN_F26R1_FB19_Pos)

#define	CAN_F26R1_FB19 CAN_F26R1_FB19_Msk

#define	CAN_F26R1_FB20_Pos (20U)

#define	CAN_F26R1_FB20_Msk (0x1UL << CAN_F26R1_FB20_Pos)

#define	CAN_F26R1_FB20 CAN_F26R1_FB20_Msk

#define	CAN_F26R1_FB21_Pos (21U)

#define	CAN_F26R1_FB21_Msk (0x1UL << CAN_F26R1_FB21_Pos)

#define	CAN_F26R1_FB21 CAN_F26R1_FB21_Msk

#define	CAN_F26R1_FB22_Pos (22U)

#define	CAN_F26R1_FB22_Msk (0x1UL << CAN_F26R1_FB22_Pos)

#define	CAN_F26R1_FB22 CAN_F26R1_FB22_Msk

#define	CAN_F26R1_FB23_Pos (23U)

#define	CAN_F26R1_FB23_Msk (0x1UL << CAN_F26R1_FB23_Pos)

#define	CAN_F26R1_FB23 CAN_F26R1_FB23_Msk

#define	CAN_F26R1_FB24_Pos (24U)

#define	CAN_F26R1_FB24_Msk (0x1UL << CAN_F26R1_FB24_Pos)

#define	CAN_F26R1_FB24 CAN_F26R1_FB24_Msk

#define	CAN_F26R1_FB25_Pos (25U)

#define	CAN_F26R1_FB25_Msk (0x1UL << CAN_F26R1_FB25_Pos)

#define	CAN_F26R1_FB25 CAN_F26R1_FB25_Msk

#define	CAN_F26R1_FB26_Pos (26U)

#define	CAN_F26R1_FB26_Msk (0x1UL << CAN_F26R1_FB26_Pos)

#define	CAN_F26R1_FB26 CAN_F26R1_FB26_Msk

#define	CAN_F26R1_FB27_Pos (27U)

#define	CAN_F26R1_FB27_Msk (0x1UL << CAN_F26R1_FB27_Pos)

#define	CAN_F26R1_FB27 CAN_F26R1_FB27_Msk

#define	CAN_F26R1_FB28_Pos (28U)

#define	CAN_F26R1_FB28_Msk (0x1UL << CAN_F26R1_FB28_Pos)

#define	CAN_F26R1_FB28 CAN_F26R1_FB28_Msk

#define	CAN_F26R1_FB29_Pos (29U)

#define	CAN_F26R1_FB29_Msk (0x1UL << CAN_F26R1_FB29_Pos)

#define	CAN_F26R1_FB29 CAN_F26R1_FB29_Msk

#define	CAN_F26R1_FB30_Pos (30U)

#define	CAN_F26R1_FB30_Msk (0x1UL << CAN_F26R1_FB30_Pos)

#define	CAN_F26R1_FB30 CAN_F26R1_FB30_Msk

#define	CAN_F26R1_FB31_Pos (31U)

#define	CAN_F26R1_FB31_Msk (0x1UL << CAN_F26R1_FB31_Pos)

#define	CAN_F26R1_FB31 CAN_F26R1_FB31_Msk

#define	CAN_F27R1_FB0_Pos (0U)

#define	CAN_F27R1_FB0_Msk (0x1UL << CAN_F27R1_FB0_Pos)

#define	CAN_F27R1_FB0 CAN_F27R1_FB0_Msk

#define	CAN_F27R1_FB1_Pos (1U)

#define	CAN_F27R1_FB1_Msk (0x1UL << CAN_F27R1_FB1_Pos)

#define	CAN_F27R1_FB1 CAN_F27R1_FB1_Msk

#define	CAN_F27R1_FB2_Pos (2U)

#define	CAN_F27R1_FB2_Msk (0x1UL << CAN_F27R1_FB2_Pos)

#define	CAN_F27R1_FB2 CAN_F27R1_FB2_Msk

#define	CAN_F27R1_FB3_Pos (3U)

#define	CAN_F27R1_FB3_Msk (0x1UL << CAN_F27R1_FB3_Pos)

#define	CAN_F27R1_FB3 CAN_F27R1_FB3_Msk

#define	CAN_F27R1_FB4_Pos (4U)

#define	CAN_F27R1_FB4_Msk (0x1UL << CAN_F27R1_FB4_Pos)

#define	CAN_F27R1_FB4 CAN_F27R1_FB4_Msk

#define	CAN_F27R1_FB5_Pos (5U)

#define	CAN_F27R1_FB5_Msk (0x1UL << CAN_F27R1_FB5_Pos)

#define	CAN_F27R1_FB5 CAN_F27R1_FB5_Msk

#define	CAN_F27R1_FB6_Pos (6U)

#define	CAN_F27R1_FB6_Msk (0x1UL << CAN_F27R1_FB6_Pos)

#define	CAN_F27R1_FB6 CAN_F27R1_FB6_Msk

#define	CAN_F27R1_FB7_Pos (7U)

#define	CAN_F27R1_FB7_Msk (0x1UL << CAN_F27R1_FB7_Pos)

#define	CAN_F27R1_FB7 CAN_F27R1_FB7_Msk

#define	CAN_F27R1_FB8_Pos (8U)

#define	CAN_F27R1_FB8_Msk (0x1UL << CAN_F27R1_FB8_Pos)

#define	CAN_F27R1_FB8 CAN_F27R1_FB8_Msk

#define	CAN_F27R1_FB9_Pos (9U)

#define	CAN_F27R1_FB9_Msk (0x1UL << CAN_F27R1_FB9_Pos)

#define	CAN_F27R1_FB9 CAN_F27R1_FB9_Msk

#define	CAN_F27R1_FB10_Pos (10U)

#define	CAN_F27R1_FB10_Msk (0x1UL << CAN_F27R1_FB10_Pos)

#define	CAN_F27R1_FB10 CAN_F27R1_FB10_Msk

#define	CAN_F27R1_FB11_Pos (11U)

#define	CAN_F27R1_FB11_Msk (0x1UL << CAN_F27R1_FB11_Pos)

#define	CAN_F27R1_FB11 CAN_F27R1_FB11_Msk

#define	CAN_F27R1_FB12_Pos (12U)

#define	CAN_F27R1_FB12_Msk (0x1UL << CAN_F27R1_FB12_Pos)

#define	CAN_F27R1_FB12 CAN_F27R1_FB12_Msk

#define	CAN_F27R1_FB13_Pos (13U)

#define	CAN_F27R1_FB13_Msk (0x1UL << CAN_F27R1_FB13_Pos)

#define	CAN_F27R1_FB13 CAN_F27R1_FB13_Msk

#define	CAN_F27R1_FB14_Pos (14U)

#define	CAN_F27R1_FB14_Msk (0x1UL << CAN_F27R1_FB14_Pos)

#define	CAN_F27R1_FB14 CAN_F27R1_FB14_Msk

#define	CAN_F27R1_FB15_Pos (15U)

#define	CAN_F27R1_FB15_Msk (0x1UL << CAN_F27R1_FB15_Pos)

#define	CAN_F27R1_FB15 CAN_F27R1_FB15_Msk

#define	CAN_F27R1_FB16_Pos (16U)

#define	CAN_F27R1_FB16_Msk (0x1UL << CAN_F27R1_FB16_Pos)

#define	CAN_F27R1_FB16 CAN_F27R1_FB16_Msk

#define	CAN_F27R1_FB17_Pos (17U)

#define	CAN_F27R1_FB17_Msk (0x1UL << CAN_F27R1_FB17_Pos)

#define	CAN_F27R1_FB17 CAN_F27R1_FB17_Msk

#define	CAN_F27R1_FB18_Pos (18U)

#define	CAN_F27R1_FB18_Msk (0x1UL << CAN_F27R1_FB18_Pos)

#define	CAN_F27R1_FB18 CAN_F27R1_FB18_Msk

#define	CAN_F27R1_FB19_Pos (19U)

#define	CAN_F27R1_FB19_Msk (0x1UL << CAN_F27R1_FB19_Pos)

#define	CAN_F27R1_FB19 CAN_F27R1_FB19_Msk

#define	CAN_F27R1_FB20_Pos (20U)

#define	CAN_F27R1_FB20_Msk (0x1UL << CAN_F27R1_FB20_Pos)

#define	CAN_F27R1_FB20 CAN_F27R1_FB20_Msk

#define	CAN_F27R1_FB21_Pos (21U)

#define	CAN_F27R1_FB21_Msk (0x1UL << CAN_F27R1_FB21_Pos)

#define	CAN_F27R1_FB21 CAN_F27R1_FB21_Msk

#define	CAN_F27R1_FB22_Pos (22U)

#define	CAN_F27R1_FB22_Msk (0x1UL << CAN_F27R1_FB22_Pos)

#define	CAN_F27R1_FB22 CAN_F27R1_FB22_Msk

#define	CAN_F27R1_FB23_Pos (23U)

#define	CAN_F27R1_FB23_Msk (0x1UL << CAN_F27R1_FB23_Pos)

#define	CAN_F27R1_FB23 CAN_F27R1_FB23_Msk

#define	CAN_F27R1_FB24_Pos (24U)

#define	CAN_F27R1_FB24_Msk (0x1UL << CAN_F27R1_FB24_Pos)

#define	CAN_F27R1_FB24 CAN_F27R1_FB24_Msk

#define	CAN_F27R1_FB25_Pos (25U)

#define	CAN_F27R1_FB25_Msk (0x1UL << CAN_F27R1_FB25_Pos)

#define	CAN_F27R1_FB25 CAN_F27R1_FB25_Msk

#define	CAN_F27R1_FB26_Pos (26U)

#define	CAN_F27R1_FB26_Msk (0x1UL << CAN_F27R1_FB26_Pos)

#define	CAN_F27R1_FB26 CAN_F27R1_FB26_Msk

#define	CAN_F27R1_FB27_Pos (27U)

#define	CAN_F27R1_FB27_Msk (0x1UL << CAN_F27R1_FB27_Pos)

#define	CAN_F27R1_FB27 CAN_F27R1_FB27_Msk

#define	CAN_F27R1_FB28_Pos (28U)

#define	CAN_F27R1_FB28_Msk (0x1UL << CAN_F27R1_FB28_Pos)

#define	CAN_F27R1_FB28 CAN_F27R1_FB28_Msk

#define	CAN_F27R1_FB29_Pos (29U)

#define	CAN_F27R1_FB29_Msk (0x1UL << CAN_F27R1_FB29_Pos)

#define	CAN_F27R1_FB29 CAN_F27R1_FB29_Msk

#define	CAN_F27R1_FB30_Pos (30U)

#define	CAN_F27R1_FB30_Msk (0x1UL << CAN_F27R1_FB30_Pos)

#define	CAN_F27R1_FB30 CAN_F27R1_FB30_Msk

#define	CAN_F27R1_FB31_Pos (31U)

#define	CAN_F27R1_FB31_Msk (0x1UL << CAN_F27R1_FB31_Pos)

#define	CAN_F27R1_FB31 CAN_F27R1_FB31_Msk

#define	CAN_F0R2_FB0_Pos (0U)

#define	CAN_F0R2_FB0_Msk (0x1UL << CAN_F0R2_FB0_Pos)

#define	CAN_F0R2_FB0 CAN_F0R2_FB0_Msk

#define	CAN_F0R2_FB1_Pos (1U)

#define	CAN_F0R2_FB1_Msk (0x1UL << CAN_F0R2_FB1_Pos)

#define	CAN_F0R2_FB1 CAN_F0R2_FB1_Msk

#define	CAN_F0R2_FB2_Pos (2U)

#define	CAN_F0R2_FB2_Msk (0x1UL << CAN_F0R2_FB2_Pos)

#define	CAN_F0R2_FB2 CAN_F0R2_FB2_Msk

#define	CAN_F0R2_FB3_Pos (3U)

#define	CAN_F0R2_FB3_Msk (0x1UL << CAN_F0R2_FB3_Pos)

#define	CAN_F0R2_FB3 CAN_F0R2_FB3_Msk

#define	CAN_F0R2_FB4_Pos (4U)

#define	CAN_F0R2_FB4_Msk (0x1UL << CAN_F0R2_FB4_Pos)

#define	CAN_F0R2_FB4 CAN_F0R2_FB4_Msk

#define	CAN_F0R2_FB5_Pos (5U)

#define	CAN_F0R2_FB5_Msk (0x1UL << CAN_F0R2_FB5_Pos)

#define	CAN_F0R2_FB5 CAN_F0R2_FB5_Msk

#define	CAN_F0R2_FB6_Pos (6U)

#define	CAN_F0R2_FB6_Msk (0x1UL << CAN_F0R2_FB6_Pos)

#define	CAN_F0R2_FB6 CAN_F0R2_FB6_Msk

#define	CAN_F0R2_FB7_Pos (7U)

#define	CAN_F0R2_FB7_Msk (0x1UL << CAN_F0R2_FB7_Pos)

#define	CAN_F0R2_FB7 CAN_F0R2_FB7_Msk

#define	CAN_F0R2_FB8_Pos (8U)

#define	CAN_F0R2_FB8_Msk (0x1UL << CAN_F0R2_FB8_Pos)

#define	CAN_F0R2_FB8 CAN_F0R2_FB8_Msk

#define	CAN_F0R2_FB9_Pos (9U)

#define	CAN_F0R2_FB9_Msk (0x1UL << CAN_F0R2_FB9_Pos)

#define	CAN_F0R2_FB9 CAN_F0R2_FB9_Msk

#define	CAN_F0R2_FB10_Pos (10U)

#define	CAN_F0R2_FB10_Msk (0x1UL << CAN_F0R2_FB10_Pos)

#define	CAN_F0R2_FB10 CAN_F0R2_FB10_Msk

#define	CAN_F0R2_FB11_Pos (11U)

#define	CAN_F0R2_FB11_Msk (0x1UL << CAN_F0R2_FB11_Pos)

#define	CAN_F0R2_FB11 CAN_F0R2_FB11_Msk

#define	CAN_F0R2_FB12_Pos (12U)

#define	CAN_F0R2_FB12_Msk (0x1UL << CAN_F0R2_FB12_Pos)

#define	CAN_F0R2_FB12 CAN_F0R2_FB12_Msk

#define	CAN_F0R2_FB13_Pos (13U)

#define	CAN_F0R2_FB13_Msk (0x1UL << CAN_F0R2_FB13_Pos)

#define	CAN_F0R2_FB13 CAN_F0R2_FB13_Msk

#define	CAN_F0R2_FB14_Pos (14U)

#define	CAN_F0R2_FB14_Msk (0x1UL << CAN_F0R2_FB14_Pos)

#define	CAN_F0R2_FB14 CAN_F0R2_FB14_Msk

#define	CAN_F0R2_FB15_Pos (15U)

#define	CAN_F0R2_FB15_Msk (0x1UL << CAN_F0R2_FB15_Pos)

#define	CAN_F0R2_FB15 CAN_F0R2_FB15_Msk

#define	CAN_F0R2_FB16_Pos (16U)

#define	CAN_F0R2_FB16_Msk (0x1UL << CAN_F0R2_FB16_Pos)

#define	CAN_F0R2_FB16 CAN_F0R2_FB16_Msk

#define	CAN_F0R2_FB17_Pos (17U)

#define	CAN_F0R2_FB17_Msk (0x1UL << CAN_F0R2_FB17_Pos)

#define	CAN_F0R2_FB17 CAN_F0R2_FB17_Msk

#define	CAN_F0R2_FB18_Pos (18U)

#define	CAN_F0R2_FB18_Msk (0x1UL << CAN_F0R2_FB18_Pos)

#define	CAN_F0R2_FB18 CAN_F0R2_FB18_Msk

#define	CAN_F0R2_FB19_Pos (19U)

#define	CAN_F0R2_FB19_Msk (0x1UL << CAN_F0R2_FB19_Pos)

#define	CAN_F0R2_FB19 CAN_F0R2_FB19_Msk

#define	CAN_F0R2_FB20_Pos (20U)

#define	CAN_F0R2_FB20_Msk (0x1UL << CAN_F0R2_FB20_Pos)

#define	CAN_F0R2_FB20 CAN_F0R2_FB20_Msk

#define	CAN_F0R2_FB21_Pos (21U)

#define	CAN_F0R2_FB21_Msk (0x1UL << CAN_F0R2_FB21_Pos)

#define	CAN_F0R2_FB21 CAN_F0R2_FB21_Msk

#define	CAN_F0R2_FB22_Pos (22U)

#define	CAN_F0R2_FB22_Msk (0x1UL << CAN_F0R2_FB22_Pos)

#define	CAN_F0R2_FB22 CAN_F0R2_FB22_Msk

#define	CAN_F0R2_FB23_Pos (23U)

#define	CAN_F0R2_FB23_Msk (0x1UL << CAN_F0R2_FB23_Pos)

#define	CAN_F0R2_FB23 CAN_F0R2_FB23_Msk

#define	CAN_F0R2_FB24_Pos (24U)

#define	CAN_F0R2_FB24_Msk (0x1UL << CAN_F0R2_FB24_Pos)

#define	CAN_F0R2_FB24 CAN_F0R2_FB24_Msk

#define	CAN_F0R2_FB25_Pos (25U)

#define	CAN_F0R2_FB25_Msk (0x1UL << CAN_F0R2_FB25_Pos)

#define	CAN_F0R2_FB25 CAN_F0R2_FB25_Msk

#define	CAN_F0R2_FB26_Pos (26U)

#define	CAN_F0R2_FB26_Msk (0x1UL << CAN_F0R2_FB26_Pos)

#define	CAN_F0R2_FB26 CAN_F0R2_FB26_Msk

#define	CAN_F0R2_FB27_Pos (27U)

#define	CAN_F0R2_FB27_Msk (0x1UL << CAN_F0R2_FB27_Pos)

#define	CAN_F0R2_FB27 CAN_F0R2_FB27_Msk

#define	CAN_F0R2_FB28_Pos (28U)

#define	CAN_F0R2_FB28_Msk (0x1UL << CAN_F0R2_FB28_Pos)

#define	CAN_F0R2_FB28 CAN_F0R2_FB28_Msk

#define	CAN_F0R2_FB29_Pos (29U)

#define	CAN_F0R2_FB29_Msk (0x1UL << CAN_F0R2_FB29_Pos)

#define	CAN_F0R2_FB29 CAN_F0R2_FB29_Msk

#define	CAN_F0R2_FB30_Pos (30U)

#define	CAN_F0R2_FB30_Msk (0x1UL << CAN_F0R2_FB30_Pos)

#define	CAN_F0R2_FB30 CAN_F0R2_FB30_Msk

#define	CAN_F0R2_FB31_Pos (31U)

#define	CAN_F0R2_FB31_Msk (0x1UL << CAN_F0R2_FB31_Pos)

#define	CAN_F0R2_FB31 CAN_F0R2_FB31_Msk

#define	CAN_F1R2_FB0_Pos (0U)

#define	CAN_F1R2_FB0_Msk (0x1UL << CAN_F1R2_FB0_Pos)

#define	CAN_F1R2_FB0 CAN_F1R2_FB0_Msk

#define	CAN_F1R2_FB1_Pos (1U)

#define	CAN_F1R2_FB1_Msk (0x1UL << CAN_F1R2_FB1_Pos)

#define	CAN_F1R2_FB1 CAN_F1R2_FB1_Msk

#define	CAN_F1R2_FB2_Pos (2U)

#define	CAN_F1R2_FB2_Msk (0x1UL << CAN_F1R2_FB2_Pos)

#define	CAN_F1R2_FB2 CAN_F1R2_FB2_Msk

#define	CAN_F1R2_FB3_Pos (3U)

#define	CAN_F1R2_FB3_Msk (0x1UL << CAN_F1R2_FB3_Pos)

#define	CAN_F1R2_FB3 CAN_F1R2_FB3_Msk

#define	CAN_F1R2_FB4_Pos (4U)

#define	CAN_F1R2_FB4_Msk (0x1UL << CAN_F1R2_FB4_Pos)

#define	CAN_F1R2_FB4 CAN_F1R2_FB4_Msk

#define	CAN_F1R2_FB5_Pos (5U)

#define	CAN_F1R2_FB5_Msk (0x1UL << CAN_F1R2_FB5_Pos)

#define	CAN_F1R2_FB5 CAN_F1R2_FB5_Msk

#define	CAN_F1R2_FB6_Pos (6U)

#define	CAN_F1R2_FB6_Msk (0x1UL << CAN_F1R2_FB6_Pos)

#define	CAN_F1R2_FB6 CAN_F1R2_FB6_Msk

#define	CAN_F1R2_FB7_Pos (7U)

#define	CAN_F1R2_FB7_Msk (0x1UL << CAN_F1R2_FB7_Pos)

#define	CAN_F1R2_FB7 CAN_F1R2_FB7_Msk

#define	CAN_F1R2_FB8_Pos (8U)

#define	CAN_F1R2_FB8_Msk (0x1UL << CAN_F1R2_FB8_Pos)

#define	CAN_F1R2_FB8 CAN_F1R2_FB8_Msk

#define	CAN_F1R2_FB9_Pos (9U)

#define	CAN_F1R2_FB9_Msk (0x1UL << CAN_F1R2_FB9_Pos)

#define	CAN_F1R2_FB9 CAN_F1R2_FB9_Msk

#define	CAN_F1R2_FB10_Pos (10U)

#define	CAN_F1R2_FB10_Msk (0x1UL << CAN_F1R2_FB10_Pos)

#define	CAN_F1R2_FB10 CAN_F1R2_FB10_Msk

#define	CAN_F1R2_FB11_Pos (11U)

#define	CAN_F1R2_FB11_Msk (0x1UL << CAN_F1R2_FB11_Pos)

#define	CAN_F1R2_FB11 CAN_F1R2_FB11_Msk

#define	CAN_F1R2_FB12_Pos (12U)

#define	CAN_F1R2_FB12_Msk (0x1UL << CAN_F1R2_FB12_Pos)

#define	CAN_F1R2_FB12 CAN_F1R2_FB12_Msk

#define	CAN_F1R2_FB13_Pos (13U)

#define	CAN_F1R2_FB13_Msk (0x1UL << CAN_F1R2_FB13_Pos)

#define	CAN_F1R2_FB13 CAN_F1R2_FB13_Msk

#define	CAN_F1R2_FB14_Pos (14U)

#define	CAN_F1R2_FB14_Msk (0x1UL << CAN_F1R2_FB14_Pos)

#define	CAN_F1R2_FB14 CAN_F1R2_FB14_Msk

#define	CAN_F1R2_FB15_Pos (15U)

#define	CAN_F1R2_FB15_Msk (0x1UL << CAN_F1R2_FB15_Pos)

#define	CAN_F1R2_FB15 CAN_F1R2_FB15_Msk

#define	CAN_F1R2_FB16_Pos (16U)

#define	CAN_F1R2_FB16_Msk (0x1UL << CAN_F1R2_FB16_Pos)

#define	CAN_F1R2_FB16 CAN_F1R2_FB16_Msk

#define	CAN_F1R2_FB17_Pos (17U)

#define	CAN_F1R2_FB17_Msk (0x1UL << CAN_F1R2_FB17_Pos)

#define	CAN_F1R2_FB17 CAN_F1R2_FB17_Msk

#define	CAN_F1R2_FB18_Pos (18U)

#define	CAN_F1R2_FB18_Msk (0x1UL << CAN_F1R2_FB18_Pos)

#define	CAN_F1R2_FB18 CAN_F1R2_FB18_Msk

#define	CAN_F1R2_FB19_Pos (19U)

#define	CAN_F1R2_FB19_Msk (0x1UL << CAN_F1R2_FB19_Pos)

#define	CAN_F1R2_FB19 CAN_F1R2_FB19_Msk

#define	CAN_F1R2_FB20_Pos (20U)

#define	CAN_F1R2_FB20_Msk (0x1UL << CAN_F1R2_FB20_Pos)

#define	CAN_F1R2_FB20 CAN_F1R2_FB20_Msk

#define	CAN_F1R2_FB21_Pos (21U)

#define	CAN_F1R2_FB21_Msk (0x1UL << CAN_F1R2_FB21_Pos)

#define	CAN_F1R2_FB21 CAN_F1R2_FB21_Msk

#define	CAN_F1R2_FB22_Pos (22U)

#define	CAN_F1R2_FB22_Msk (0x1UL << CAN_F1R2_FB22_Pos)

#define	CAN_F1R2_FB22 CAN_F1R2_FB22_Msk

#define	CAN_F1R2_FB23_Pos (23U)

#define	CAN_F1R2_FB23_Msk (0x1UL << CAN_F1R2_FB23_Pos)

#define	CAN_F1R2_FB23 CAN_F1R2_FB23_Msk

#define	CAN_F1R2_FB24_Pos (24U)

#define	CAN_F1R2_FB24_Msk (0x1UL << CAN_F1R2_FB24_Pos)

#define	CAN_F1R2_FB24 CAN_F1R2_FB24_Msk

#define	CAN_F1R2_FB25_Pos (25U)

#define	CAN_F1R2_FB25_Msk (0x1UL << CAN_F1R2_FB25_Pos)

#define	CAN_F1R2_FB25 CAN_F1R2_FB25_Msk

#define	CAN_F1R2_FB26_Pos (26U)

#define	CAN_F1R2_FB26_Msk (0x1UL << CAN_F1R2_FB26_Pos)

#define	CAN_F1R2_FB26 CAN_F1R2_FB26_Msk

#define	CAN_F1R2_FB27_Pos (27U)

#define	CAN_F1R2_FB27_Msk (0x1UL << CAN_F1R2_FB27_Pos)

#define	CAN_F1R2_FB27 CAN_F1R2_FB27_Msk

#define	CAN_F1R2_FB28_Pos (28U)

#define	CAN_F1R2_FB28_Msk (0x1UL << CAN_F1R2_FB28_Pos)

#define	CAN_F1R2_FB28 CAN_F1R2_FB28_Msk

#define	CAN_F1R2_FB29_Pos (29U)

#define	CAN_F1R2_FB29_Msk (0x1UL << CAN_F1R2_FB29_Pos)

#define	CAN_F1R2_FB29 CAN_F1R2_FB29_Msk

#define	CAN_F1R2_FB30_Pos (30U)

#define	CAN_F1R2_FB30_Msk (0x1UL << CAN_F1R2_FB30_Pos)

#define	CAN_F1R2_FB30 CAN_F1R2_FB30_Msk

#define	CAN_F1R2_FB31_Pos (31U)

#define	CAN_F1R2_FB31_Msk (0x1UL << CAN_F1R2_FB31_Pos)

#define	CAN_F1R2_FB31 CAN_F1R2_FB31_Msk

#define	CAN_F2R2_FB0_Pos (0U)

#define	CAN_F2R2_FB0_Msk (0x1UL << CAN_F2R2_FB0_Pos)

#define	CAN_F2R2_FB0 CAN_F2R2_FB0_Msk

#define	CAN_F2R2_FB1_Pos (1U)

#define	CAN_F2R2_FB1_Msk (0x1UL << CAN_F2R2_FB1_Pos)

#define	CAN_F2R2_FB1 CAN_F2R2_FB1_Msk

#define	CAN_F2R2_FB2_Pos (2U)

#define	CAN_F2R2_FB2_Msk (0x1UL << CAN_F2R2_FB2_Pos)

#define	CAN_F2R2_FB2 CAN_F2R2_FB2_Msk

#define	CAN_F2R2_FB3_Pos (3U)

#define	CAN_F2R2_FB3_Msk (0x1UL << CAN_F2R2_FB3_Pos)

#define	CAN_F2R2_FB3 CAN_F2R2_FB3_Msk

#define	CAN_F2R2_FB4_Pos (4U)

#define	CAN_F2R2_FB4_Msk (0x1UL << CAN_F2R2_FB4_Pos)

#define	CAN_F2R2_FB4 CAN_F2R2_FB4_Msk

#define	CAN_F2R2_FB5_Pos (5U)

#define	CAN_F2R2_FB5_Msk (0x1UL << CAN_F2R2_FB5_Pos)

#define	CAN_F2R2_FB5 CAN_F2R2_FB5_Msk

#define	CAN_F2R2_FB6_Pos (6U)

#define	CAN_F2R2_FB6_Msk (0x1UL << CAN_F2R2_FB6_Pos)

#define	CAN_F2R2_FB6 CAN_F2R2_FB6_Msk

#define	CAN_F2R2_FB7_Pos (7U)

#define	CAN_F2R2_FB7_Msk (0x1UL << CAN_F2R2_FB7_Pos)

#define	CAN_F2R2_FB7 CAN_F2R2_FB7_Msk

#define	CAN_F2R2_FB8_Pos (8U)

#define	CAN_F2R2_FB8_Msk (0x1UL << CAN_F2R2_FB8_Pos)

#define	CAN_F2R2_FB8 CAN_F2R2_FB8_Msk

#define	CAN_F2R2_FB9_Pos (9U)

#define	CAN_F2R2_FB9_Msk (0x1UL << CAN_F2R2_FB9_Pos)

#define	CAN_F2R2_FB9 CAN_F2R2_FB9_Msk

#define	CAN_F2R2_FB10_Pos (10U)

#define	CAN_F2R2_FB10_Msk (0x1UL << CAN_F2R2_FB10_Pos)

#define	CAN_F2R2_FB10 CAN_F2R2_FB10_Msk

#define	CAN_F2R2_FB11_Pos (11U)

#define	CAN_F2R2_FB11_Msk (0x1UL << CAN_F2R2_FB11_Pos)

#define	CAN_F2R2_FB11 CAN_F2R2_FB11_Msk

#define	CAN_F2R2_FB12_Pos (12U)

#define	CAN_F2R2_FB12_Msk (0x1UL << CAN_F2R2_FB12_Pos)

#define	CAN_F2R2_FB12 CAN_F2R2_FB12_Msk

#define	CAN_F2R2_FB13_Pos (13U)

#define	CAN_F2R2_FB13_Msk (0x1UL << CAN_F2R2_FB13_Pos)

#define	CAN_F2R2_FB13 CAN_F2R2_FB13_Msk

#define	CAN_F2R2_FB14_Pos (14U)

#define	CAN_F2R2_FB14_Msk (0x1UL << CAN_F2R2_FB14_Pos)

#define	CAN_F2R2_FB14 CAN_F2R2_FB14_Msk

#define	CAN_F2R2_FB15_Pos (15U)

#define	CAN_F2R2_FB15_Msk (0x1UL << CAN_F2R2_FB15_Pos)

#define	CAN_F2R2_FB15 CAN_F2R2_FB15_Msk

#define	CAN_F2R2_FB16_Pos (16U)

#define	CAN_F2R2_FB16_Msk (0x1UL << CAN_F2R2_FB16_Pos)

#define	CAN_F2R2_FB16 CAN_F2R2_FB16_Msk

#define	CAN_F2R2_FB17_Pos (17U)

#define	CAN_F2R2_FB17_Msk (0x1UL << CAN_F2R2_FB17_Pos)

#define	CAN_F2R2_FB17 CAN_F2R2_FB17_Msk

#define	CAN_F2R2_FB18_Pos (18U)

#define	CAN_F2R2_FB18_Msk (0x1UL << CAN_F2R2_FB18_Pos)

#define	CAN_F2R2_FB18 CAN_F2R2_FB18_Msk

#define	CAN_F2R2_FB19_Pos (19U)

#define	CAN_F2R2_FB19_Msk (0x1UL << CAN_F2R2_FB19_Pos)

#define	CAN_F2R2_FB19 CAN_F2R2_FB19_Msk

#define	CAN_F2R2_FB20_Pos (20U)

#define	CAN_F2R2_FB20_Msk (0x1UL << CAN_F2R2_FB20_Pos)

#define	CAN_F2R2_FB20 CAN_F2R2_FB20_Msk

#define	CAN_F2R2_FB21_Pos (21U)

#define	CAN_F2R2_FB21_Msk (0x1UL << CAN_F2R2_FB21_Pos)

#define	CAN_F2R2_FB21 CAN_F2R2_FB21_Msk

#define	CAN_F2R2_FB22_Pos (22U)

#define	CAN_F2R2_FB22_Msk (0x1UL << CAN_F2R2_FB22_Pos)

#define	CAN_F2R2_FB22 CAN_F2R2_FB22_Msk

#define	CAN_F2R2_FB23_Pos (23U)

#define	CAN_F2R2_FB23_Msk (0x1UL << CAN_F2R2_FB23_Pos)

#define	CAN_F2R2_FB23 CAN_F2R2_FB23_Msk

#define	CAN_F2R2_FB24_Pos (24U)

#define	CAN_F2R2_FB24_Msk (0x1UL << CAN_F2R2_FB24_Pos)

#define	CAN_F2R2_FB24 CAN_F2R2_FB24_Msk

#define	CAN_F2R2_FB25_Pos (25U)

#define	CAN_F2R2_FB25_Msk (0x1UL << CAN_F2R2_FB25_Pos)

#define	CAN_F2R2_FB25 CAN_F2R2_FB25_Msk

#define	CAN_F2R2_FB26_Pos (26U)

#define	CAN_F2R2_FB26_Msk (0x1UL << CAN_F2R2_FB26_Pos)

#define	CAN_F2R2_FB26 CAN_F2R2_FB26_Msk

#define	CAN_F2R2_FB27_Pos (27U)

#define	CAN_F2R2_FB27_Msk (0x1UL << CAN_F2R2_FB27_Pos)

#define	CAN_F2R2_FB27 CAN_F2R2_FB27_Msk

#define	CAN_F2R2_FB28_Pos (28U)

#define	CAN_F2R2_FB28_Msk (0x1UL << CAN_F2R2_FB28_Pos)

#define	CAN_F2R2_FB28 CAN_F2R2_FB28_Msk

#define	CAN_F2R2_FB29_Pos (29U)

#define	CAN_F2R2_FB29_Msk (0x1UL << CAN_F2R2_FB29_Pos)

#define	CAN_F2R2_FB29 CAN_F2R2_FB29_Msk

#define	CAN_F2R2_FB30_Pos (30U)

#define	CAN_F2R2_FB30_Msk (0x1UL << CAN_F2R2_FB30_Pos)

#define	CAN_F2R2_FB30 CAN_F2R2_FB30_Msk

#define	CAN_F2R2_FB31_Pos (31U)

#define	CAN_F2R2_FB31_Msk (0x1UL << CAN_F2R2_FB31_Pos)

#define	CAN_F2R2_FB31 CAN_F2R2_FB31_Msk

#define	CAN_F3R2_FB0_Pos (0U)

#define	CAN_F3R2_FB0_Msk (0x1UL << CAN_F3R2_FB0_Pos)

#define	CAN_F3R2_FB0 CAN_F3R2_FB0_Msk

#define	CAN_F3R2_FB1_Pos (1U)

#define	CAN_F3R2_FB1_Msk (0x1UL << CAN_F3R2_FB1_Pos)

#define	CAN_F3R2_FB1 CAN_F3R2_FB1_Msk

#define	CAN_F3R2_FB2_Pos (2U)

#define	CAN_F3R2_FB2_Msk (0x1UL << CAN_F3R2_FB2_Pos)

#define	CAN_F3R2_FB2 CAN_F3R2_FB2_Msk

#define	CAN_F3R2_FB3_Pos (3U)

#define	CAN_F3R2_FB3_Msk (0x1UL << CAN_F3R2_FB3_Pos)

#define	CAN_F3R2_FB3 CAN_F3R2_FB3_Msk

#define	CAN_F3R2_FB4_Pos (4U)

#define	CAN_F3R2_FB4_Msk (0x1UL << CAN_F3R2_FB4_Pos)

#define	CAN_F3R2_FB4 CAN_F3R2_FB4_Msk

#define	CAN_F3R2_FB5_Pos (5U)

#define	CAN_F3R2_FB5_Msk (0x1UL << CAN_F3R2_FB5_Pos)

#define	CAN_F3R2_FB5 CAN_F3R2_FB5_Msk

#define	CAN_F3R2_FB6_Pos (6U)

#define	CAN_F3R2_FB6_Msk (0x1UL << CAN_F3R2_FB6_Pos)

#define	CAN_F3R2_FB6 CAN_F3R2_FB6_Msk

#define	CAN_F3R2_FB7_Pos (7U)

#define	CAN_F3R2_FB7_Msk (0x1UL << CAN_F3R2_FB7_Pos)

#define	CAN_F3R2_FB7 CAN_F3R2_FB7_Msk

#define	CAN_F3R2_FB8_Pos (8U)

#define	CAN_F3R2_FB8_Msk (0x1UL << CAN_F3R2_FB8_Pos)

#define	CAN_F3R2_FB8 CAN_F3R2_FB8_Msk

#define	CAN_F3R2_FB9_Pos (9U)

#define	CAN_F3R2_FB9_Msk (0x1UL << CAN_F3R2_FB9_Pos)

#define	CAN_F3R2_FB9 CAN_F3R2_FB9_Msk

#define	CAN_F3R2_FB10_Pos (10U)

#define	CAN_F3R2_FB10_Msk (0x1UL << CAN_F3R2_FB10_Pos)

#define	CAN_F3R2_FB10 CAN_F3R2_FB10_Msk

#define	CAN_F3R2_FB11_Pos (11U)

#define	CAN_F3R2_FB11_Msk (0x1UL << CAN_F3R2_FB11_Pos)

#define	CAN_F3R2_FB11 CAN_F3R2_FB11_Msk

#define	CAN_F3R2_FB12_Pos (12U)

#define	CAN_F3R2_FB12_Msk (0x1UL << CAN_F3R2_FB12_Pos)

#define	CAN_F3R2_FB12 CAN_F3R2_FB12_Msk

#define	CAN_F3R2_FB13_Pos (13U)

#define	CAN_F3R2_FB13_Msk (0x1UL << CAN_F3R2_FB13_Pos)

#define	CAN_F3R2_FB13 CAN_F3R2_FB13_Msk

#define	CAN_F3R2_FB14_Pos (14U)

#define	CAN_F3R2_FB14_Msk (0x1UL << CAN_F3R2_FB14_Pos)

#define	CAN_F3R2_FB14 CAN_F3R2_FB14_Msk

#define	CAN_F3R2_FB15_Pos (15U)

#define	CAN_F3R2_FB15_Msk (0x1UL << CAN_F3R2_FB15_Pos)

#define	CAN_F3R2_FB15 CAN_F3R2_FB15_Msk

#define	CAN_F3R2_FB16_Pos (16U)

#define	CAN_F3R2_FB16_Msk (0x1UL << CAN_F3R2_FB16_Pos)

#define	CAN_F3R2_FB16 CAN_F3R2_FB16_Msk

#define	CAN_F3R2_FB17_Pos (17U)

#define	CAN_F3R2_FB17_Msk (0x1UL << CAN_F3R2_FB17_Pos)

#define	CAN_F3R2_FB17 CAN_F3R2_FB17_Msk

#define	CAN_F3R2_FB18_Pos (18U)

#define	CAN_F3R2_FB18_Msk (0x1UL << CAN_F3R2_FB18_Pos)

#define	CAN_F3R2_FB18 CAN_F3R2_FB18_Msk

#define	CAN_F3R2_FB19_Pos (19U)

#define	CAN_F3R2_FB19_Msk (0x1UL << CAN_F3R2_FB19_Pos)

#define	CAN_F3R2_FB19 CAN_F3R2_FB19_Msk

#define	CAN_F3R2_FB20_Pos (20U)

#define	CAN_F3R2_FB20_Msk (0x1UL << CAN_F3R2_FB20_Pos)

#define	CAN_F3R2_FB20 CAN_F3R2_FB20_Msk

#define	CAN_F3R2_FB21_Pos (21U)

#define	CAN_F3R2_FB21_Msk (0x1UL << CAN_F3R2_FB21_Pos)

#define	CAN_F3R2_FB21 CAN_F3R2_FB21_Msk

#define	CAN_F3R2_FB22_Pos (22U)

#define	CAN_F3R2_FB22_Msk (0x1UL << CAN_F3R2_FB22_Pos)

#define	CAN_F3R2_FB22 CAN_F3R2_FB22_Msk

#define	CAN_F3R2_FB23_Pos (23U)

#define	CAN_F3R2_FB23_Msk (0x1UL << CAN_F3R2_FB23_Pos)

#define	CAN_F3R2_FB23 CAN_F3R2_FB23_Msk

#define	CAN_F3R2_FB24_Pos (24U)

#define	CAN_F3R2_FB24_Msk (0x1UL << CAN_F3R2_FB24_Pos)

#define	CAN_F3R2_FB24 CAN_F3R2_FB24_Msk

#define	CAN_F3R2_FB25_Pos (25U)

#define	CAN_F3R2_FB25_Msk (0x1UL << CAN_F3R2_FB25_Pos)

#define	CAN_F3R2_FB25 CAN_F3R2_FB25_Msk

#define	CAN_F3R2_FB26_Pos (26U)

#define	CAN_F3R2_FB26_Msk (0x1UL << CAN_F3R2_FB26_Pos)

#define	CAN_F3R2_FB26 CAN_F3R2_FB26_Msk

#define	CAN_F3R2_FB27_Pos (27U)

#define	CAN_F3R2_FB27_Msk (0x1UL << CAN_F3R2_FB27_Pos)

#define	CAN_F3R2_FB27 CAN_F3R2_FB27_Msk

#define	CAN_F3R2_FB28_Pos (28U)

#define	CAN_F3R2_FB28_Msk (0x1UL << CAN_F3R2_FB28_Pos)

#define	CAN_F3R2_FB28 CAN_F3R2_FB28_Msk

#define	CAN_F3R2_FB29_Pos (29U)

#define	CAN_F3R2_FB29_Msk (0x1UL << CAN_F3R2_FB29_Pos)

#define	CAN_F3R2_FB29 CAN_F3R2_FB29_Msk

#define	CAN_F3R2_FB30_Pos (30U)

#define	CAN_F3R2_FB30_Msk (0x1UL << CAN_F3R2_FB30_Pos)

#define	CAN_F3R2_FB30 CAN_F3R2_FB30_Msk

#define	CAN_F3R2_FB31_Pos (31U)

#define	CAN_F3R2_FB31_Msk (0x1UL << CAN_F3R2_FB31_Pos)

#define	CAN_F3R2_FB31 CAN_F3R2_FB31_Msk

#define	CAN_F4R2_FB0_Pos (0U)

#define	CAN_F4R2_FB0_Msk (0x1UL << CAN_F4R2_FB0_Pos)

#define	CAN_F4R2_FB0 CAN_F4R2_FB0_Msk

#define	CAN_F4R2_FB1_Pos (1U)

#define	CAN_F4R2_FB1_Msk (0x1UL << CAN_F4R2_FB1_Pos)

#define	CAN_F4R2_FB1 CAN_F4R2_FB1_Msk

#define	CAN_F4R2_FB2_Pos (2U)

#define	CAN_F4R2_FB2_Msk (0x1UL << CAN_F4R2_FB2_Pos)

#define	CAN_F4R2_FB2 CAN_F4R2_FB2_Msk

#define	CAN_F4R2_FB3_Pos (3U)

#define	CAN_F4R2_FB3_Msk (0x1UL << CAN_F4R2_FB3_Pos)

#define	CAN_F4R2_FB3 CAN_F4R2_FB3_Msk

#define	CAN_F4R2_FB4_Pos (4U)

#define	CAN_F4R2_FB4_Msk (0x1UL << CAN_F4R2_FB4_Pos)

#define	CAN_F4R2_FB4 CAN_F4R2_FB4_Msk

#define	CAN_F4R2_FB5_Pos (5U)

#define	CAN_F4R2_FB5_Msk (0x1UL << CAN_F4R2_FB5_Pos)

#define	CAN_F4R2_FB5 CAN_F4R2_FB5_Msk

#define	CAN_F4R2_FB6_Pos (6U)

#define	CAN_F4R2_FB6_Msk (0x1UL << CAN_F4R2_FB6_Pos)

#define	CAN_F4R2_FB6 CAN_F4R2_FB6_Msk

#define	CAN_F4R2_FB7_Pos (7U)

#define	CAN_F4R2_FB7_Msk (0x1UL << CAN_F4R2_FB7_Pos)

#define	CAN_F4R2_FB7 CAN_F4R2_FB7_Msk

#define	CAN_F4R2_FB8_Pos (8U)

#define	CAN_F4R2_FB8_Msk (0x1UL << CAN_F4R2_FB8_Pos)

#define	CAN_F4R2_FB8 CAN_F4R2_FB8_Msk

#define	CAN_F4R2_FB9_Pos (9U)

#define	CAN_F4R2_FB9_Msk (0x1UL << CAN_F4R2_FB9_Pos)

#define	CAN_F4R2_FB9 CAN_F4R2_FB9_Msk

#define	CAN_F4R2_FB10_Pos (10U)

#define	CAN_F4R2_FB10_Msk (0x1UL << CAN_F4R2_FB10_Pos)

#define	CAN_F4R2_FB10 CAN_F4R2_FB10_Msk

#define	CAN_F4R2_FB11_Pos (11U)

#define	CAN_F4R2_FB11_Msk (0x1UL << CAN_F4R2_FB11_Pos)

#define	CAN_F4R2_FB11 CAN_F4R2_FB11_Msk

#define	CAN_F4R2_FB12_Pos (12U)

#define	CAN_F4R2_FB12_Msk (0x1UL << CAN_F4R2_FB12_Pos)

#define	CAN_F4R2_FB12 CAN_F4R2_FB12_Msk

#define	CAN_F4R2_FB13_Pos (13U)

#define	CAN_F4R2_FB13_Msk (0x1UL << CAN_F4R2_FB13_Pos)

#define	CAN_F4R2_FB13 CAN_F4R2_FB13_Msk

#define	CAN_F4R2_FB14_Pos (14U)

#define	CAN_F4R2_FB14_Msk (0x1UL << CAN_F4R2_FB14_Pos)

#define	CAN_F4R2_FB14 CAN_F4R2_FB14_Msk

#define	CAN_F4R2_FB15_Pos (15U)

#define	CAN_F4R2_FB15_Msk (0x1UL << CAN_F4R2_FB15_Pos)

#define	CAN_F4R2_FB15 CAN_F4R2_FB15_Msk

#define	CAN_F4R2_FB16_Pos (16U)

#define	CAN_F4R2_FB16_Msk (0x1UL << CAN_F4R2_FB16_Pos)

#define	CAN_F4R2_FB16 CAN_F4R2_FB16_Msk

#define	CAN_F4R2_FB17_Pos (17U)

#define	CAN_F4R2_FB17_Msk (0x1UL << CAN_F4R2_FB17_Pos)

#define	CAN_F4R2_FB17 CAN_F4R2_FB17_Msk

#define	CAN_F4R2_FB18_Pos (18U)

#define	CAN_F4R2_FB18_Msk (0x1UL << CAN_F4R2_FB18_Pos)

#define	CAN_F4R2_FB18 CAN_F4R2_FB18_Msk

#define	CAN_F4R2_FB19_Pos (19U)

#define	CAN_F4R2_FB19_Msk (0x1UL << CAN_F4R2_FB19_Pos)

#define	CAN_F4R2_FB19 CAN_F4R2_FB19_Msk

#define	CAN_F4R2_FB20_Pos (20U)

#define	CAN_F4R2_FB20_Msk (0x1UL << CAN_F4R2_FB20_Pos)

#define	CAN_F4R2_FB20 CAN_F4R2_FB20_Msk

#define	CAN_F4R2_FB21_Pos (21U)

#define	CAN_F4R2_FB21_Msk (0x1UL << CAN_F4R2_FB21_Pos)

#define	CAN_F4R2_FB21 CAN_F4R2_FB21_Msk

#define	CAN_F4R2_FB22_Pos (22U)

#define	CAN_F4R2_FB22_Msk (0x1UL << CAN_F4R2_FB22_Pos)

#define	CAN_F4R2_FB22 CAN_F4R2_FB22_Msk

#define	CAN_F4R2_FB23_Pos (23U)

#define	CAN_F4R2_FB23_Msk (0x1UL << CAN_F4R2_FB23_Pos)

#define	CAN_F4R2_FB23 CAN_F4R2_FB23_Msk

#define	CAN_F4R2_FB24_Pos (24U)

#define	CAN_F4R2_FB24_Msk (0x1UL << CAN_F4R2_FB24_Pos)

#define	CAN_F4R2_FB24 CAN_F4R2_FB24_Msk

#define	CAN_F4R2_FB25_Pos (25U)

#define	CAN_F4R2_FB25_Msk (0x1UL << CAN_F4R2_FB25_Pos)

#define	CAN_F4R2_FB25 CAN_F4R2_FB25_Msk

#define	CAN_F4R2_FB26_Pos (26U)

#define	CAN_F4R2_FB26_Msk (0x1UL << CAN_F4R2_FB26_Pos)

#define	CAN_F4R2_FB26 CAN_F4R2_FB26_Msk

#define	CAN_F4R2_FB27_Pos (27U)

#define	CAN_F4R2_FB27_Msk (0x1UL << CAN_F4R2_FB27_Pos)

#define	CAN_F4R2_FB27 CAN_F4R2_FB27_Msk

#define	CAN_F4R2_FB28_Pos (28U)

#define	CAN_F4R2_FB28_Msk (0x1UL << CAN_F4R2_FB28_Pos)

#define	CAN_F4R2_FB28 CAN_F4R2_FB28_Msk

#define	CAN_F4R2_FB29_Pos (29U)

#define	CAN_F4R2_FB29_Msk (0x1UL << CAN_F4R2_FB29_Pos)

#define	CAN_F4R2_FB29 CAN_F4R2_FB29_Msk

#define	CAN_F4R2_FB30_Pos (30U)

#define	CAN_F4R2_FB30_Msk (0x1UL << CAN_F4R2_FB30_Pos)

#define	CAN_F4R2_FB30 CAN_F4R2_FB30_Msk

#define	CAN_F4R2_FB31_Pos (31U)

#define	CAN_F4R2_FB31_Msk (0x1UL << CAN_F4R2_FB31_Pos)

#define	CAN_F4R2_FB31 CAN_F4R2_FB31_Msk

#define	CAN_F5R2_FB0_Pos (0U)

#define	CAN_F5R2_FB0_Msk (0x1UL << CAN_F5R2_FB0_Pos)

#define	CAN_F5R2_FB0 CAN_F5R2_FB0_Msk

#define	CAN_F5R2_FB1_Pos (1U)

#define	CAN_F5R2_FB1_Msk (0x1UL << CAN_F5R2_FB1_Pos)

#define	CAN_F5R2_FB1 CAN_F5R2_FB1_Msk

#define	CAN_F5R2_FB2_Pos (2U)

#define	CAN_F5R2_FB2_Msk (0x1UL << CAN_F5R2_FB2_Pos)

#define	CAN_F5R2_FB2 CAN_F5R2_FB2_Msk

#define	CAN_F5R2_FB3_Pos (3U)

#define	CAN_F5R2_FB3_Msk (0x1UL << CAN_F5R2_FB3_Pos)

#define	CAN_F5R2_FB3 CAN_F5R2_FB3_Msk

#define	CAN_F5R2_FB4_Pos (4U)

#define	CAN_F5R2_FB4_Msk (0x1UL << CAN_F5R2_FB4_Pos)

#define	CAN_F5R2_FB4 CAN_F5R2_FB4_Msk

#define	CAN_F5R2_FB5_Pos (5U)

#define	CAN_F5R2_FB5_Msk (0x1UL << CAN_F5R2_FB5_Pos)

#define	CAN_F5R2_FB5 CAN_F5R2_FB5_Msk

#define	CAN_F5R2_FB6_Pos (6U)

#define	CAN_F5R2_FB6_Msk (0x1UL << CAN_F5R2_FB6_Pos)

#define	CAN_F5R2_FB6 CAN_F5R2_FB6_Msk

#define	CAN_F5R2_FB7_Pos (7U)

#define	CAN_F5R2_FB7_Msk (0x1UL << CAN_F5R2_FB7_Pos)

#define	CAN_F5R2_FB7 CAN_F5R2_FB7_Msk

#define	CAN_F5R2_FB8_Pos (8U)

#define	CAN_F5R2_FB8_Msk (0x1UL << CAN_F5R2_FB8_Pos)

#define	CAN_F5R2_FB8 CAN_F5R2_FB8_Msk

#define	CAN_F5R2_FB9_Pos (9U)

#define	CAN_F5R2_FB9_Msk (0x1UL << CAN_F5R2_FB9_Pos)

#define	CAN_F5R2_FB9 CAN_F5R2_FB9_Msk

#define	CAN_F5R2_FB10_Pos (10U)

#define	CAN_F5R2_FB10_Msk (0x1UL << CAN_F5R2_FB10_Pos)

#define	CAN_F5R2_FB10 CAN_F5R2_FB10_Msk

#define	CAN_F5R2_FB11_Pos (11U)

#define	CAN_F5R2_FB11_Msk (0x1UL << CAN_F5R2_FB11_Pos)

#define	CAN_F5R2_FB11 CAN_F5R2_FB11_Msk

#define	CAN_F5R2_FB12_Pos (12U)

#define	CAN_F5R2_FB12_Msk (0x1UL << CAN_F5R2_FB12_Pos)

#define	CAN_F5R2_FB12 CAN_F5R2_FB12_Msk

#define	CAN_F5R2_FB13_Pos (13U)

#define	CAN_F5R2_FB13_Msk (0x1UL << CAN_F5R2_FB13_Pos)

#define	CAN_F5R2_FB13 CAN_F5R2_FB13_Msk

#define	CAN_F5R2_FB14_Pos (14U)

#define	CAN_F5R2_FB14_Msk (0x1UL << CAN_F5R2_FB14_Pos)

#define	CAN_F5R2_FB14 CAN_F5R2_FB14_Msk

#define	CAN_F5R2_FB15_Pos (15U)

#define	CAN_F5R2_FB15_Msk (0x1UL << CAN_F5R2_FB15_Pos)

#define	CAN_F5R2_FB15 CAN_F5R2_FB15_Msk

#define	CAN_F5R2_FB16_Pos (16U)

#define	CAN_F5R2_FB16_Msk (0x1UL << CAN_F5R2_FB16_Pos)

#define	CAN_F5R2_FB16 CAN_F5R2_FB16_Msk

#define	CAN_F5R2_FB17_Pos (17U)

#define	CAN_F5R2_FB17_Msk (0x1UL << CAN_F5R2_FB17_Pos)

#define	CAN_F5R2_FB17 CAN_F5R2_FB17_Msk

#define	CAN_F5R2_FB18_Pos (18U)

#define	CAN_F5R2_FB18_Msk (0x1UL << CAN_F5R2_FB18_Pos)

#define	CAN_F5R2_FB18 CAN_F5R2_FB18_Msk

#define	CAN_F5R2_FB19_Pos (19U)

#define	CAN_F5R2_FB19_Msk (0x1UL << CAN_F5R2_FB19_Pos)

#define	CAN_F5R2_FB19 CAN_F5R2_FB19_Msk

#define	CAN_F5R2_FB20_Pos (20U)

#define	CAN_F5R2_FB20_Msk (0x1UL << CAN_F5R2_FB20_Pos)

#define	CAN_F5R2_FB20 CAN_F5R2_FB20_Msk

#define	CAN_F5R2_FB21_Pos (21U)

#define	CAN_F5R2_FB21_Msk (0x1UL << CAN_F5R2_FB21_Pos)

#define	CAN_F5R2_FB21 CAN_F5R2_FB21_Msk

#define	CAN_F5R2_FB22_Pos (22U)

#define	CAN_F5R2_FB22_Msk (0x1UL << CAN_F5R2_FB22_Pos)

#define	CAN_F5R2_FB22 CAN_F5R2_FB22_Msk

#define	CAN_F5R2_FB23_Pos (23U)

#define	CAN_F5R2_FB23_Msk (0x1UL << CAN_F5R2_FB23_Pos)

#define	CAN_F5R2_FB23 CAN_F5R2_FB23_Msk

#define	CAN_F5R2_FB24_Pos (24U)

#define	CAN_F5R2_FB24_Msk (0x1UL << CAN_F5R2_FB24_Pos)

#define	CAN_F5R2_FB24 CAN_F5R2_FB24_Msk

#define	CAN_F5R2_FB25_Pos (25U)

#define	CAN_F5R2_FB25_Msk (0x1UL << CAN_F5R2_FB25_Pos)

#define	CAN_F5R2_FB25 CAN_F5R2_FB25_Msk

#define	CAN_F5R2_FB26_Pos (26U)

#define	CAN_F5R2_FB26_Msk (0x1UL << CAN_F5R2_FB26_Pos)

#define	CAN_F5R2_FB26 CAN_F5R2_FB26_Msk

#define	CAN_F5R2_FB27_Pos (27U)

#define	CAN_F5R2_FB27_Msk (0x1UL << CAN_F5R2_FB27_Pos)

#define	CAN_F5R2_FB27 CAN_F5R2_FB27_Msk

#define	CAN_F5R2_FB28_Pos (28U)

#define	CAN_F5R2_FB28_Msk (0x1UL << CAN_F5R2_FB28_Pos)

#define	CAN_F5R2_FB28 CAN_F5R2_FB28_Msk

#define	CAN_F5R2_FB29_Pos (29U)

#define	CAN_F5R2_FB29_Msk (0x1UL << CAN_F5R2_FB29_Pos)

#define	CAN_F5R2_FB29 CAN_F5R2_FB29_Msk

#define	CAN_F5R2_FB30_Pos (30U)

#define	CAN_F5R2_FB30_Msk (0x1UL << CAN_F5R2_FB30_Pos)

#define	CAN_F5R2_FB30 CAN_F5R2_FB30_Msk

#define	CAN_F5R2_FB31_Pos (31U)

#define	CAN_F5R2_FB31_Msk (0x1UL << CAN_F5R2_FB31_Pos)

#define	CAN_F5R2_FB31 CAN_F5R2_FB31_Msk

#define	CAN_F6R2_FB0_Pos (0U)

#define	CAN_F6R2_FB0_Msk (0x1UL << CAN_F6R2_FB0_Pos)

#define	CAN_F6R2_FB0 CAN_F6R2_FB0_Msk

#define	CAN_F6R2_FB1_Pos (1U)

#define	CAN_F6R2_FB1_Msk (0x1UL << CAN_F6R2_FB1_Pos)

#define	CAN_F6R2_FB1 CAN_F6R2_FB1_Msk

#define	CAN_F6R2_FB2_Pos (2U)

#define	CAN_F6R2_FB2_Msk (0x1UL << CAN_F6R2_FB2_Pos)

#define	CAN_F6R2_FB2 CAN_F6R2_FB2_Msk

#define	CAN_F6R2_FB3_Pos (3U)

#define	CAN_F6R2_FB3_Msk (0x1UL << CAN_F6R2_FB3_Pos)

#define	CAN_F6R2_FB3 CAN_F6R2_FB3_Msk

#define	CAN_F6R2_FB4_Pos (4U)

#define	CAN_F6R2_FB4_Msk (0x1UL << CAN_F6R2_FB4_Pos)

#define	CAN_F6R2_FB4 CAN_F6R2_FB4_Msk

#define	CAN_F6R2_FB5_Pos (5U)

#define	CAN_F6R2_FB5_Msk (0x1UL << CAN_F6R2_FB5_Pos)

#define	CAN_F6R2_FB5 CAN_F6R2_FB5_Msk

#define	CAN_F6R2_FB6_Pos (6U)

#define	CAN_F6R2_FB6_Msk (0x1UL << CAN_F6R2_FB6_Pos)

#define	CAN_F6R2_FB6 CAN_F6R2_FB6_Msk

#define	CAN_F6R2_FB7_Pos (7U)

#define	CAN_F6R2_FB7_Msk (0x1UL << CAN_F6R2_FB7_Pos)

#define	CAN_F6R2_FB7 CAN_F6R2_FB7_Msk

#define	CAN_F6R2_FB8_Pos (8U)

#define	CAN_F6R2_FB8_Msk (0x1UL << CAN_F6R2_FB8_Pos)

#define	CAN_F6R2_FB8 CAN_F6R2_FB8_Msk

#define	CAN_F6R2_FB9_Pos (9U)

#define	CAN_F6R2_FB9_Msk (0x1UL << CAN_F6R2_FB9_Pos)

#define	CAN_F6R2_FB9 CAN_F6R2_FB9_Msk

#define	CAN_F6R2_FB10_Pos (10U)

#define	CAN_F6R2_FB10_Msk (0x1UL << CAN_F6R2_FB10_Pos)

#define	CAN_F6R2_FB10 CAN_F6R2_FB10_Msk

#define	CAN_F6R2_FB11_Pos (11U)

#define	CAN_F6R2_FB11_Msk (0x1UL << CAN_F6R2_FB11_Pos)

#define	CAN_F6R2_FB11 CAN_F6R2_FB11_Msk

#define	CAN_F6R2_FB12_Pos (12U)

#define	CAN_F6R2_FB12_Msk (0x1UL << CAN_F6R2_FB12_Pos)

#define	CAN_F6R2_FB12 CAN_F6R2_FB12_Msk

#define	CAN_F6R2_FB13_Pos (13U)

#define	CAN_F6R2_FB13_Msk (0x1UL << CAN_F6R2_FB13_Pos)

#define	CAN_F6R2_FB13 CAN_F6R2_FB13_Msk

#define	CAN_F6R2_FB14_Pos (14U)

#define	CAN_F6R2_FB14_Msk (0x1UL << CAN_F6R2_FB14_Pos)

#define	CAN_F6R2_FB14 CAN_F6R2_FB14_Msk

#define	CAN_F6R2_FB15_Pos (15U)

#define	CAN_F6R2_FB15_Msk (0x1UL << CAN_F6R2_FB15_Pos)

#define	CAN_F6R2_FB15 CAN_F6R2_FB15_Msk

#define	CAN_F6R2_FB16_Pos (16U)

#define	CAN_F6R2_FB16_Msk (0x1UL << CAN_F6R2_FB16_Pos)

#define	CAN_F6R2_FB16 CAN_F6R2_FB16_Msk

#define	CAN_F6R2_FB17_Pos (17U)

#define	CAN_F6R2_FB17_Msk (0x1UL << CAN_F6R2_FB17_Pos)

#define	CAN_F6R2_FB17 CAN_F6R2_FB17_Msk

#define	CAN_F6R2_FB18_Pos (18U)

#define	CAN_F6R2_FB18_Msk (0x1UL << CAN_F6R2_FB18_Pos)

#define	CAN_F6R2_FB18 CAN_F6R2_FB18_Msk

#define	CAN_F6R2_FB19_Pos (19U)

#define	CAN_F6R2_FB19_Msk (0x1UL << CAN_F6R2_FB19_Pos)

#define	CAN_F6R2_FB19 CAN_F6R2_FB19_Msk

#define	CAN_F6R2_FB20_Pos (20U)

#define	CAN_F6R2_FB20_Msk (0x1UL << CAN_F6R2_FB20_Pos)

#define	CAN_F6R2_FB20 CAN_F6R2_FB20_Msk

#define	CAN_F6R2_FB21_Pos (21U)

#define	CAN_F6R2_FB21_Msk (0x1UL << CAN_F6R2_FB21_Pos)

#define	CAN_F6R2_FB21 CAN_F6R2_FB21_Msk

#define	CAN_F6R2_FB22_Pos (22U)

#define	CAN_F6R2_FB22_Msk (0x1UL << CAN_F6R2_FB22_Pos)

#define	CAN_F6R2_FB22 CAN_F6R2_FB22_Msk

#define	CAN_F6R2_FB23_Pos (23U)

#define	CAN_F6R2_FB23_Msk (0x1UL << CAN_F6R2_FB23_Pos)

#define	CAN_F6R2_FB23 CAN_F6R2_FB23_Msk

#define	CAN_F6R2_FB24_Pos (24U)

#define	CAN_F6R2_FB24_Msk (0x1UL << CAN_F6R2_FB24_Pos)

#define	CAN_F6R2_FB24 CAN_F6R2_FB24_Msk

#define	CAN_F6R2_FB25_Pos (25U)

#define	CAN_F6R2_FB25_Msk (0x1UL << CAN_F6R2_FB25_Pos)

#define	CAN_F6R2_FB25 CAN_F6R2_FB25_Msk

#define	CAN_F6R2_FB26_Pos (26U)

#define	CAN_F6R2_FB26_Msk (0x1UL << CAN_F6R2_FB26_Pos)

#define	CAN_F6R2_FB26 CAN_F6R2_FB26_Msk

#define	CAN_F6R2_FB27_Pos (27U)

#define	CAN_F6R2_FB27_Msk (0x1UL << CAN_F6R2_FB27_Pos)

#define	CAN_F6R2_FB27 CAN_F6R2_FB27_Msk

#define	CAN_F6R2_FB28_Pos (28U)

#define	CAN_F6R2_FB28_Msk (0x1UL << CAN_F6R2_FB28_Pos)

#define	CAN_F6R2_FB28 CAN_F6R2_FB28_Msk

#define	CAN_F6R2_FB29_Pos (29U)

#define	CAN_F6R2_FB29_Msk (0x1UL << CAN_F6R2_FB29_Pos)

#define	CAN_F6R2_FB29 CAN_F6R2_FB29_Msk

#define	CAN_F6R2_FB30_Pos (30U)

#define	CAN_F6R2_FB30_Msk (0x1UL << CAN_F6R2_FB30_Pos)

#define	CAN_F6R2_FB30 CAN_F6R2_FB30_Msk

#define	CAN_F6R2_FB31_Pos (31U)

#define	CAN_F6R2_FB31_Msk (0x1UL << CAN_F6R2_FB31_Pos)

#define	CAN_F6R2_FB31 CAN_F6R2_FB31_Msk

#define	CAN_F7R2_FB0_Pos (0U)

#define	CAN_F7R2_FB0_Msk (0x1UL << CAN_F7R2_FB0_Pos)

#define	CAN_F7R2_FB0 CAN_F7R2_FB0_Msk

#define	CAN_F7R2_FB1_Pos (1U)

#define	CAN_F7R2_FB1_Msk (0x1UL << CAN_F7R2_FB1_Pos)

#define	CAN_F7R2_FB1 CAN_F7R2_FB1_Msk

#define	CAN_F7R2_FB2_Pos (2U)

#define	CAN_F7R2_FB2_Msk (0x1UL << CAN_F7R2_FB2_Pos)

#define	CAN_F7R2_FB2 CAN_F7R2_FB2_Msk

#define	CAN_F7R2_FB3_Pos (3U)

#define	CAN_F7R2_FB3_Msk (0x1UL << CAN_F7R2_FB3_Pos)

#define	CAN_F7R2_FB3 CAN_F7R2_FB3_Msk

#define	CAN_F7R2_FB4_Pos (4U)

#define	CAN_F7R2_FB4_Msk (0x1UL << CAN_F7R2_FB4_Pos)

#define	CAN_F7R2_FB4 CAN_F7R2_FB4_Msk

#define	CAN_F7R2_FB5_Pos (5U)

#define	CAN_F7R2_FB5_Msk (0x1UL << CAN_F7R2_FB5_Pos)

#define	CAN_F7R2_FB5 CAN_F7R2_FB5_Msk

#define	CAN_F7R2_FB6_Pos (6U)

#define	CAN_F7R2_FB6_Msk (0x1UL << CAN_F7R2_FB6_Pos)

#define	CAN_F7R2_FB6 CAN_F7R2_FB6_Msk

#define	CAN_F7R2_FB7_Pos (7U)

#define	CAN_F7R2_FB7_Msk (0x1UL << CAN_F7R2_FB7_Pos)

#define	CAN_F7R2_FB7 CAN_F7R2_FB7_Msk

#define	CAN_F7R2_FB8_Pos (8U)

#define	CAN_F7R2_FB8_Msk (0x1UL << CAN_F7R2_FB8_Pos)

#define	CAN_F7R2_FB8 CAN_F7R2_FB8_Msk

#define	CAN_F7R2_FB9_Pos (9U)

#define	CAN_F7R2_FB9_Msk (0x1UL << CAN_F7R2_FB9_Pos)

#define	CAN_F7R2_FB9 CAN_F7R2_FB9_Msk

#define	CAN_F7R2_FB10_Pos (10U)

#define	CAN_F7R2_FB10_Msk (0x1UL << CAN_F7R2_FB10_Pos)

#define	CAN_F7R2_FB10 CAN_F7R2_FB10_Msk

#define	CAN_F7R2_FB11_Pos (11U)

#define	CAN_F7R2_FB11_Msk (0x1UL << CAN_F7R2_FB11_Pos)

#define	CAN_F7R2_FB11 CAN_F7R2_FB11_Msk

#define	CAN_F7R2_FB12_Pos (12U)

#define	CAN_F7R2_FB12_Msk (0x1UL << CAN_F7R2_FB12_Pos)

#define	CAN_F7R2_FB12 CAN_F7R2_FB12_Msk

#define	CAN_F7R2_FB13_Pos (13U)

#define	CAN_F7R2_FB13_Msk (0x1UL << CAN_F7R2_FB13_Pos)

#define	CAN_F7R2_FB13 CAN_F7R2_FB13_Msk

#define	CAN_F7R2_FB14_Pos (14U)

#define	CAN_F7R2_FB14_Msk (0x1UL << CAN_F7R2_FB14_Pos)

#define	CAN_F7R2_FB14 CAN_F7R2_FB14_Msk

#define	CAN_F7R2_FB15_Pos (15U)

#define	CAN_F7R2_FB15_Msk (0x1UL << CAN_F7R2_FB15_Pos)

#define	CAN_F7R2_FB15 CAN_F7R2_FB15_Msk

#define	CAN_F7R2_FB16_Pos (16U)

#define	CAN_F7R2_FB16_Msk (0x1UL << CAN_F7R2_FB16_Pos)

#define	CAN_F7R2_FB16 CAN_F7R2_FB16_Msk

#define	CAN_F7R2_FB17_Pos (17U)

#define	CAN_F7R2_FB17_Msk (0x1UL << CAN_F7R2_FB17_Pos)

#define	CAN_F7R2_FB17 CAN_F7R2_FB17_Msk

#define	CAN_F7R2_FB18_Pos (18U)

#define	CAN_F7R2_FB18_Msk (0x1UL << CAN_F7R2_FB18_Pos)

#define	CAN_F7R2_FB18 CAN_F7R2_FB18_Msk

#define	CAN_F7R2_FB19_Pos (19U)

#define	CAN_F7R2_FB19_Msk (0x1UL << CAN_F7R2_FB19_Pos)

#define	CAN_F7R2_FB19 CAN_F7R2_FB19_Msk

#define	CAN_F7R2_FB20_Pos (20U)

#define	CAN_F7R2_FB20_Msk (0x1UL << CAN_F7R2_FB20_Pos)

#define	CAN_F7R2_FB20 CAN_F7R2_FB20_Msk

#define	CAN_F7R2_FB21_Pos (21U)

#define	CAN_F7R2_FB21_Msk (0x1UL << CAN_F7R2_FB21_Pos)

#define	CAN_F7R2_FB21 CAN_F7R2_FB21_Msk

#define	CAN_F7R2_FB22_Pos (22U)

#define	CAN_F7R2_FB22_Msk (0x1UL << CAN_F7R2_FB22_Pos)

#define	CAN_F7R2_FB22 CAN_F7R2_FB22_Msk

#define	CAN_F7R2_FB23_Pos (23U)

#define	CAN_F7R2_FB23_Msk (0x1UL << CAN_F7R2_FB23_Pos)

#define	CAN_F7R2_FB23 CAN_F7R2_FB23_Msk

#define	CAN_F7R2_FB24_Pos (24U)

#define	CAN_F7R2_FB24_Msk (0x1UL << CAN_F7R2_FB24_Pos)

#define	CAN_F7R2_FB24 CAN_F7R2_FB24_Msk

#define	CAN_F7R2_FB25_Pos (25U)

#define	CAN_F7R2_FB25_Msk (0x1UL << CAN_F7R2_FB25_Pos)

#define	CAN_F7R2_FB25 CAN_F7R2_FB25_Msk

#define	CAN_F7R2_FB26_Pos (26U)

#define	CAN_F7R2_FB26_Msk (0x1UL << CAN_F7R2_FB26_Pos)

#define	CAN_F7R2_FB26 CAN_F7R2_FB26_Msk

#define	CAN_F7R2_FB27_Pos (27U)

#define	CAN_F7R2_FB27_Msk (0x1UL << CAN_F7R2_FB27_Pos)

#define	CAN_F7R2_FB27 CAN_F7R2_FB27_Msk

#define	CAN_F7R2_FB28_Pos (28U)

#define	CAN_F7R2_FB28_Msk (0x1UL << CAN_F7R2_FB28_Pos)

#define	CAN_F7R2_FB28 CAN_F7R2_FB28_Msk

#define	CAN_F7R2_FB29_Pos (29U)

#define	CAN_F7R2_FB29_Msk (0x1UL << CAN_F7R2_FB29_Pos)

#define	CAN_F7R2_FB29 CAN_F7R2_FB29_Msk

#define	CAN_F7R2_FB30_Pos (30U)

#define	CAN_F7R2_FB30_Msk (0x1UL << CAN_F7R2_FB30_Pos)

#define	CAN_F7R2_FB30 CAN_F7R2_FB30_Msk

#define	CAN_F7R2_FB31_Pos (31U)

#define	CAN_F7R2_FB31_Msk (0x1UL << CAN_F7R2_FB31_Pos)

#define	CAN_F7R2_FB31 CAN_F7R2_FB31_Msk

#define	CAN_F8R2_FB0_Pos (0U)

#define	CAN_F8R2_FB0_Msk (0x1UL << CAN_F8R2_FB0_Pos)

#define	CAN_F8R2_FB0 CAN_F8R2_FB0_Msk

#define	CAN_F8R2_FB1_Pos (1U)

#define	CAN_F8R2_FB1_Msk (0x1UL << CAN_F8R2_FB1_Pos)

#define	CAN_F8R2_FB1 CAN_F8R2_FB1_Msk

#define	CAN_F8R2_FB2_Pos (2U)

#define	CAN_F8R2_FB2_Msk (0x1UL << CAN_F8R2_FB2_Pos)

#define	CAN_F8R2_FB2 CAN_F8R2_FB2_Msk

#define	CAN_F8R2_FB3_Pos (3U)

#define	CAN_F8R2_FB3_Msk (0x1UL << CAN_F8R2_FB3_Pos)

#define	CAN_F8R2_FB3 CAN_F8R2_FB3_Msk

#define	CAN_F8R2_FB4_Pos (4U)

#define	CAN_F8R2_FB4_Msk (0x1UL << CAN_F8R2_FB4_Pos)

#define	CAN_F8R2_FB4 CAN_F8R2_FB4_Msk

#define	CAN_F8R2_FB5_Pos (5U)

#define	CAN_F8R2_FB5_Msk (0x1UL << CAN_F8R2_FB5_Pos)

#define	CAN_F8R2_FB5 CAN_F8R2_FB5_Msk

#define	CAN_F8R2_FB6_Pos (6U)

#define	CAN_F8R2_FB6_Msk (0x1UL << CAN_F8R2_FB6_Pos)

#define	CAN_F8R2_FB6 CAN_F8R2_FB6_Msk

#define	CAN_F8R2_FB7_Pos (7U)

#define	CAN_F8R2_FB7_Msk (0x1UL << CAN_F8R2_FB7_Pos)

#define	CAN_F8R2_FB7 CAN_F8R2_FB7_Msk

#define	CAN_F8R2_FB8_Pos (8U)

#define	CAN_F8R2_FB8_Msk (0x1UL << CAN_F8R2_FB8_Pos)

#define	CAN_F8R2_FB8 CAN_F8R2_FB8_Msk

#define	CAN_F8R2_FB9_Pos (9U)

#define	CAN_F8R2_FB9_Msk (0x1UL << CAN_F8R2_FB9_Pos)

#define	CAN_F8R2_FB9 CAN_F8R2_FB9_Msk

#define	CAN_F8R2_FB10_Pos (10U)

#define	CAN_F8R2_FB10_Msk (0x1UL << CAN_F8R2_FB10_Pos)

#define	CAN_F8R2_FB10 CAN_F8R2_FB10_Msk

#define	CAN_F8R2_FB11_Pos (11U)

#define	CAN_F8R2_FB11_Msk (0x1UL << CAN_F8R2_FB11_Pos)

#define	CAN_F8R2_FB11 CAN_F8R2_FB11_Msk

#define	CAN_F8R2_FB12_Pos (12U)

#define	CAN_F8R2_FB12_Msk (0x1UL << CAN_F8R2_FB12_Pos)

#define	CAN_F8R2_FB12 CAN_F8R2_FB12_Msk

#define	CAN_F8R2_FB13_Pos (13U)

#define	CAN_F8R2_FB13_Msk (0x1UL << CAN_F8R2_FB13_Pos)

#define	CAN_F8R2_FB13 CAN_F8R2_FB13_Msk

#define	CAN_F8R2_FB14_Pos (14U)

#define	CAN_F8R2_FB14_Msk (0x1UL << CAN_F8R2_FB14_Pos)

#define	CAN_F8R2_FB14 CAN_F8R2_FB14_Msk

#define	CAN_F8R2_FB15_Pos (15U)

#define	CAN_F8R2_FB15_Msk (0x1UL << CAN_F8R2_FB15_Pos)

#define	CAN_F8R2_FB15 CAN_F8R2_FB15_Msk

#define	CAN_F8R2_FB16_Pos (16U)

#define	CAN_F8R2_FB16_Msk (0x1UL << CAN_F8R2_FB16_Pos)

#define	CAN_F8R2_FB16 CAN_F8R2_FB16_Msk

#define	CAN_F8R2_FB17_Pos (17U)

#define	CAN_F8R2_FB17_Msk (0x1UL << CAN_F8R2_FB17_Pos)

#define	CAN_F8R2_FB17 CAN_F8R2_FB17_Msk

#define	CAN_F8R2_FB18_Pos (18U)

#define	CAN_F8R2_FB18_Msk (0x1UL << CAN_F8R2_FB18_Pos)

#define	CAN_F8R2_FB18 CAN_F8R2_FB18_Msk

#define	CAN_F8R2_FB19_Pos (19U)

#define	CAN_F8R2_FB19_Msk (0x1UL << CAN_F8R2_FB19_Pos)

#define	CAN_F8R2_FB19 CAN_F8R2_FB19_Msk

#define	CAN_F8R2_FB20_Pos (20U)

#define	CAN_F8R2_FB20_Msk (0x1UL << CAN_F8R2_FB20_Pos)

#define	CAN_F8R2_FB20 CAN_F8R2_FB20_Msk

#define	CAN_F8R2_FB21_Pos (21U)

#define	CAN_F8R2_FB21_Msk (0x1UL << CAN_F8R2_FB21_Pos)

#define	CAN_F8R2_FB21 CAN_F8R2_FB21_Msk

#define	CAN_F8R2_FB22_Pos (22U)

#define	CAN_F8R2_FB22_Msk (0x1UL << CAN_F8R2_FB22_Pos)

#define	CAN_F8R2_FB22 CAN_F8R2_FB22_Msk

#define	CAN_F8R2_FB23_Pos (23U)

#define	CAN_F8R2_FB23_Msk (0x1UL << CAN_F8R2_FB23_Pos)

#define	CAN_F8R2_FB23 CAN_F8R2_FB23_Msk

#define	CAN_F8R2_FB24_Pos (24U)

#define	CAN_F8R2_FB24_Msk (0x1UL << CAN_F8R2_FB24_Pos)

#define	CAN_F8R2_FB24 CAN_F8R2_FB24_Msk

#define	CAN_F8R2_FB25_Pos (25U)

#define	CAN_F8R2_FB25_Msk (0x1UL << CAN_F8R2_FB25_Pos)

#define	CAN_F8R2_FB25 CAN_F8R2_FB25_Msk

#define	CAN_F8R2_FB26_Pos (26U)

#define	CAN_F8R2_FB26_Msk (0x1UL << CAN_F8R2_FB26_Pos)

#define	CAN_F8R2_FB26 CAN_F8R2_FB26_Msk

#define	CAN_F8R2_FB27_Pos (27U)

#define	CAN_F8R2_FB27_Msk (0x1UL << CAN_F8R2_FB27_Pos)

#define	CAN_F8R2_FB27 CAN_F8R2_FB27_Msk

#define	CAN_F8R2_FB28_Pos (28U)

#define	CAN_F8R2_FB28_Msk (0x1UL << CAN_F8R2_FB28_Pos)

#define	CAN_F8R2_FB28 CAN_F8R2_FB28_Msk

#define	CAN_F8R2_FB29_Pos (29U)

#define	CAN_F8R2_FB29_Msk (0x1UL << CAN_F8R2_FB29_Pos)

#define	CAN_F8R2_FB29 CAN_F8R2_FB29_Msk

#define	CAN_F8R2_FB30_Pos (30U)

#define	CAN_F8R2_FB30_Msk (0x1UL << CAN_F8R2_FB30_Pos)

#define	CAN_F8R2_FB30 CAN_F8R2_FB30_Msk

#define	CAN_F8R2_FB31_Pos (31U)

#define	CAN_F8R2_FB31_Msk (0x1UL << CAN_F8R2_FB31_Pos)

#define	CAN_F8R2_FB31 CAN_F8R2_FB31_Msk

#define	CAN_F9R2_FB0_Pos (0U)

#define	CAN_F9R2_FB0_Msk (0x1UL << CAN_F9R2_FB0_Pos)

#define	CAN_F9R2_FB0 CAN_F9R2_FB0_Msk

#define	CAN_F9R2_FB1_Pos (1U)

#define	CAN_F9R2_FB1_Msk (0x1UL << CAN_F9R2_FB1_Pos)

#define	CAN_F9R2_FB1 CAN_F9R2_FB1_Msk

#define	CAN_F9R2_FB2_Pos (2U)

#define	CAN_F9R2_FB2_Msk (0x1UL << CAN_F9R2_FB2_Pos)

#define	CAN_F9R2_FB2 CAN_F9R2_FB2_Msk

#define	CAN_F9R2_FB3_Pos (3U)

#define	CAN_F9R2_FB3_Msk (0x1UL << CAN_F9R2_FB3_Pos)

#define	CAN_F9R2_FB3 CAN_F9R2_FB3_Msk

#define	CAN_F9R2_FB4_Pos (4U)

#define	CAN_F9R2_FB4_Msk (0x1UL << CAN_F9R2_FB4_Pos)

#define	CAN_F9R2_FB4 CAN_F9R2_FB4_Msk

#define	CAN_F9R2_FB5_Pos (5U)

#define	CAN_F9R2_FB5_Msk (0x1UL << CAN_F9R2_FB5_Pos)

#define	CAN_F9R2_FB5 CAN_F9R2_FB5_Msk

#define	CAN_F9R2_FB6_Pos (6U)

#define	CAN_F9R2_FB6_Msk (0x1UL << CAN_F9R2_FB6_Pos)

#define	CAN_F9R2_FB6 CAN_F9R2_FB6_Msk

#define	CAN_F9R2_FB7_Pos (7U)

#define	CAN_F9R2_FB7_Msk (0x1UL << CAN_F9R2_FB7_Pos)

#define	CAN_F9R2_FB7 CAN_F9R2_FB7_Msk

#define	CAN_F9R2_FB8_Pos (8U)

#define	CAN_F9R2_FB8_Msk (0x1UL << CAN_F9R2_FB8_Pos)

#define	CAN_F9R2_FB8 CAN_F9R2_FB8_Msk

#define	CAN_F9R2_FB9_Pos (9U)

#define	CAN_F9R2_FB9_Msk (0x1UL << CAN_F9R2_FB9_Pos)

#define	CAN_F9R2_FB9 CAN_F9R2_FB9_Msk

#define	CAN_F9R2_FB10_Pos (10U)

#define	CAN_F9R2_FB10_Msk (0x1UL << CAN_F9R2_FB10_Pos)

#define	CAN_F9R2_FB10 CAN_F9R2_FB10_Msk

#define	CAN_F9R2_FB11_Pos (11U)

#define	CAN_F9R2_FB11_Msk (0x1UL << CAN_F9R2_FB11_Pos)

#define	CAN_F9R2_FB11 CAN_F9R2_FB11_Msk

#define	CAN_F9R2_FB12_Pos (12U)

#define	CAN_F9R2_FB12_Msk (0x1UL << CAN_F9R2_FB12_Pos)

#define	CAN_F9R2_FB12 CAN_F9R2_FB12_Msk

#define	CAN_F9R2_FB13_Pos (13U)

#define	CAN_F9R2_FB13_Msk (0x1UL << CAN_F9R2_FB13_Pos)

#define	CAN_F9R2_FB13 CAN_F9R2_FB13_Msk

#define	CAN_F9R2_FB14_Pos (14U)

#define	CAN_F9R2_FB14_Msk (0x1UL << CAN_F9R2_FB14_Pos)

#define	CAN_F9R2_FB14 CAN_F9R2_FB14_Msk

#define	CAN_F9R2_FB15_Pos (15U)

#define	CAN_F9R2_FB15_Msk (0x1UL << CAN_F9R2_FB15_Pos)

#define	CAN_F9R2_FB15 CAN_F9R2_FB15_Msk

#define	CAN_F9R2_FB16_Pos (16U)

#define	CAN_F9R2_FB16_Msk (0x1UL << CAN_F9R2_FB16_Pos)

#define	CAN_F9R2_FB16 CAN_F9R2_FB16_Msk

#define	CAN_F9R2_FB17_Pos (17U)

#define	CAN_F9R2_FB17_Msk (0x1UL << CAN_F9R2_FB17_Pos)

#define	CAN_F9R2_FB17 CAN_F9R2_FB17_Msk

#define	CAN_F9R2_FB18_Pos (18U)

#define	CAN_F9R2_FB18_Msk (0x1UL << CAN_F9R2_FB18_Pos)

#define	CAN_F9R2_FB18 CAN_F9R2_FB18_Msk

#define	CAN_F9R2_FB19_Pos (19U)

#define	CAN_F9R2_FB19_Msk (0x1UL << CAN_F9R2_FB19_Pos)

#define	CAN_F9R2_FB19 CAN_F9R2_FB19_Msk

#define	CAN_F9R2_FB20_Pos (20U)

#define	CAN_F9R2_FB20_Msk (0x1UL << CAN_F9R2_FB20_Pos)

#define	CAN_F9R2_FB20 CAN_F9R2_FB20_Msk

#define	CAN_F9R2_FB21_Pos (21U)

#define	CAN_F9R2_FB21_Msk (0x1UL << CAN_F9R2_FB21_Pos)

#define	CAN_F9R2_FB21 CAN_F9R2_FB21_Msk

#define	CAN_F9R2_FB22_Pos (22U)

#define	CAN_F9R2_FB22_Msk (0x1UL << CAN_F9R2_FB22_Pos)

#define	CAN_F9R2_FB22 CAN_F9R2_FB22_Msk

#define	CAN_F9R2_FB23_Pos (23U)

#define	CAN_F9R2_FB23_Msk (0x1UL << CAN_F9R2_FB23_Pos)

#define	CAN_F9R2_FB23 CAN_F9R2_FB23_Msk

#define	CAN_F9R2_FB24_Pos (24U)

#define	CAN_F9R2_FB24_Msk (0x1UL << CAN_F9R2_FB24_Pos)

#define	CAN_F9R2_FB24 CAN_F9R2_FB24_Msk

#define	CAN_F9R2_FB25_Pos (25U)

#define	CAN_F9R2_FB25_Msk (0x1UL << CAN_F9R2_FB25_Pos)

#define	CAN_F9R2_FB25 CAN_F9R2_FB25_Msk

#define	CAN_F9R2_FB26_Pos (26U)

#define	CAN_F9R2_FB26_Msk (0x1UL << CAN_F9R2_FB26_Pos)

#define	CAN_F9R2_FB26 CAN_F9R2_FB26_Msk

#define	CAN_F9R2_FB27_Pos (27U)

#define	CAN_F9R2_FB27_Msk (0x1UL << CAN_F9R2_FB27_Pos)

#define	CAN_F9R2_FB27 CAN_F9R2_FB27_Msk

#define	CAN_F9R2_FB28_Pos (28U)

#define	CAN_F9R2_FB28_Msk (0x1UL << CAN_F9R2_FB28_Pos)

#define	CAN_F9R2_FB28 CAN_F9R2_FB28_Msk

#define	CAN_F9R2_FB29_Pos (29U)

#define	CAN_F9R2_FB29_Msk (0x1UL << CAN_F9R2_FB29_Pos)

#define	CAN_F9R2_FB29 CAN_F9R2_FB29_Msk

#define	CAN_F9R2_FB30_Pos (30U)

#define	CAN_F9R2_FB30_Msk (0x1UL << CAN_F9R2_FB30_Pos)

#define	CAN_F9R2_FB30 CAN_F9R2_FB30_Msk

#define	CAN_F9R2_FB31_Pos (31U)

#define	CAN_F9R2_FB31_Msk (0x1UL << CAN_F9R2_FB31_Pos)

#define	CAN_F9R2_FB31 CAN_F9R2_FB31_Msk

#define	CAN_F10R2_FB0_Pos (0U)

#define	CAN_F10R2_FB0_Msk (0x1UL << CAN_F10R2_FB0_Pos)

#define	CAN_F10R2_FB0 CAN_F10R2_FB0_Msk

#define	CAN_F10R2_FB1_Pos (1U)

#define	CAN_F10R2_FB1_Msk (0x1UL << CAN_F10R2_FB1_Pos)

#define	CAN_F10R2_FB1 CAN_F10R2_FB1_Msk

#define	CAN_F10R2_FB2_Pos (2U)

#define	CAN_F10R2_FB2_Msk (0x1UL << CAN_F10R2_FB2_Pos)

#define	CAN_F10R2_FB2 CAN_F10R2_FB2_Msk

#define	CAN_F10R2_FB3_Pos (3U)

#define	CAN_F10R2_FB3_Msk (0x1UL << CAN_F10R2_FB3_Pos)

#define	CAN_F10R2_FB3 CAN_F10R2_FB3_Msk

#define	CAN_F10R2_FB4_Pos (4U)

#define	CAN_F10R2_FB4_Msk (0x1UL << CAN_F10R2_FB4_Pos)

#define	CAN_F10R2_FB4 CAN_F10R2_FB4_Msk

#define	CAN_F10R2_FB5_Pos (5U)

#define	CAN_F10R2_FB5_Msk (0x1UL << CAN_F10R2_FB5_Pos)

#define	CAN_F10R2_FB5 CAN_F10R2_FB5_Msk

#define	CAN_F10R2_FB6_Pos (6U)

#define	CAN_F10R2_FB6_Msk (0x1UL << CAN_F10R2_FB6_Pos)

#define	CAN_F10R2_FB6 CAN_F10R2_FB6_Msk

#define	CAN_F10R2_FB7_Pos (7U)

#define	CAN_F10R2_FB7_Msk (0x1UL << CAN_F10R2_FB7_Pos)

#define	CAN_F10R2_FB7 CAN_F10R2_FB7_Msk

#define	CAN_F10R2_FB8_Pos (8U)

#define	CAN_F10R2_FB8_Msk (0x1UL << CAN_F10R2_FB8_Pos)

#define	CAN_F10R2_FB8 CAN_F10R2_FB8_Msk

#define	CAN_F10R2_FB9_Pos (9U)

#define	CAN_F10R2_FB9_Msk (0x1UL << CAN_F10R2_FB9_Pos)

#define	CAN_F10R2_FB9 CAN_F10R2_FB9_Msk

#define	CAN_F10R2_FB10_Pos (10U)

#define	CAN_F10R2_FB10_Msk (0x1UL << CAN_F10R2_FB10_Pos)

#define	CAN_F10R2_FB10 CAN_F10R2_FB10_Msk

#define	CAN_F10R2_FB11_Pos (11U)

#define	CAN_F10R2_FB11_Msk (0x1UL << CAN_F10R2_FB11_Pos)

#define	CAN_F10R2_FB11 CAN_F10R2_FB11_Msk

#define	CAN_F10R2_FB12_Pos (12U)

#define	CAN_F10R2_FB12_Msk (0x1UL << CAN_F10R2_FB12_Pos)

#define	CAN_F10R2_FB12 CAN_F10R2_FB12_Msk

#define	CAN_F10R2_FB13_Pos (13U)

#define	CAN_F10R2_FB13_Msk (0x1UL << CAN_F10R2_FB13_Pos)

#define	CAN_F10R2_FB13 CAN_F10R2_FB13_Msk

#define	CAN_F10R2_FB14_Pos (14U)

#define	CAN_F10R2_FB14_Msk (0x1UL << CAN_F10R2_FB14_Pos)

#define	CAN_F10R2_FB14 CAN_F10R2_FB14_Msk

#define	CAN_F10R2_FB15_Pos (15U)

#define	CAN_F10R2_FB15_Msk (0x1UL << CAN_F10R2_FB15_Pos)

#define	CAN_F10R2_FB15 CAN_F10R2_FB15_Msk

#define	CAN_F10R2_FB16_Pos (16U)

#define	CAN_F10R2_FB16_Msk (0x1UL << CAN_F10R2_FB16_Pos)

#define	CAN_F10R2_FB16 CAN_F10R2_FB16_Msk

#define	CAN_F10R2_FB17_Pos (17U)

#define	CAN_F10R2_FB17_Msk (0x1UL << CAN_F10R2_FB17_Pos)

#define	CAN_F10R2_FB17 CAN_F10R2_FB17_Msk

#define	CAN_F10R2_FB18_Pos (18U)

#define	CAN_F10R2_FB18_Msk (0x1UL << CAN_F10R2_FB18_Pos)

#define	CAN_F10R2_FB18 CAN_F10R2_FB18_Msk

#define	CAN_F10R2_FB19_Pos (19U)

#define	CAN_F10R2_FB19_Msk (0x1UL << CAN_F10R2_FB19_Pos)

#define	CAN_F10R2_FB19 CAN_F10R2_FB19_Msk

#define	CAN_F10R2_FB20_Pos (20U)

#define	CAN_F10R2_FB20_Msk (0x1UL << CAN_F10R2_FB20_Pos)

#define	CAN_F10R2_FB20 CAN_F10R2_FB20_Msk

#define	CAN_F10R2_FB21_Pos (21U)

#define	CAN_F10R2_FB21_Msk (0x1UL << CAN_F10R2_FB21_Pos)

#define	CAN_F10R2_FB21 CAN_F10R2_FB21_Msk

#define	CAN_F10R2_FB22_Pos (22U)

#define	CAN_F10R2_FB22_Msk (0x1UL << CAN_F10R2_FB22_Pos)

#define	CAN_F10R2_FB22 CAN_F10R2_FB22_Msk

#define	CAN_F10R2_FB23_Pos (23U)

#define	CAN_F10R2_FB23_Msk (0x1UL << CAN_F10R2_FB23_Pos)

#define	CAN_F10R2_FB23 CAN_F10R2_FB23_Msk

#define	CAN_F10R2_FB24_Pos (24U)

#define	CAN_F10R2_FB24_Msk (0x1UL << CAN_F10R2_FB24_Pos)

#define	CAN_F10R2_FB24 CAN_F10R2_FB24_Msk

#define	CAN_F10R2_FB25_Pos (25U)

#define	CAN_F10R2_FB25_Msk (0x1UL << CAN_F10R2_FB25_Pos)

#define	CAN_F10R2_FB25 CAN_F10R2_FB25_Msk

#define	CAN_F10R2_FB26_Pos (26U)

#define	CAN_F10R2_FB26_Msk (0x1UL << CAN_F10R2_FB26_Pos)

#define	CAN_F10R2_FB26 CAN_F10R2_FB26_Msk

#define	CAN_F10R2_FB27_Pos (27U)

#define	CAN_F10R2_FB27_Msk (0x1UL << CAN_F10R2_FB27_Pos)

#define	CAN_F10R2_FB27 CAN_F10R2_FB27_Msk

#define	CAN_F10R2_FB28_Pos (28U)

#define	CAN_F10R2_FB28_Msk (0x1UL << CAN_F10R2_FB28_Pos)

#define	CAN_F10R2_FB28 CAN_F10R2_FB28_Msk

#define	CAN_F10R2_FB29_Pos (29U)

#define	CAN_F10R2_FB29_Msk (0x1UL << CAN_F10R2_FB29_Pos)

#define	CAN_F10R2_FB29 CAN_F10R2_FB29_Msk

#define	CAN_F10R2_FB30_Pos (30U)

#define	CAN_F10R2_FB30_Msk (0x1UL << CAN_F10R2_FB30_Pos)

#define	CAN_F10R2_FB30 CAN_F10R2_FB30_Msk

#define	CAN_F10R2_FB31_Pos (31U)

#define	CAN_F10R2_FB31_Msk (0x1UL << CAN_F10R2_FB31_Pos)

#define	CAN_F10R2_FB31 CAN_F10R2_FB31_Msk

#define	CAN_F11R2_FB0_Pos (0U)

#define	CAN_F11R2_FB0_Msk (0x1UL << CAN_F11R2_FB0_Pos)

#define	CAN_F11R2_FB0 CAN_F11R2_FB0_Msk

#define	CAN_F11R2_FB1_Pos (1U)

#define	CAN_F11R2_FB1_Msk (0x1UL << CAN_F11R2_FB1_Pos)

#define	CAN_F11R2_FB1 CAN_F11R2_FB1_Msk

#define	CAN_F11R2_FB2_Pos (2U)

#define	CAN_F11R2_FB2_Msk (0x1UL << CAN_F11R2_FB2_Pos)

#define	CAN_F11R2_FB2 CAN_F11R2_FB2_Msk

#define	CAN_F11R2_FB3_Pos (3U)

#define	CAN_F11R2_FB3_Msk (0x1UL << CAN_F11R2_FB3_Pos)

#define	CAN_F11R2_FB3 CAN_F11R2_FB3_Msk

#define	CAN_F11R2_FB4_Pos (4U)

#define	CAN_F11R2_FB4_Msk (0x1UL << CAN_F11R2_FB4_Pos)

#define	CAN_F11R2_FB4 CAN_F11R2_FB4_Msk

#define	CAN_F11R2_FB5_Pos (5U)

#define	CAN_F11R2_FB5_Msk (0x1UL << CAN_F11R2_FB5_Pos)

#define	CAN_F11R2_FB5 CAN_F11R2_FB5_Msk

#define	CAN_F11R2_FB6_Pos (6U)

#define	CAN_F11R2_FB6_Msk (0x1UL << CAN_F11R2_FB6_Pos)

#define	CAN_F11R2_FB6 CAN_F11R2_FB6_Msk

#define	CAN_F11R2_FB7_Pos (7U)

#define	CAN_F11R2_FB7_Msk (0x1UL << CAN_F11R2_FB7_Pos)

#define	CAN_F11R2_FB7 CAN_F11R2_FB7_Msk

#define	CAN_F11R2_FB8_Pos (8U)

#define	CAN_F11R2_FB8_Msk (0x1UL << CAN_F11R2_FB8_Pos)

#define	CAN_F11R2_FB8 CAN_F11R2_FB8_Msk

#define	CAN_F11R2_FB9_Pos (9U)

#define	CAN_F11R2_FB9_Msk (0x1UL << CAN_F11R2_FB9_Pos)

#define	CAN_F11R2_FB9 CAN_F11R2_FB9_Msk

#define	CAN_F11R2_FB10_Pos (10U)

#define	CAN_F11R2_FB10_Msk (0x1UL << CAN_F11R2_FB10_Pos)

#define	CAN_F11R2_FB10 CAN_F11R2_FB10_Msk

#define	CAN_F11R2_FB11_Pos (11U)

#define	CAN_F11R2_FB11_Msk (0x1UL << CAN_F11R2_FB11_Pos)

#define	CAN_F11R2_FB11 CAN_F11R2_FB11_Msk

#define	CAN_F11R2_FB12_Pos (12U)

#define	CAN_F11R2_FB12_Msk (0x1UL << CAN_F11R2_FB12_Pos)

#define	CAN_F11R2_FB12 CAN_F11R2_FB12_Msk

#define	CAN_F11R2_FB13_Pos (13U)

#define	CAN_F11R2_FB13_Msk (0x1UL << CAN_F11R2_FB13_Pos)

#define	CAN_F11R2_FB13 CAN_F11R2_FB13_Msk

#define	CAN_F11R2_FB14_Pos (14U)

#define	CAN_F11R2_FB14_Msk (0x1UL << CAN_F11R2_FB14_Pos)

#define	CAN_F11R2_FB14 CAN_F11R2_FB14_Msk

#define	CAN_F11R2_FB15_Pos (15U)

#define	CAN_F11R2_FB15_Msk (0x1UL << CAN_F11R2_FB15_Pos)

#define	CAN_F11R2_FB15 CAN_F11R2_FB15_Msk

#define	CAN_F11R2_FB16_Pos (16U)

#define	CAN_F11R2_FB16_Msk (0x1UL << CAN_F11R2_FB16_Pos)

#define	CAN_F11R2_FB16 CAN_F11R2_FB16_Msk

#define	CAN_F11R2_FB17_Pos (17U)

#define	CAN_F11R2_FB17_Msk (0x1UL << CAN_F11R2_FB17_Pos)

#define	CAN_F11R2_FB17 CAN_F11R2_FB17_Msk

#define	CAN_F11R2_FB18_Pos (18U)

#define	CAN_F11R2_FB18_Msk (0x1UL << CAN_F11R2_FB18_Pos)

#define	CAN_F11R2_FB18 CAN_F11R2_FB18_Msk

#define	CAN_F11R2_FB19_Pos (19U)

#define	CAN_F11R2_FB19_Msk (0x1UL << CAN_F11R2_FB19_Pos)

#define	CAN_F11R2_FB19 CAN_F11R2_FB19_Msk

#define	CAN_F11R2_FB20_Pos (20U)

#define	CAN_F11R2_FB20_Msk (0x1UL << CAN_F11R2_FB20_Pos)

#define	CAN_F11R2_FB20 CAN_F11R2_FB20_Msk

#define	CAN_F11R2_FB21_Pos (21U)

#define	CAN_F11R2_FB21_Msk (0x1UL << CAN_F11R2_FB21_Pos)

#define	CAN_F11R2_FB21 CAN_F11R2_FB21_Msk

#define	CAN_F11R2_FB22_Pos (22U)

#define	CAN_F11R2_FB22_Msk (0x1UL << CAN_F11R2_FB22_Pos)

#define	CAN_F11R2_FB22 CAN_F11R2_FB22_Msk

#define	CAN_F11R2_FB23_Pos (23U)

#define	CAN_F11R2_FB23_Msk (0x1UL << CAN_F11R2_FB23_Pos)

#define	CAN_F11R2_FB23 CAN_F11R2_FB23_Msk

#define	CAN_F11R2_FB24_Pos (24U)

#define	CAN_F11R2_FB24_Msk (0x1UL << CAN_F11R2_FB24_Pos)

#define	CAN_F11R2_FB24 CAN_F11R2_FB24_Msk

#define	CAN_F11R2_FB25_Pos (25U)

#define	CAN_F11R2_FB25_Msk (0x1UL << CAN_F11R2_FB25_Pos)

#define	CAN_F11R2_FB25 CAN_F11R2_FB25_Msk

#define	CAN_F11R2_FB26_Pos (26U)

#define	CAN_F11R2_FB26_Msk (0x1UL << CAN_F11R2_FB26_Pos)

#define	CAN_F11R2_FB26 CAN_F11R2_FB26_Msk

#define	CAN_F11R2_FB27_Pos (27U)

#define	CAN_F11R2_FB27_Msk (0x1UL << CAN_F11R2_FB27_Pos)

#define	CAN_F11R2_FB27 CAN_F11R2_FB27_Msk

#define	CAN_F11R2_FB28_Pos (28U)

#define	CAN_F11R2_FB28_Msk (0x1UL << CAN_F11R2_FB28_Pos)

#define	CAN_F11R2_FB28 CAN_F11R2_FB28_Msk

#define	CAN_F11R2_FB29_Pos (29U)

#define	CAN_F11R2_FB29_Msk (0x1UL << CAN_F11R2_FB29_Pos)

#define	CAN_F11R2_FB29 CAN_F11R2_FB29_Msk

#define	CAN_F11R2_FB30_Pos (30U)

#define	CAN_F11R2_FB30_Msk (0x1UL << CAN_F11R2_FB30_Pos)

#define	CAN_F11R2_FB30 CAN_F11R2_FB30_Msk

#define	CAN_F11R2_FB31_Pos (31U)

#define	CAN_F11R2_FB31_Msk (0x1UL << CAN_F11R2_FB31_Pos)

#define	CAN_F11R2_FB31 CAN_F11R2_FB31_Msk

#define	CAN_F12R2_FB0_Pos (0U)

#define	CAN_F12R2_FB0_Msk (0x1UL << CAN_F12R2_FB0_Pos)

#define	CAN_F12R2_FB0 CAN_F12R2_FB0_Msk

#define	CAN_F12R2_FB1_Pos (1U)

#define	CAN_F12R2_FB1_Msk (0x1UL << CAN_F12R2_FB1_Pos)

#define	CAN_F12R2_FB1 CAN_F12R2_FB1_Msk

#define	CAN_F12R2_FB2_Pos (2U)

#define	CAN_F12R2_FB2_Msk (0x1UL << CAN_F12R2_FB2_Pos)

#define	CAN_F12R2_FB2 CAN_F12R2_FB2_Msk

#define	CAN_F12R2_FB3_Pos (3U)

#define	CAN_F12R2_FB3_Msk (0x1UL << CAN_F12R2_FB3_Pos)

#define	CAN_F12R2_FB3 CAN_F12R2_FB3_Msk

#define	CAN_F12R2_FB4_Pos (4U)

#define	CAN_F12R2_FB4_Msk (0x1UL << CAN_F12R2_FB4_Pos)

#define	CAN_F12R2_FB4 CAN_F12R2_FB4_Msk

#define	CAN_F12R2_FB5_Pos (5U)

#define	CAN_F12R2_FB5_Msk (0x1UL << CAN_F12R2_FB5_Pos)

#define	CAN_F12R2_FB5 CAN_F12R2_FB5_Msk

#define	CAN_F12R2_FB6_Pos (6U)

#define	CAN_F12R2_FB6_Msk (0x1UL << CAN_F12R2_FB6_Pos)

#define	CAN_F12R2_FB6 CAN_F12R2_FB6_Msk

#define	CAN_F12R2_FB7_Pos (7U)

#define	CAN_F12R2_FB7_Msk (0x1UL << CAN_F12R2_FB7_Pos)

#define	CAN_F12R2_FB7 CAN_F12R2_FB7_Msk

#define	CAN_F12R2_FB8_Pos (8U)

#define	CAN_F12R2_FB8_Msk (0x1UL << CAN_F12R2_FB8_Pos)

#define	CAN_F12R2_FB8 CAN_F12R2_FB8_Msk

#define	CAN_F12R2_FB9_Pos (9U)

#define	CAN_F12R2_FB9_Msk (0x1UL << CAN_F12R2_FB9_Pos)

#define	CAN_F12R2_FB9 CAN_F12R2_FB9_Msk

#define	CAN_F12R2_FB10_Pos (10U)

#define	CAN_F12R2_FB10_Msk (0x1UL << CAN_F12R2_FB10_Pos)

#define	CAN_F12R2_FB10 CAN_F12R2_FB10_Msk

#define	CAN_F12R2_FB11_Pos (11U)

#define	CAN_F12R2_FB11_Msk (0x1UL << CAN_F12R2_FB11_Pos)

#define	CAN_F12R2_FB11 CAN_F12R2_FB11_Msk

#define	CAN_F12R2_FB12_Pos (12U)

#define	CAN_F12R2_FB12_Msk (0x1UL << CAN_F12R2_FB12_Pos)

#define	CAN_F12R2_FB12 CAN_F12R2_FB12_Msk

#define	CAN_F12R2_FB13_Pos (13U)

#define	CAN_F12R2_FB13_Msk (0x1UL << CAN_F12R2_FB13_Pos)

#define	CAN_F12R2_FB13 CAN_F12R2_FB13_Msk

#define	CAN_F12R2_FB14_Pos (14U)

#define	CAN_F12R2_FB14_Msk (0x1UL << CAN_F12R2_FB14_Pos)

#define	CAN_F12R2_FB14 CAN_F12R2_FB14_Msk

#define	CAN_F12R2_FB15_Pos (15U)

#define	CAN_F12R2_FB15_Msk (0x1UL << CAN_F12R2_FB15_Pos)

#define	CAN_F12R2_FB15 CAN_F12R2_FB15_Msk

#define	CAN_F12R2_FB16_Pos (16U)

#define	CAN_F12R2_FB16_Msk (0x1UL << CAN_F12R2_FB16_Pos)

#define	CAN_F12R2_FB16 CAN_F12R2_FB16_Msk

#define	CAN_F12R2_FB17_Pos (17U)

#define	CAN_F12R2_FB17_Msk (0x1UL << CAN_F12R2_FB17_Pos)

#define	CAN_F12R2_FB17 CAN_F12R2_FB17_Msk

#define	CAN_F12R2_FB18_Pos (18U)

#define	CAN_F12R2_FB18_Msk (0x1UL << CAN_F12R2_FB18_Pos)

#define	CAN_F12R2_FB18 CAN_F12R2_FB18_Msk

#define	CAN_F12R2_FB19_Pos (19U)

#define	CAN_F12R2_FB19_Msk (0x1UL << CAN_F12R2_FB19_Pos)

#define	CAN_F12R2_FB19 CAN_F12R2_FB19_Msk

#define	CAN_F12R2_FB20_Pos (20U)

#define	CAN_F12R2_FB20_Msk (0x1UL << CAN_F12R2_FB20_Pos)

#define	CAN_F12R2_FB20 CAN_F12R2_FB20_Msk

#define	CAN_F12R2_FB21_Pos (21U)

#define	CAN_F12R2_FB21_Msk (0x1UL << CAN_F12R2_FB21_Pos)

#define	CAN_F12R2_FB21 CAN_F12R2_FB21_Msk

#define	CAN_F12R2_FB22_Pos (22U)

#define	CAN_F12R2_FB22_Msk (0x1UL << CAN_F12R2_FB22_Pos)

#define	CAN_F12R2_FB22 CAN_F12R2_FB22_Msk

#define	CAN_F12R2_FB23_Pos (23U)

#define	CAN_F12R2_FB23_Msk (0x1UL << CAN_F12R2_FB23_Pos)

#define	CAN_F12R2_FB23 CAN_F12R2_FB23_Msk

#define	CAN_F12R2_FB24_Pos (24U)

#define	CAN_F12R2_FB24_Msk (0x1UL << CAN_F12R2_FB24_Pos)

#define	CAN_F12R2_FB24 CAN_F12R2_FB24_Msk

#define	CAN_F12R2_FB25_Pos (25U)

#define	CAN_F12R2_FB25_Msk (0x1UL << CAN_F12R2_FB25_Pos)

#define	CAN_F12R2_FB25 CAN_F12R2_FB25_Msk

#define	CAN_F12R2_FB26_Pos (26U)

#define	CAN_F12R2_FB26_Msk (0x1UL << CAN_F12R2_FB26_Pos)

#define	CAN_F12R2_FB26 CAN_F12R2_FB26_Msk

#define	CAN_F12R2_FB27_Pos (27U)

#define	CAN_F12R2_FB27_Msk (0x1UL << CAN_F12R2_FB27_Pos)

#define	CAN_F12R2_FB27 CAN_F12R2_FB27_Msk

#define	CAN_F12R2_FB28_Pos (28U)

#define	CAN_F12R2_FB28_Msk (0x1UL << CAN_F12R2_FB28_Pos)

#define	CAN_F12R2_FB28 CAN_F12R2_FB28_Msk

#define	CAN_F12R2_FB29_Pos (29U)

#define	CAN_F12R2_FB29_Msk (0x1UL << CAN_F12R2_FB29_Pos)

#define	CAN_F12R2_FB29 CAN_F12R2_FB29_Msk

#define	CAN_F12R2_FB30_Pos (30U)

#define	CAN_F12R2_FB30_Msk (0x1UL << CAN_F12R2_FB30_Pos)

#define	CAN_F12R2_FB30 CAN_F12R2_FB30_Msk

#define	CAN_F12R2_FB31_Pos (31U)

#define	CAN_F12R2_FB31_Msk (0x1UL << CAN_F12R2_FB31_Pos)

#define	CAN_F12R2_FB31 CAN_F12R2_FB31_Msk

#define	CAN_F13R2_FB0_Pos (0U)

#define	CAN_F13R2_FB0_Msk (0x1UL << CAN_F13R2_FB0_Pos)

#define	CAN_F13R2_FB0 CAN_F13R2_FB0_Msk

#define	CAN_F13R2_FB1_Pos (1U)

#define	CAN_F13R2_FB1_Msk (0x1UL << CAN_F13R2_FB1_Pos)

#define	CAN_F13R2_FB1 CAN_F13R2_FB1_Msk

#define	CAN_F13R2_FB2_Pos (2U)

#define	CAN_F13R2_FB2_Msk (0x1UL << CAN_F13R2_FB2_Pos)

#define	CAN_F13R2_FB2 CAN_F13R2_FB2_Msk

#define	CAN_F13R2_FB3_Pos (3U)

#define	CAN_F13R2_FB3_Msk (0x1UL << CAN_F13R2_FB3_Pos)

#define	CAN_F13R2_FB3 CAN_F13R2_FB3_Msk

#define	CAN_F13R2_FB4_Pos (4U)

#define	CAN_F13R2_FB4_Msk (0x1UL << CAN_F13R2_FB4_Pos)

#define	CAN_F13R2_FB4 CAN_F13R2_FB4_Msk

#define	CAN_F13R2_FB5_Pos (5U)

#define	CAN_F13R2_FB5_Msk (0x1UL << CAN_F13R2_FB5_Pos)

#define	CAN_F13R2_FB5 CAN_F13R2_FB5_Msk

#define	CAN_F13R2_FB6_Pos (6U)

#define	CAN_F13R2_FB6_Msk (0x1UL << CAN_F13R2_FB6_Pos)

#define	CAN_F13R2_FB6 CAN_F13R2_FB6_Msk

#define	CAN_F13R2_FB7_Pos (7U)

#define	CAN_F13R2_FB7_Msk (0x1UL << CAN_F13R2_FB7_Pos)

#define	CAN_F13R2_FB7 CAN_F13R2_FB7_Msk

#define	CAN_F13R2_FB8_Pos (8U)

#define	CAN_F13R2_FB8_Msk (0x1UL << CAN_F13R2_FB8_Pos)

#define	CAN_F13R2_FB8 CAN_F13R2_FB8_Msk

#define	CAN_F13R2_FB9_Pos (9U)

#define	CAN_F13R2_FB9_Msk (0x1UL << CAN_F13R2_FB9_Pos)

#define	CAN_F13R2_FB9 CAN_F13R2_FB9_Msk

#define	CAN_F13R2_FB10_Pos (10U)

#define	CAN_F13R2_FB10_Msk (0x1UL << CAN_F13R2_FB10_Pos)

#define	CAN_F13R2_FB10 CAN_F13R2_FB10_Msk

#define	CAN_F13R2_FB11_Pos (11U)

#define	CAN_F13R2_FB11_Msk (0x1UL << CAN_F13R2_FB11_Pos)

#define	CAN_F13R2_FB11 CAN_F13R2_FB11_Msk

#define	CAN_F13R2_FB12_Pos (12U)

#define	CAN_F13R2_FB12_Msk (0x1UL << CAN_F13R2_FB12_Pos)

#define	CAN_F13R2_FB12 CAN_F13R2_FB12_Msk

#define	CAN_F13R2_FB13_Pos (13U)

#define	CAN_F13R2_FB13_Msk (0x1UL << CAN_F13R2_FB13_Pos)

#define	CAN_F13R2_FB13 CAN_F13R2_FB13_Msk

#define	CAN_F13R2_FB14_Pos (14U)

#define	CAN_F13R2_FB14_Msk (0x1UL << CAN_F13R2_FB14_Pos)

#define	CAN_F13R2_FB14 CAN_F13R2_FB14_Msk

#define	CAN_F13R2_FB15_Pos (15U)

#define	CAN_F13R2_FB15_Msk (0x1UL << CAN_F13R2_FB15_Pos)

#define	CAN_F13R2_FB15 CAN_F13R2_FB15_Msk

#define	CAN_F13R2_FB16_Pos (16U)

#define	CAN_F13R2_FB16_Msk (0x1UL << CAN_F13R2_FB16_Pos)

#define	CAN_F13R2_FB16 CAN_F13R2_FB16_Msk

#define	CAN_F13R2_FB17_Pos (17U)

#define	CAN_F13R2_FB17_Msk (0x1UL << CAN_F13R2_FB17_Pos)

#define	CAN_F13R2_FB17 CAN_F13R2_FB17_Msk

#define	CAN_F13R2_FB18_Pos (18U)

#define	CAN_F13R2_FB18_Msk (0x1UL << CAN_F13R2_FB18_Pos)

#define	CAN_F13R2_FB18 CAN_F13R2_FB18_Msk

#define	CAN_F13R2_FB19_Pos (19U)

#define	CAN_F13R2_FB19_Msk (0x1UL << CAN_F13R2_FB19_Pos)

#define	CAN_F13R2_FB19 CAN_F13R2_FB19_Msk

#define	CAN_F13R2_FB20_Pos (20U)

#define	CAN_F13R2_FB20_Msk (0x1UL << CAN_F13R2_FB20_Pos)

#define	CAN_F13R2_FB20 CAN_F13R2_FB20_Msk

#define	CAN_F13R2_FB21_Pos (21U)

#define	CAN_F13R2_FB21_Msk (0x1UL << CAN_F13R2_FB21_Pos)

#define	CAN_F13R2_FB21 CAN_F13R2_FB21_Msk

#define	CAN_F13R2_FB22_Pos (22U)

#define	CAN_F13R2_FB22_Msk (0x1UL << CAN_F13R2_FB22_Pos)

#define	CAN_F13R2_FB22 CAN_F13R2_FB22_Msk

#define	CAN_F13R2_FB23_Pos (23U)

#define	CAN_F13R2_FB23_Msk (0x1UL << CAN_F13R2_FB23_Pos)

#define	CAN_F13R2_FB23 CAN_F13R2_FB23_Msk

#define	CAN_F13R2_FB24_Pos (24U)

#define	CAN_F13R2_FB24_Msk (0x1UL << CAN_F13R2_FB24_Pos)

#define	CAN_F13R2_FB24 CAN_F13R2_FB24_Msk

#define	CAN_F13R2_FB25_Pos (25U)

#define	CAN_F13R2_FB25_Msk (0x1UL << CAN_F13R2_FB25_Pos)

#define	CAN_F13R2_FB25 CAN_F13R2_FB25_Msk

#define	CAN_F13R2_FB26_Pos (26U)

#define	CAN_F13R2_FB26_Msk (0x1UL << CAN_F13R2_FB26_Pos)

#define	CAN_F13R2_FB26 CAN_F13R2_FB26_Msk

#define	CAN_F13R2_FB27_Pos (27U)

#define	CAN_F13R2_FB27_Msk (0x1UL << CAN_F13R2_FB27_Pos)

#define	CAN_F13R2_FB27 CAN_F13R2_FB27_Msk

#define	CAN_F13R2_FB28_Pos (28U)

#define	CAN_F13R2_FB28_Msk (0x1UL << CAN_F13R2_FB28_Pos)

#define	CAN_F13R2_FB28 CAN_F13R2_FB28_Msk

#define	CAN_F13R2_FB29_Pos (29U)

#define	CAN_F13R2_FB29_Msk (0x1UL << CAN_F13R2_FB29_Pos)

#define	CAN_F13R2_FB29 CAN_F13R2_FB29_Msk

#define	CAN_F13R2_FB30_Pos (30U)

#define	CAN_F13R2_FB30_Msk (0x1UL << CAN_F13R2_FB30_Pos)

#define	CAN_F13R2_FB30 CAN_F13R2_FB30_Msk

#define	CAN_F13R2_FB31_Pos (31U)

#define	CAN_F13R2_FB31_Msk (0x1UL << CAN_F13R2_FB31_Pos)

#define	CAN_F13R2_FB31 CAN_F13R2_FB31_Msk

#define	CAN_F14R2_FB0_Pos (0U)

#define	CAN_F14R2_FB0_Msk (0x1UL << CAN_F14R2_FB0_Pos)

#define	CAN_F14R2_FB0 CAN_F14R2_FB0_Msk

#define	CAN_F14R2_FB1_Pos (1U)

#define	CAN_F14R2_FB1_Msk (0x1UL << CAN_F14R2_FB1_Pos)

#define	CAN_F14R2_FB1 CAN_F14R2_FB1_Msk

#define	CAN_F14R2_FB2_Pos (2U)

#define	CAN_F14R2_FB2_Msk (0x1UL << CAN_F14R2_FB2_Pos)

#define	CAN_F14R2_FB2 CAN_F14R2_FB2_Msk

#define	CAN_F14R2_FB3_Pos (3U)

#define	CAN_F14R2_FB3_Msk (0x1UL << CAN_F14R2_FB3_Pos)

#define	CAN_F14R2_FB3 CAN_F14R2_FB3_Msk

#define	CAN_F14R2_FB4_Pos (4U)

#define	CAN_F14R2_FB4_Msk (0x1UL << CAN_F14R2_FB4_Pos)

#define	CAN_F14R2_FB4 CAN_F14R2_FB4_Msk

#define	CAN_F14R2_FB5_Pos (5U)

#define	CAN_F14R2_FB5_Msk (0x1UL << CAN_F14R2_FB5_Pos)

#define	CAN_F14R2_FB5 CAN_F14R2_FB5_Msk

#define	CAN_F14R2_FB6_Pos (6U)

#define	CAN_F14R2_FB6_Msk (0x1UL << CAN_F14R2_FB6_Pos)

#define	CAN_F14R2_FB6 CAN_F14R2_FB6_Msk

#define	CAN_F14R2_FB7_Pos (7U)

#define	CAN_F14R2_FB7_Msk (0x1UL << CAN_F14R2_FB7_Pos)

#define	CAN_F14R2_FB7 CAN_F14R2_FB7_Msk

#define	CAN_F14R2_FB8_Pos (8U)

#define	CAN_F14R2_FB8_Msk (0x1UL << CAN_F14R2_FB8_Pos)

#define	CAN_F14R2_FB8 CAN_F14R2_FB8_Msk

#define	CAN_F14R2_FB9_Pos (9U)

#define	CAN_F14R2_FB9_Msk (0x1UL << CAN_F14R2_FB9_Pos)

#define	CAN_F14R2_FB9 CAN_F14R2_FB9_Msk

#define	CAN_F14R2_FB10_Pos (10U)

#define	CAN_F14R2_FB10_Msk (0x1UL << CAN_F14R2_FB10_Pos)

#define	CAN_F14R2_FB10 CAN_F14R2_FB10_Msk

#define	CAN_F14R2_FB11_Pos (11U)

#define	CAN_F14R2_FB11_Msk (0x1UL << CAN_F14R2_FB11_Pos)

#define	CAN_F14R2_FB11 CAN_F14R2_FB11_Msk

#define	CAN_F14R2_FB12_Pos (12U)

#define	CAN_F14R2_FB12_Msk (0x1UL << CAN_F14R2_FB12_Pos)

#define	CAN_F14R2_FB12 CAN_F14R2_FB12_Msk

#define	CAN_F14R2_FB13_Pos (13U)

#define	CAN_F14R2_FB13_Msk (0x1UL << CAN_F14R2_FB13_Pos)

#define	CAN_F14R2_FB13 CAN_F14R2_FB13_Msk

#define	CAN_F14R2_FB14_Pos (14U)

#define	CAN_F14R2_FB14_Msk (0x1UL << CAN_F14R2_FB14_Pos)

#define	CAN_F14R2_FB14 CAN_F14R2_FB14_Msk

#define	CAN_F14R2_FB15_Pos (15U)

#define	CAN_F14R2_FB15_Msk (0x1UL << CAN_F14R2_FB15_Pos)

#define	CAN_F14R2_FB15 CAN_F14R2_FB15_Msk

#define	CAN_F14R2_FB16_Pos (16U)

#define	CAN_F14R2_FB16_Msk (0x1UL << CAN_F14R2_FB16_Pos)

#define	CAN_F14R2_FB16 CAN_F14R2_FB16_Msk

#define	CAN_F14R2_FB17_Pos (17U)

#define	CAN_F14R2_FB17_Msk (0x1UL << CAN_F14R2_FB17_Pos)

#define	CAN_F14R2_FB17 CAN_F14R2_FB17_Msk

#define	CAN_F14R2_FB18_Pos (18U)

#define	CAN_F14R2_FB18_Msk (0x1UL << CAN_F14R2_FB18_Pos)

#define	CAN_F14R2_FB18 CAN_F14R2_FB18_Msk

#define	CAN_F14R2_FB19_Pos (19U)

#define	CAN_F14R2_FB19_Msk (0x1UL << CAN_F14R2_FB19_Pos)

#define	CAN_F14R2_FB19 CAN_F14R2_FB19_Msk

#define	CAN_F14R2_FB20_Pos (20U)

#define	CAN_F14R2_FB20_Msk (0x1UL << CAN_F14R2_FB20_Pos)

#define	CAN_F14R2_FB20 CAN_F14R2_FB20_Msk

#define	CAN_F14R2_FB21_Pos (21U)

#define	CAN_F14R2_FB21_Msk (0x1UL << CAN_F14R2_FB21_Pos)

#define	CAN_F14R2_FB21 CAN_F14R2_FB21_Msk

#define	CAN_F14R2_FB22_Pos (22U)

#define	CAN_F14R2_FB22_Msk (0x1UL << CAN_F14R2_FB22_Pos)

#define	CAN_F14R2_FB22 CAN_F14R2_FB22_Msk

#define	CAN_F14R2_FB23_Pos (23U)

#define	CAN_F14R2_FB23_Msk (0x1UL << CAN_F14R2_FB23_Pos)

#define	CAN_F14R2_FB23 CAN_F14R2_FB23_Msk

#define	CAN_F14R2_FB24_Pos (24U)

#define	CAN_F14R2_FB24_Msk (0x1UL << CAN_F14R2_FB24_Pos)

#define	CAN_F14R2_FB24 CAN_F14R2_FB24_Msk

#define	CAN_F14R2_FB25_Pos (25U)

#define	CAN_F14R2_FB25_Msk (0x1UL << CAN_F14R2_FB25_Pos)

#define	CAN_F14R2_FB25 CAN_F14R2_FB25_Msk

#define	CAN_F14R2_FB26_Pos (26U)

#define	CAN_F14R2_FB26_Msk (0x1UL << CAN_F14R2_FB26_Pos)

#define	CAN_F14R2_FB26 CAN_F14R2_FB26_Msk

#define	CAN_F14R2_FB27_Pos (27U)

#define	CAN_F14R2_FB27_Msk (0x1UL << CAN_F14R2_FB27_Pos)

#define	CAN_F14R2_FB27 CAN_F14R2_FB27_Msk

#define	CAN_F14R2_FB28_Pos (28U)

#define	CAN_F14R2_FB28_Msk (0x1UL << CAN_F14R2_FB28_Pos)

#define	CAN_F14R2_FB28 CAN_F14R2_FB28_Msk

#define	CAN_F14R2_FB29_Pos (29U)

#define	CAN_F14R2_FB29_Msk (0x1UL << CAN_F14R2_FB29_Pos)

#define	CAN_F14R2_FB29 CAN_F14R2_FB29_Msk

#define	CAN_F14R2_FB30_Pos (30U)

#define	CAN_F14R2_FB30_Msk (0x1UL << CAN_F14R2_FB30_Pos)

#define	CAN_F14R2_FB30 CAN_F14R2_FB30_Msk

#define	CAN_F14R2_FB31_Pos (31U)

#define	CAN_F14R2_FB31_Msk (0x1UL << CAN_F14R2_FB31_Pos)

#define	CAN_F14R2_FB31 CAN_F14R2_FB31_Msk

#define	CAN_F15R2_FB0_Pos (0U)

#define	CAN_F15R2_FB0_Msk (0x1UL << CAN_F15R2_FB0_Pos)

#define	CAN_F15R2_FB0 CAN_F15R2_FB0_Msk

#define	CAN_F15R2_FB1_Pos (1U)

#define	CAN_F15R2_FB1_Msk (0x1UL << CAN_F15R2_FB1_Pos)

#define	CAN_F15R2_FB1 CAN_F15R2_FB1_Msk

#define	CAN_F15R2_FB2_Pos (2U)

#define	CAN_F15R2_FB2_Msk (0x1UL << CAN_F15R2_FB2_Pos)

#define	CAN_F15R2_FB2 CAN_F15R2_FB2_Msk

#define	CAN_F15R2_FB3_Pos (3U)

#define	CAN_F15R2_FB3_Msk (0x1UL << CAN_F15R2_FB3_Pos)

#define	CAN_F15R2_FB3 CAN_F15R2_FB3_Msk

#define	CAN_F15R2_FB4_Pos (4U)

#define	CAN_F15R2_FB4_Msk (0x1UL << CAN_F15R2_FB4_Pos)

#define	CAN_F15R2_FB4 CAN_F15R2_FB4_Msk

#define	CAN_F15R2_FB5_Pos (5U)

#define	CAN_F15R2_FB5_Msk (0x1UL << CAN_F15R2_FB5_Pos)

#define	CAN_F15R2_FB5 CAN_F15R2_FB5_Msk

#define	CAN_F15R2_FB6_Pos (6U)

#define	CAN_F15R2_FB6_Msk (0x1UL << CAN_F15R2_FB6_Pos)

#define	CAN_F15R2_FB6 CAN_F15R2_FB6_Msk

#define	CAN_F15R2_FB7_Pos (7U)

#define	CAN_F15R2_FB7_Msk (0x1UL << CAN_F15R2_FB7_Pos)

#define	CAN_F15R2_FB7 CAN_F15R2_FB7_Msk

#define	CAN_F15R2_FB8_Pos (8U)

#define	CAN_F15R2_FB8_Msk (0x1UL << CAN_F15R2_FB8_Pos)

#define	CAN_F15R2_FB8 CAN_F15R2_FB8_Msk

#define	CAN_F15R2_FB9_Pos (9U)

#define	CAN_F15R2_FB9_Msk (0x1UL << CAN_F15R2_FB9_Pos)

#define	CAN_F15R2_FB9 CAN_F15R2_FB9_Msk

#define	CAN_F15R2_FB10_Pos (10U)

#define	CAN_F15R2_FB10_Msk (0x1UL << CAN_F15R2_FB10_Pos)

#define	CAN_F15R2_FB10 CAN_F15R2_FB10_Msk

#define	CAN_F15R2_FB11_Pos (11U)

#define	CAN_F15R2_FB11_Msk (0x1UL << CAN_F15R2_FB11_Pos)

#define	CAN_F15R2_FB11 CAN_F15R2_FB11_Msk

#define	CAN_F15R2_FB12_Pos (12U)

#define	CAN_F15R2_FB12_Msk (0x1UL << CAN_F15R2_FB12_Pos)

#define	CAN_F15R2_FB12 CAN_F15R2_FB12_Msk

#define	CAN_F15R2_FB13_Pos (13U)

#define	CAN_F15R2_FB13_Msk (0x1UL << CAN_F15R2_FB13_Pos)

#define	CAN_F15R2_FB13 CAN_F15R2_FB13_Msk

#define	CAN_F15R2_FB14_Pos (14U)

#define	CAN_F15R2_FB14_Msk (0x1UL << CAN_F15R2_FB14_Pos)

#define	CAN_F15R2_FB14 CAN_F15R2_FB14_Msk

#define	CAN_F15R2_FB15_Pos (15U)

#define	CAN_F15R2_FB15_Msk (0x1UL << CAN_F15R2_FB15_Pos)

#define	CAN_F15R2_FB15 CAN_F15R2_FB15_Msk

#define	CAN_F15R2_FB16_Pos (16U)

#define	CAN_F15R2_FB16_Msk (0x1UL << CAN_F15R2_FB16_Pos)

#define	CAN_F15R2_FB16 CAN_F15R2_FB16_Msk

#define	CAN_F15R2_FB17_Pos (17U)

#define	CAN_F15R2_FB17_Msk (0x1UL << CAN_F15R2_FB17_Pos)

#define	CAN_F15R2_FB17 CAN_F15R2_FB17_Msk

#define	CAN_F15R2_FB18_Pos (18U)

#define	CAN_F15R2_FB18_Msk (0x1UL << CAN_F15R2_FB18_Pos)

#define	CAN_F15R2_FB18 CAN_F15R2_FB18_Msk

#define	CAN_F15R2_FB19_Pos (19U)

#define	CAN_F15R2_FB19_Msk (0x1UL << CAN_F15R2_FB19_Pos)

#define	CAN_F15R2_FB19 CAN_F15R2_FB19_Msk

#define	CAN_F15R2_FB20_Pos (20U)

#define	CAN_F15R2_FB20_Msk (0x1UL << CAN_F15R2_FB20_Pos)

#define	CAN_F15R2_FB20 CAN_F15R2_FB20_Msk

#define	CAN_F15R2_FB21_Pos (21U)

#define	CAN_F15R2_FB21_Msk (0x1UL << CAN_F15R2_FB21_Pos)

#define	CAN_F15R2_FB21 CAN_F15R2_FB21_Msk

#define	CAN_F15R2_FB22_Pos (22U)

#define	CAN_F15R2_FB22_Msk (0x1UL << CAN_F15R2_FB22_Pos)

#define	CAN_F15R2_FB22 CAN_F15R2_FB22_Msk

#define	CAN_F15R2_FB23_Pos (23U)

#define	CAN_F15R2_FB23_Msk (0x1UL << CAN_F15R2_FB23_Pos)

#define	CAN_F15R2_FB23 CAN_F15R2_FB23_Msk

#define	CAN_F15R2_FB24_Pos (24U)

#define	CAN_F15R2_FB24_Msk (0x1UL << CAN_F15R2_FB24_Pos)

#define	CAN_F15R2_FB24 CAN_F15R2_FB24_Msk

#define	CAN_F15R2_FB25_Pos (25U)

#define	CAN_F15R2_FB25_Msk (0x1UL << CAN_F15R2_FB25_Pos)

#define	CAN_F15R2_FB25 CAN_F15R2_FB25_Msk

#define	CAN_F15R2_FB26_Pos (26U)

#define	CAN_F15R2_FB26_Msk (0x1UL << CAN_F15R2_FB26_Pos)

#define	CAN_F15R2_FB26 CAN_F15R2_FB26_Msk

#define	CAN_F15R2_FB27_Pos (27U)

#define	CAN_F15R2_FB27_Msk (0x1UL << CAN_F15R2_FB27_Pos)

#define	CAN_F15R2_FB27 CAN_F15R2_FB27_Msk

#define	CAN_F15R2_FB28_Pos (28U)

#define	CAN_F15R2_FB28_Msk (0x1UL << CAN_F15R2_FB28_Pos)

#define	CAN_F15R2_FB28 CAN_F15R2_FB28_Msk

#define	CAN_F15R2_FB29_Pos (29U)

#define	CAN_F15R2_FB29_Msk (0x1UL << CAN_F15R2_FB29_Pos)

#define	CAN_F15R2_FB29 CAN_F15R2_FB29_Msk

#define	CAN_F15R2_FB30_Pos (30U)

#define	CAN_F15R2_FB30_Msk (0x1UL << CAN_F15R2_FB30_Pos)

#define	CAN_F15R2_FB30 CAN_F15R2_FB30_Msk

#define	CAN_F15R2_FB31_Pos (31U)

#define	CAN_F15R2_FB31_Msk (0x1UL << CAN_F15R2_FB31_Pos)

#define	CAN_F15R2_FB31 CAN_F15R2_FB31_Msk

#define	CAN_F16R2_FB0_Pos (0U)

#define	CAN_F16R2_FB0_Msk (0x1UL << CAN_F16R2_FB0_Pos)

#define	CAN_F16R2_FB0 CAN_F16R2_FB0_Msk

#define	CAN_F16R2_FB1_Pos (1U)

#define	CAN_F16R2_FB1_Msk (0x1UL << CAN_F16R2_FB1_Pos)

#define	CAN_F16R2_FB1 CAN_F16R2_FB1_Msk

#define	CAN_F16R2_FB2_Pos (2U)

#define	CAN_F16R2_FB2_Msk (0x1UL << CAN_F16R2_FB2_Pos)

#define	CAN_F16R2_FB2 CAN_F16R2_FB2_Msk

#define	CAN_F16R2_FB3_Pos (3U)

#define	CAN_F16R2_FB3_Msk (0x1UL << CAN_F16R2_FB3_Pos)

#define	CAN_F16R2_FB3 CAN_F16R2_FB3_Msk

#define	CAN_F16R2_FB4_Pos (4U)

#define	CAN_F16R2_FB4_Msk (0x1UL << CAN_F16R2_FB4_Pos)

#define	CAN_F16R2_FB4 CAN_F16R2_FB4_Msk

#define	CAN_F16R2_FB5_Pos (5U)

#define	CAN_F16R2_FB5_Msk (0x1UL << CAN_F16R2_FB5_Pos)

#define	CAN_F16R2_FB5 CAN_F16R2_FB5_Msk

#define	CAN_F16R2_FB6_Pos (6U)

#define	CAN_F16R2_FB6_Msk (0x1UL << CAN_F16R2_FB6_Pos)

#define	CAN_F16R2_FB6 CAN_F16R2_FB6_Msk

#define	CAN_F16R2_FB7_Pos (7U)

#define	CAN_F16R2_FB7_Msk (0x1UL << CAN_F16R2_FB7_Pos)

#define	CAN_F16R2_FB7 CAN_F16R2_FB7_Msk

#define	CAN_F16R2_FB8_Pos (8U)

#define	CAN_F16R2_FB8_Msk (0x1UL << CAN_F16R2_FB8_Pos)

#define	CAN_F16R2_FB8 CAN_F16R2_FB8_Msk

#define	CAN_F16R2_FB9_Pos (9U)

#define	CAN_F16R2_FB9_Msk (0x1UL << CAN_F16R2_FB9_Pos)

#define	CAN_F16R2_FB9 CAN_F16R2_FB9_Msk

#define	CAN_F16R2_FB10_Pos (10U)

#define	CAN_F16R2_FB10_Msk (0x1UL << CAN_F16R2_FB10_Pos)

#define	CAN_F16R2_FB10 CAN_F16R2_FB10_Msk

#define	CAN_F16R2_FB11_Pos (11U)

#define	CAN_F16R2_FB11_Msk (0x1UL << CAN_F16R2_FB11_Pos)

#define	CAN_F16R2_FB11 CAN_F16R2_FB11_Msk

#define	CAN_F16R2_FB12_Pos (12U)

#define	CAN_F16R2_FB12_Msk (0x1UL << CAN_F16R2_FB12_Pos)

#define	CAN_F16R2_FB12 CAN_F16R2_FB12_Msk

#define	CAN_F16R2_FB13_Pos (13U)

#define	CAN_F16R2_FB13_Msk (0x1UL << CAN_F16R2_FB13_Pos)

#define	CAN_F16R2_FB13 CAN_F16R2_FB13_Msk

#define	CAN_F16R2_FB14_Pos (14U)

#define	CAN_F16R2_FB14_Msk (0x1UL << CAN_F16R2_FB14_Pos)

#define	CAN_F16R2_FB14 CAN_F16R2_FB14_Msk

#define	CAN_F16R2_FB15_Pos (15U)

#define	CAN_F16R2_FB15_Msk (0x1UL << CAN_F16R2_FB15_Pos)

#define	CAN_F16R2_FB15 CAN_F16R2_FB15_Msk

#define	CAN_F16R2_FB16_Pos (16U)

#define	CAN_F16R2_FB16_Msk (0x1UL << CAN_F16R2_FB16_Pos)

#define	CAN_F16R2_FB16 CAN_F16R2_FB16_Msk

#define	CAN_F16R2_FB17_Pos (17U)

#define	CAN_F16R2_FB17_Msk (0x1UL << CAN_F16R2_FB17_Pos)

#define	CAN_F16R2_FB17 CAN_F16R2_FB17_Msk

#define	CAN_F16R2_FB18_Pos (18U)

#define	CAN_F16R2_FB18_Msk (0x1UL << CAN_F16R2_FB18_Pos)

#define	CAN_F16R2_FB18 CAN_F16R2_FB18_Msk

#define	CAN_F16R2_FB19_Pos (19U)

#define	CAN_F16R2_FB19_Msk (0x1UL << CAN_F16R2_FB19_Pos)

#define	CAN_F16R2_FB19 CAN_F16R2_FB19_Msk

#define	CAN_F16R2_FB20_Pos (20U)

#define	CAN_F16R2_FB20_Msk (0x1UL << CAN_F16R2_FB20_Pos)

#define	CAN_F16R2_FB20 CAN_F16R2_FB20_Msk

#define	CAN_F16R2_FB21_Pos (21U)

#define	CAN_F16R2_FB21_Msk (0x1UL << CAN_F16R2_FB21_Pos)

#define	CAN_F16R2_FB21 CAN_F16R2_FB21_Msk

#define	CAN_F16R2_FB22_Pos (22U)

#define	CAN_F16R2_FB22_Msk (0x1UL << CAN_F16R2_FB22_Pos)

#define	CAN_F16R2_FB22 CAN_F16R2_FB22_Msk

#define	CAN_F16R2_FB23_Pos (23U)

#define	CAN_F16R2_FB23_Msk (0x1UL << CAN_F16R2_FB23_Pos)

#define	CAN_F16R2_FB23 CAN_F16R2_FB23_Msk

#define	CAN_F16R2_FB24_Pos (24U)

#define	CAN_F16R2_FB24_Msk (0x1UL << CAN_F16R2_FB24_Pos)

#define	CAN_F16R2_FB24 CAN_F16R2_FB24_Msk

#define	CAN_F16R2_FB25_Pos (25U)

#define	CAN_F16R2_FB25_Msk (0x1UL << CAN_F16R2_FB25_Pos)

#define	CAN_F16R2_FB25 CAN_F16R2_FB25_Msk

#define	CAN_F16R2_FB26_Pos (26U)

#define	CAN_F16R2_FB26_Msk (0x1UL << CAN_F16R2_FB26_Pos)

#define	CAN_F16R2_FB26 CAN_F16R2_FB26_Msk

#define	CAN_F16R2_FB27_Pos (27U)

#define	CAN_F16R2_FB27_Msk (0x1UL << CAN_F16R2_FB27_Pos)

#define	CAN_F16R2_FB27 CAN_F16R2_FB27_Msk

#define	CAN_F16R2_FB28_Pos (28U)

#define	CAN_F16R2_FB28_Msk (0x1UL << CAN_F16R2_FB28_Pos)

#define	CAN_F16R2_FB28 CAN_F16R2_FB28_Msk

#define	CAN_F16R2_FB29_Pos (29U)

#define	CAN_F16R2_FB29_Msk (0x1UL << CAN_F16R2_FB29_Pos)

#define	CAN_F16R2_FB29 CAN_F16R2_FB29_Msk

#define	CAN_F16R2_FB30_Pos (30U)

#define	CAN_F16R2_FB30_Msk (0x1UL << CAN_F16R2_FB30_Pos)

#define	CAN_F16R2_FB30 CAN_F16R2_FB30_Msk

#define	CAN_F16R2_FB31_Pos (31U)

#define	CAN_F16R2_FB31_Msk (0x1UL << CAN_F16R2_FB31_Pos)

#define	CAN_F16R2_FB31 CAN_F16R2_FB31_Msk

#define	CAN_F17R2_FB0_Pos (0U)

#define	CAN_F17R2_FB0_Msk (0x1UL << CAN_F17R2_FB0_Pos)

#define	CAN_F17R2_FB0 CAN_F17R2_FB0_Msk

#define	CAN_F17R2_FB1_Pos (1U)

#define	CAN_F17R2_FB1_Msk (0x1UL << CAN_F17R2_FB1_Pos)

#define	CAN_F17R2_FB1 CAN_F17R2_FB1_Msk

#define	CAN_F17R2_FB2_Pos (2U)

#define	CAN_F17R2_FB2_Msk (0x1UL << CAN_F17R2_FB2_Pos)

#define	CAN_F17R2_FB2 CAN_F17R2_FB2_Msk

#define	CAN_F17R2_FB3_Pos (3U)

#define	CAN_F17R2_FB3_Msk (0x1UL << CAN_F17R2_FB3_Pos)

#define	CAN_F17R2_FB3 CAN_F17R2_FB3_Msk

#define	CAN_F17R2_FB4_Pos (4U)

#define	CAN_F17R2_FB4_Msk (0x1UL << CAN_F17R2_FB4_Pos)

#define	CAN_F17R2_FB4 CAN_F17R2_FB4_Msk

#define	CAN_F17R2_FB5_Pos (5U)

#define	CAN_F17R2_FB5_Msk (0x1UL << CAN_F17R2_FB5_Pos)

#define	CAN_F17R2_FB5 CAN_F17R2_FB5_Msk

#define	CAN_F17R2_FB6_Pos (6U)

#define	CAN_F17R2_FB6_Msk (0x1UL << CAN_F17R2_FB6_Pos)

#define	CAN_F17R2_FB6 CAN_F17R2_FB6_Msk

#define	CAN_F17R2_FB7_Pos (7U)

#define	CAN_F17R2_FB7_Msk (0x1UL << CAN_F17R2_FB7_Pos)

#define	CAN_F17R2_FB7 CAN_F17R2_FB7_Msk

#define	CAN_F17R2_FB8_Pos (8U)

#define	CAN_F17R2_FB8_Msk (0x1UL << CAN_F17R2_FB8_Pos)

#define	CAN_F17R2_FB8 CAN_F17R2_FB8_Msk

#define	CAN_F17R2_FB9_Pos (9U)

#define	CAN_F17R2_FB9_Msk (0x1UL << CAN_F17R2_FB9_Pos)

#define	CAN_F17R2_FB9 CAN_F17R2_FB9_Msk

#define	CAN_F17R2_FB10_Pos (10U)

#define	CAN_F17R2_FB10_Msk (0x1UL << CAN_F17R2_FB10_Pos)

#define	CAN_F17R2_FB10 CAN_F17R2_FB10_Msk

#define	CAN_F17R2_FB11_Pos (11U)

#define	CAN_F17R2_FB11_Msk (0x1UL << CAN_F17R2_FB11_Pos)

#define	CAN_F17R2_FB11 CAN_F17R2_FB11_Msk

#define	CAN_F17R2_FB12_Pos (12U)

#define	CAN_F17R2_FB12_Msk (0x1UL << CAN_F17R2_FB12_Pos)

#define	CAN_F17R2_FB12 CAN_F17R2_FB12_Msk

#define	CAN_F17R2_FB13_Pos (13U)

#define	CAN_F17R2_FB13_Msk (0x1UL << CAN_F17R2_FB13_Pos)

#define	CAN_F17R2_FB13 CAN_F17R2_FB13_Msk

#define	CAN_F17R2_FB14_Pos (14U)

#define	CAN_F17R2_FB14_Msk (0x1UL << CAN_F17R2_FB14_Pos)

#define	CAN_F17R2_FB14 CAN_F17R2_FB14_Msk

#define	CAN_F17R2_FB15_Pos (15U)

#define	CAN_F17R2_FB15_Msk (0x1UL << CAN_F17R2_FB15_Pos)

#define	CAN_F17R2_FB15 CAN_F17R2_FB15_Msk

#define	CAN_F17R2_FB16_Pos (16U)

#define	CAN_F17R2_FB16_Msk (0x1UL << CAN_F17R2_FB16_Pos)

#define	CAN_F17R2_FB16 CAN_F17R2_FB16_Msk

#define	CAN_F17R2_FB17_Pos (17U)

#define	CAN_F17R2_FB17_Msk (0x1UL << CAN_F17R2_FB17_Pos)

#define	CAN_F17R2_FB17 CAN_F17R2_FB17_Msk

#define	CAN_F17R2_FB18_Pos (18U)

#define	CAN_F17R2_FB18_Msk (0x1UL << CAN_F17R2_FB18_Pos)

#define	CAN_F17R2_FB18 CAN_F17R2_FB18_Msk

#define	CAN_F17R2_FB19_Pos (19U)

#define	CAN_F17R2_FB19_Msk (0x1UL << CAN_F17R2_FB19_Pos)

#define	CAN_F17R2_FB19 CAN_F17R2_FB19_Msk

#define	CAN_F17R2_FB20_Pos (20U)

#define	CAN_F17R2_FB20_Msk (0x1UL << CAN_F17R2_FB20_Pos)

#define	CAN_F17R2_FB20 CAN_F17R2_FB20_Msk

#define	CAN_F17R2_FB21_Pos (21U)

#define	CAN_F17R2_FB21_Msk (0x1UL << CAN_F17R2_FB21_Pos)

#define	CAN_F17R2_FB21 CAN_F17R2_FB21_Msk

#define	CAN_F17R2_FB22_Pos (22U)

#define	CAN_F17R2_FB22_Msk (0x1UL << CAN_F17R2_FB22_Pos)

#define	CAN_F17R2_FB22 CAN_F17R2_FB22_Msk

#define	CAN_F17R2_FB23_Pos (23U)

#define	CAN_F17R2_FB23_Msk (0x1UL << CAN_F17R2_FB23_Pos)

#define	CAN_F17R2_FB23 CAN_F17R2_FB23_Msk

#define	CAN_F17R2_FB24_Pos (24U)

#define	CAN_F17R2_FB24_Msk (0x1UL << CAN_F17R2_FB24_Pos)

#define	CAN_F17R2_FB24 CAN_F17R2_FB24_Msk

#define	CAN_F17R2_FB25_Pos (25U)

#define	CAN_F17R2_FB25_Msk (0x1UL << CAN_F17R2_FB25_Pos)

#define	CAN_F17R2_FB25 CAN_F17R2_FB25_Msk

#define	CAN_F17R2_FB26_Pos (26U)

#define	CAN_F17R2_FB26_Msk (0x1UL << CAN_F17R2_FB26_Pos)

#define	CAN_F17R2_FB26 CAN_F17R2_FB26_Msk

#define	CAN_F17R2_FB27_Pos (27U)

#define	CAN_F17R2_FB27_Msk (0x1UL << CAN_F17R2_FB27_Pos)

#define	CAN_F17R2_FB27 CAN_F17R2_FB27_Msk

#define	CAN_F17R2_FB28_Pos (28U)

#define	CAN_F17R2_FB28_Msk (0x1UL << CAN_F17R2_FB28_Pos)

#define	CAN_F17R2_FB28 CAN_F17R2_FB28_Msk

#define	CAN_F17R2_FB29_Pos (29U)

#define	CAN_F17R2_FB29_Msk (0x1UL << CAN_F17R2_FB29_Pos)

#define	CAN_F17R2_FB29 CAN_F17R2_FB29_Msk

#define	CAN_F17R2_FB30_Pos (30U)

#define	CAN_F17R2_FB30_Msk (0x1UL << CAN_F17R2_FB30_Pos)

#define	CAN_F17R2_FB30 CAN_F17R2_FB30_Msk

#define	CAN_F17R2_FB31_Pos (31U)

#define	CAN_F17R2_FB31_Msk (0x1UL << CAN_F17R2_FB31_Pos)

#define	CAN_F17R2_FB31 CAN_F17R2_FB31_Msk

#define	CAN_F18R2_FB0_Pos (0U)

#define	CAN_F18R2_FB0_Msk (0x1UL << CAN_F18R2_FB0_Pos)

#define	CAN_F18R2_FB0 CAN_F18R2_FB0_Msk

#define	CAN_F18R2_FB1_Pos (1U)

#define	CAN_F18R2_FB1_Msk (0x1UL << CAN_F18R2_FB1_Pos)

#define	CAN_F18R2_FB1 CAN_F18R2_FB1_Msk

#define	CAN_F18R2_FB2_Pos (2U)

#define	CAN_F18R2_FB2_Msk (0x1UL << CAN_F18R2_FB2_Pos)

#define	CAN_F18R2_FB2 CAN_F18R2_FB2_Msk

#define	CAN_F18R2_FB3_Pos (3U)

#define	CAN_F18R2_FB3_Msk (0x1UL << CAN_F18R2_FB3_Pos)

#define	CAN_F18R2_FB3 CAN_F18R2_FB3_Msk

#define	CAN_F18R2_FB4_Pos (4U)

#define	CAN_F18R2_FB4_Msk (0x1UL << CAN_F18R2_FB4_Pos)

#define	CAN_F18R2_FB4 CAN_F18R2_FB4_Msk

#define	CAN_F18R2_FB5_Pos (5U)

#define	CAN_F18R2_FB5_Msk (0x1UL << CAN_F18R2_FB5_Pos)

#define	CAN_F18R2_FB5 CAN_F18R2_FB5_Msk

#define	CAN_F18R2_FB6_Pos (6U)

#define	CAN_F18R2_FB6_Msk (0x1UL << CAN_F18R2_FB6_Pos)

#define	CAN_F18R2_FB6 CAN_F18R2_FB6_Msk

#define	CAN_F18R2_FB7_Pos (7U)

#define	CAN_F18R2_FB7_Msk (0x1UL << CAN_F18R2_FB7_Pos)

#define	CAN_F18R2_FB7 CAN_F18R2_FB7_Msk

#define	CAN_F18R2_FB8_Pos (8U)

#define	CAN_F18R2_FB8_Msk (0x1UL << CAN_F18R2_FB8_Pos)

#define	CAN_F18R2_FB8 CAN_F18R2_FB8_Msk

#define	CAN_F18R2_FB9_Pos (9U)

#define	CAN_F18R2_FB9_Msk (0x1UL << CAN_F18R2_FB9_Pos)

#define	CAN_F18R2_FB9 CAN_F18R2_FB9_Msk

#define	CAN_F18R2_FB10_Pos (10U)

#define	CAN_F18R2_FB10_Msk (0x1UL << CAN_F18R2_FB10_Pos)

#define	CAN_F18R2_FB10 CAN_F18R2_FB10_Msk

#define	CAN_F18R2_FB11_Pos (11U)

#define	CAN_F18R2_FB11_Msk (0x1UL << CAN_F18R2_FB11_Pos)

#define	CAN_F18R2_FB11 CAN_F18R2_FB11_Msk

#define	CAN_F18R2_FB12_Pos (12U)

#define	CAN_F18R2_FB12_Msk (0x1UL << CAN_F18R2_FB12_Pos)

#define	CAN_F18R2_FB12 CAN_F18R2_FB12_Msk

#define	CAN_F18R2_FB13_Pos (13U)

#define	CAN_F18R2_FB13_Msk (0x1UL << CAN_F18R2_FB13_Pos)

#define	CAN_F18R2_FB13 CAN_F18R2_FB13_Msk

#define	CAN_F18R2_FB14_Pos (14U)

#define	CAN_F18R2_FB14_Msk (0x1UL << CAN_F18R2_FB14_Pos)

#define	CAN_F18R2_FB14 CAN_F18R2_FB14_Msk

#define	CAN_F18R2_FB15_Pos (15U)

#define	CAN_F18R2_FB15_Msk (0x1UL << CAN_F18R2_FB15_Pos)

#define	CAN_F18R2_FB15 CAN_F18R2_FB15_Msk

#define	CAN_F18R2_FB16_Pos (16U)

#define	CAN_F18R2_FB16_Msk (0x1UL << CAN_F18R2_FB16_Pos)

#define	CAN_F18R2_FB16 CAN_F18R2_FB16_Msk

#define	CAN_F18R2_FB17_Pos (17U)

#define	CAN_F18R2_FB17_Msk (0x1UL << CAN_F18R2_FB17_Pos)

#define	CAN_F18R2_FB17 CAN_F18R2_FB17_Msk

#define	CAN_F18R2_FB18_Pos (18U)

#define	CAN_F18R2_FB18_Msk (0x1UL << CAN_F18R2_FB18_Pos)

#define	CAN_F18R2_FB18 CAN_F18R2_FB18_Msk

#define	CAN_F18R2_FB19_Pos (19U)

#define	CAN_F18R2_FB19_Msk (0x1UL << CAN_F18R2_FB19_Pos)

#define	CAN_F18R2_FB19 CAN_F18R2_FB19_Msk

#define	CAN_F18R2_FB20_Pos (20U)

#define	CAN_F18R2_FB20_Msk (0x1UL << CAN_F18R2_FB20_Pos)

#define	CAN_F18R2_FB20 CAN_F18R2_FB20_Msk

#define	CAN_F18R2_FB21_Pos (21U)

#define	CAN_F18R2_FB21_Msk (0x1UL << CAN_F18R2_FB21_Pos)

#define	CAN_F18R2_FB21 CAN_F18R2_FB21_Msk

#define	CAN_F18R2_FB22_Pos (22U)

#define	CAN_F18R2_FB22_Msk (0x1UL << CAN_F18R2_FB22_Pos)

#define	CAN_F18R2_FB22 CAN_F18R2_FB22_Msk

#define	CAN_F18R2_FB23_Pos (23U)

#define	CAN_F18R2_FB23_Msk (0x1UL << CAN_F18R2_FB23_Pos)

#define	CAN_F18R2_FB23 CAN_F18R2_FB23_Msk

#define	CAN_F18R2_FB24_Pos (24U)

#define	CAN_F18R2_FB24_Msk (0x1UL << CAN_F18R2_FB24_Pos)

#define	CAN_F18R2_FB24 CAN_F18R2_FB24_Msk

#define	CAN_F18R2_FB25_Pos (25U)

#define	CAN_F18R2_FB25_Msk (0x1UL << CAN_F18R2_FB25_Pos)

#define	CAN_F18R2_FB25 CAN_F18R2_FB25_Msk

#define	CAN_F18R2_FB26_Pos (26U)

#define	CAN_F18R2_FB26_Msk (0x1UL << CAN_F18R2_FB26_Pos)

#define	CAN_F18R2_FB26 CAN_F18R2_FB26_Msk

#define	CAN_F18R2_FB27_Pos (27U)

#define	CAN_F18R2_FB27_Msk (0x1UL << CAN_F18R2_FB27_Pos)

#define	CAN_F18R2_FB27 CAN_F18R2_FB27_Msk

#define	CAN_F18R2_FB28_Pos (28U)

#define	CAN_F18R2_FB28_Msk (0x1UL << CAN_F18R2_FB28_Pos)

#define	CAN_F18R2_FB28 CAN_F18R2_FB28_Msk

#define	CAN_F18R2_FB29_Pos (29U)

#define	CAN_F18R2_FB29_Msk (0x1UL << CAN_F18R2_FB29_Pos)

#define	CAN_F18R2_FB29 CAN_F18R2_FB29_Msk

#define	CAN_F18R2_FB30_Pos (30U)

#define	CAN_F18R2_FB30_Msk (0x1UL << CAN_F18R2_FB30_Pos)

#define	CAN_F18R2_FB30 CAN_F18R2_FB30_Msk

#define	CAN_F18R2_FB31_Pos (31U)

#define	CAN_F18R2_FB31_Msk (0x1UL << CAN_F18R2_FB31_Pos)

#define	CAN_F18R2_FB31 CAN_F18R2_FB31_Msk

#define	CAN_F19R2_FB0_Pos (0U)

#define	CAN_F19R2_FB0_Msk (0x1UL << CAN_F19R2_FB0_Pos)

#define	CAN_F19R2_FB0 CAN_F19R2_FB0_Msk

#define	CAN_F19R2_FB1_Pos (1U)

#define	CAN_F19R2_FB1_Msk (0x1UL << CAN_F19R2_FB1_Pos)

#define	CAN_F19R2_FB1 CAN_F19R2_FB1_Msk

#define	CAN_F19R2_FB2_Pos (2U)

#define	CAN_F19R2_FB2_Msk (0x1UL << CAN_F19R2_FB2_Pos)

#define	CAN_F19R2_FB2 CAN_F19R2_FB2_Msk

#define	CAN_F19R2_FB3_Pos (3U)

#define	CAN_F19R2_FB3_Msk (0x1UL << CAN_F19R2_FB3_Pos)

#define	CAN_F19R2_FB3 CAN_F19R2_FB3_Msk

#define	CAN_F19R2_FB4_Pos (4U)

#define	CAN_F19R2_FB4_Msk (0x1UL << CAN_F19R2_FB4_Pos)

#define	CAN_F19R2_FB4 CAN_F19R2_FB4_Msk

#define	CAN_F19R2_FB5_Pos (5U)

#define	CAN_F19R2_FB5_Msk (0x1UL << CAN_F19R2_FB5_Pos)

#define	CAN_F19R2_FB5 CAN_F19R2_FB5_Msk

#define	CAN_F19R2_FB6_Pos (6U)

#define	CAN_F19R2_FB6_Msk (0x1UL << CAN_F19R2_FB6_Pos)

#define	CAN_F19R2_FB6 CAN_F19R2_FB6_Msk

#define	CAN_F19R2_FB7_Pos (7U)

#define	CAN_F19R2_FB7_Msk (0x1UL << CAN_F19R2_FB7_Pos)

#define	CAN_F19R2_FB7 CAN_F19R2_FB7_Msk

#define	CAN_F19R2_FB8_Pos (8U)

#define	CAN_F19R2_FB8_Msk (0x1UL << CAN_F19R2_FB8_Pos)

#define	CAN_F19R2_FB8 CAN_F19R2_FB8_Msk

#define	CAN_F19R2_FB9_Pos (9U)

#define	CAN_F19R2_FB9_Msk (0x1UL << CAN_F19R2_FB9_Pos)

#define	CAN_F19R2_FB9 CAN_F19R2_FB9_Msk

#define	CAN_F19R2_FB10_Pos (10U)

#define	CAN_F19R2_FB10_Msk (0x1UL << CAN_F19R2_FB10_Pos)

#define	CAN_F19R2_FB10 CAN_F19R2_FB10_Msk

#define	CAN_F19R2_FB11_Pos (11U)

#define	CAN_F19R2_FB11_Msk (0x1UL << CAN_F19R2_FB11_Pos)

#define	CAN_F19R2_FB11 CAN_F19R2_FB11_Msk

#define	CAN_F19R2_FB12_Pos (12U)

#define	CAN_F19R2_FB12_Msk (0x1UL << CAN_F19R2_FB12_Pos)

#define	CAN_F19R2_FB12 CAN_F19R2_FB12_Msk

#define	CAN_F19R2_FB13_Pos (13U)

#define	CAN_F19R2_FB13_Msk (0x1UL << CAN_F19R2_FB13_Pos)

#define	CAN_F19R2_FB13 CAN_F19R2_FB13_Msk

#define	CAN_F19R2_FB14_Pos (14U)

#define	CAN_F19R2_FB14_Msk (0x1UL << CAN_F19R2_FB14_Pos)

#define	CAN_F19R2_FB14 CAN_F19R2_FB14_Msk

#define	CAN_F19R2_FB15_Pos (15U)

#define	CAN_F19R2_FB15_Msk (0x1UL << CAN_F19R2_FB15_Pos)

#define	CAN_F19R2_FB15 CAN_F19R2_FB15_Msk

#define	CAN_F19R2_FB16_Pos (16U)

#define	CAN_F19R2_FB16_Msk (0x1UL << CAN_F19R2_FB16_Pos)

#define	CAN_F19R2_FB16 CAN_F19R2_FB16_Msk

#define	CAN_F19R2_FB17_Pos (17U)

#define	CAN_F19R2_FB17_Msk (0x1UL << CAN_F19R2_FB17_Pos)

#define	CAN_F19R2_FB17 CAN_F19R2_FB17_Msk

#define	CAN_F19R2_FB18_Pos (18U)

#define	CAN_F19R2_FB18_Msk (0x1UL << CAN_F19R2_FB18_Pos)

#define	CAN_F19R2_FB18 CAN_F19R2_FB18_Msk

#define	CAN_F19R2_FB19_Pos (19U)

#define	CAN_F19R2_FB19_Msk (0x1UL << CAN_F19R2_FB19_Pos)

#define	CAN_F19R2_FB19 CAN_F19R2_FB19_Msk

#define	CAN_F19R2_FB20_Pos (20U)

#define	CAN_F19R2_FB20_Msk (0x1UL << CAN_F19R2_FB20_Pos)

#define	CAN_F19R2_FB20 CAN_F19R2_FB20_Msk

#define	CAN_F19R2_FB21_Pos (21U)

#define	CAN_F19R2_FB21_Msk (0x1UL << CAN_F19R2_FB21_Pos)

#define	CAN_F19R2_FB21 CAN_F19R2_FB21_Msk

#define	CAN_F19R2_FB22_Pos (22U)

#define	CAN_F19R2_FB22_Msk (0x1UL << CAN_F19R2_FB22_Pos)

#define	CAN_F19R2_FB22 CAN_F19R2_FB22_Msk

#define	CAN_F19R2_FB23_Pos (23U)

#define	CAN_F19R2_FB23_Msk (0x1UL << CAN_F19R2_FB23_Pos)

#define	CAN_F19R2_FB23 CAN_F19R2_FB23_Msk

#define	CAN_F19R2_FB24_Pos (24U)

#define	CAN_F19R2_FB24_Msk (0x1UL << CAN_F19R2_FB24_Pos)

#define	CAN_F19R2_FB24 CAN_F19R2_FB24_Msk

#define	CAN_F19R2_FB25_Pos (25U)

#define	CAN_F19R2_FB25_Msk (0x1UL << CAN_F19R2_FB25_Pos)

#define	CAN_F19R2_FB25 CAN_F19R2_FB25_Msk

#define	CAN_F19R2_FB26_Pos (26U)

#define	CAN_F19R2_FB26_Msk (0x1UL << CAN_F19R2_FB26_Pos)

#define	CAN_F19R2_FB26 CAN_F19R2_FB26_Msk

#define	CAN_F19R2_FB27_Pos (27U)

#define	CAN_F19R2_FB27_Msk (0x1UL << CAN_F19R2_FB27_Pos)

#define	CAN_F19R2_FB27 CAN_F19R2_FB27_Msk

#define	CAN_F19R2_FB28_Pos (28U)

#define	CAN_F19R2_FB28_Msk (0x1UL << CAN_F19R2_FB28_Pos)

#define	CAN_F19R2_FB28 CAN_F19R2_FB28_Msk

#define	CAN_F19R2_FB29_Pos (29U)

#define	CAN_F19R2_FB29_Msk (0x1UL << CAN_F19R2_FB29_Pos)

#define	CAN_F19R2_FB29 CAN_F19R2_FB29_Msk

#define	CAN_F19R2_FB30_Pos (30U)

#define	CAN_F19R2_FB30_Msk (0x1UL << CAN_F19R2_FB30_Pos)

#define	CAN_F19R2_FB30 CAN_F19R2_FB30_Msk

#define	CAN_F19R2_FB31_Pos (31U)

#define	CAN_F19R2_FB31_Msk (0x1UL << CAN_F19R2_FB31_Pos)

#define	CAN_F19R2_FB31 CAN_F19R2_FB31_Msk

#define	CAN_F20R2_FB0_Pos (0U)

#define	CAN_F20R2_FB0_Msk (0x1UL << CAN_F20R2_FB0_Pos)

#define	CAN_F20R2_FB0 CAN_F20R2_FB0_Msk

#define	CAN_F20R2_FB1_Pos (1U)

#define	CAN_F20R2_FB1_Msk (0x1UL << CAN_F20R2_FB1_Pos)

#define	CAN_F20R2_FB1 CAN_F20R2_FB1_Msk

#define	CAN_F20R2_FB2_Pos (2U)

#define	CAN_F20R2_FB2_Msk (0x1UL << CAN_F20R2_FB2_Pos)

#define	CAN_F20R2_FB2 CAN_F20R2_FB2_Msk

#define	CAN_F20R2_FB3_Pos (3U)

#define	CAN_F20R2_FB3_Msk (0x1UL << CAN_F20R2_FB3_Pos)

#define	CAN_F20R2_FB3 CAN_F20R2_FB3_Msk

#define	CAN_F20R2_FB4_Pos (4U)

#define	CAN_F20R2_FB4_Msk (0x1UL << CAN_F20R2_FB4_Pos)

#define	CAN_F20R2_FB4 CAN_F20R2_FB4_Msk

#define	CAN_F20R2_FB5_Pos (5U)

#define	CAN_F20R2_FB5_Msk (0x1UL << CAN_F20R2_FB5_Pos)

#define	CAN_F20R2_FB5 CAN_F20R2_FB5_Msk

#define	CAN_F20R2_FB6_Pos (6U)

#define	CAN_F20R2_FB6_Msk (0x1UL << CAN_F20R2_FB6_Pos)

#define	CAN_F20R2_FB6 CAN_F20R2_FB6_Msk

#define	CAN_F20R2_FB7_Pos (7U)

#define	CAN_F20R2_FB7_Msk (0x1UL << CAN_F20R2_FB7_Pos)

#define	CAN_F20R2_FB7 CAN_F20R2_FB7_Msk

#define	CAN_F20R2_FB8_Pos (8U)

#define	CAN_F20R2_FB8_Msk (0x1UL << CAN_F20R2_FB8_Pos)

#define	CAN_F20R2_FB8 CAN_F20R2_FB8_Msk

#define	CAN_F20R2_FB9_Pos (9U)

#define	CAN_F20R2_FB9_Msk (0x1UL << CAN_F20R2_FB9_Pos)

#define	CAN_F20R2_FB9 CAN_F20R2_FB9_Msk

#define	CAN_F20R2_FB10_Pos (10U)

#define	CAN_F20R2_FB10_Msk (0x1UL << CAN_F20R2_FB10_Pos)

#define	CAN_F20R2_FB10 CAN_F20R2_FB10_Msk

#define	CAN_F20R2_FB11_Pos (11U)

#define	CAN_F20R2_FB11_Msk (0x1UL << CAN_F20R2_FB11_Pos)

#define	CAN_F20R2_FB11 CAN_F20R2_FB11_Msk

#define	CAN_F20R2_FB12_Pos (12U)

#define	CAN_F20R2_FB12_Msk (0x1UL << CAN_F20R2_FB12_Pos)

#define	CAN_F20R2_FB12 CAN_F20R2_FB12_Msk

#define	CAN_F20R2_FB13_Pos (13U)

#define	CAN_F20R2_FB13_Msk (0x1UL << CAN_F20R2_FB13_Pos)

#define	CAN_F20R2_FB13 CAN_F20R2_FB13_Msk

#define	CAN_F20R2_FB14_Pos (14U)

#define	CAN_F20R2_FB14_Msk (0x1UL << CAN_F20R2_FB14_Pos)

#define	CAN_F20R2_FB14 CAN_F20R2_FB14_Msk

#define	CAN_F20R2_FB15_Pos (15U)

#define	CAN_F20R2_FB15_Msk (0x1UL << CAN_F20R2_FB15_Pos)

#define	CAN_F20R2_FB15 CAN_F20R2_FB15_Msk

#define	CAN_F20R2_FB16_Pos (16U)

#define	CAN_F20R2_FB16_Msk (0x1UL << CAN_F20R2_FB16_Pos)

#define	CAN_F20R2_FB16 CAN_F20R2_FB16_Msk

#define	CAN_F20R2_FB17_Pos (17U)

#define	CAN_F20R2_FB17_Msk (0x1UL << CAN_F20R2_FB17_Pos)

#define	CAN_F20R2_FB17 CAN_F20R2_FB17_Msk

#define	CAN_F20R2_FB18_Pos (18U)

#define	CAN_F20R2_FB18_Msk (0x1UL << CAN_F20R2_FB18_Pos)

#define	CAN_F20R2_FB18 CAN_F20R2_FB18_Msk

#define	CAN_F20R2_FB19_Pos (19U)

#define	CAN_F20R2_FB19_Msk (0x1UL << CAN_F20R2_FB19_Pos)

#define	CAN_F20R2_FB19 CAN_F20R2_FB19_Msk

#define	CAN_F20R2_FB20_Pos (20U)

#define	CAN_F20R2_FB20_Msk (0x1UL << CAN_F20R2_FB20_Pos)

#define	CAN_F20R2_FB20 CAN_F20R2_FB20_Msk

#define	CAN_F20R2_FB21_Pos (21U)

#define	CAN_F20R2_FB21_Msk (0x1UL << CAN_F20R2_FB21_Pos)

#define	CAN_F20R2_FB21 CAN_F20R2_FB21_Msk

#define	CAN_F20R2_FB22_Pos (22U)

#define	CAN_F20R2_FB22_Msk (0x1UL << CAN_F20R2_FB22_Pos)

#define	CAN_F20R2_FB22 CAN_F20R2_FB22_Msk

#define	CAN_F20R2_FB23_Pos (23U)

#define	CAN_F20R2_FB23_Msk (0x1UL << CAN_F20R2_FB23_Pos)

#define	CAN_F20R2_FB23 CAN_F20R2_FB23_Msk

#define	CAN_F20R2_FB24_Pos (24U)

#define	CAN_F20R2_FB24_Msk (0x1UL << CAN_F20R2_FB24_Pos)

#define	CAN_F20R2_FB24 CAN_F20R2_FB24_Msk

#define	CAN_F20R2_FB25_Pos (25U)

#define	CAN_F20R2_FB25_Msk (0x1UL << CAN_F20R2_FB25_Pos)

#define	CAN_F20R2_FB25 CAN_F20R2_FB25_Msk

#define	CAN_F20R2_FB26_Pos (26U)

#define	CAN_F20R2_FB26_Msk (0x1UL << CAN_F20R2_FB26_Pos)

#define	CAN_F20R2_FB26 CAN_F20R2_FB26_Msk

#define	CAN_F20R2_FB27_Pos (27U)

#define	CAN_F20R2_FB27_Msk (0x1UL << CAN_F20R2_FB27_Pos)

#define	CAN_F20R2_FB27 CAN_F20R2_FB27_Msk

#define	CAN_F20R2_FB28_Pos (28U)

#define	CAN_F20R2_FB28_Msk (0x1UL << CAN_F20R2_FB28_Pos)

#define	CAN_F20R2_FB28 CAN_F20R2_FB28_Msk

#define	CAN_F20R2_FB29_Pos (29U)

#define	CAN_F20R2_FB29_Msk (0x1UL << CAN_F20R2_FB29_Pos)

#define	CAN_F20R2_FB29 CAN_F20R2_FB29_Msk

#define	CAN_F20R2_FB30_Pos (30U)

#define	CAN_F20R2_FB30_Msk (0x1UL << CAN_F20R2_FB30_Pos)

#define	CAN_F20R2_FB30 CAN_F20R2_FB30_Msk

#define	CAN_F20R2_FB31_Pos (31U)

#define	CAN_F20R2_FB31_Msk (0x1UL << CAN_F20R2_FB31_Pos)

#define	CAN_F20R2_FB31 CAN_F20R2_FB31_Msk

#define	CAN_F21R2_FB0_Pos (0U)

#define	CAN_F21R2_FB0_Msk (0x1UL << CAN_F21R2_FB0_Pos)

#define	CAN_F21R2_FB0 CAN_F21R2_FB0_Msk

#define	CAN_F21R2_FB1_Pos (1U)

#define	CAN_F21R2_FB1_Msk (0x1UL << CAN_F21R2_FB1_Pos)

#define	CAN_F21R2_FB1 CAN_F21R2_FB1_Msk

#define	CAN_F21R2_FB2_Pos (2U)

#define	CAN_F21R2_FB2_Msk (0x1UL << CAN_F21R2_FB2_Pos)

#define	CAN_F21R2_FB2 CAN_F21R2_FB2_Msk

#define	CAN_F21R2_FB3_Pos (3U)

#define	CAN_F21R2_FB3_Msk (0x1UL << CAN_F21R2_FB3_Pos)

#define	CAN_F21R2_FB3 CAN_F21R2_FB3_Msk

#define	CAN_F21R2_FB4_Pos (4U)

#define	CAN_F21R2_FB4_Msk (0x1UL << CAN_F21R2_FB4_Pos)

#define	CAN_F21R2_FB4 CAN_F21R2_FB4_Msk

#define	CAN_F21R2_FB5_Pos (5U)

#define	CAN_F21R2_FB5_Msk (0x1UL << CAN_F21R2_FB5_Pos)

#define	CAN_F21R2_FB5 CAN_F21R2_FB5_Msk

#define	CAN_F21R2_FB6_Pos (6U)

#define	CAN_F21R2_FB6_Msk (0x1UL << CAN_F21R2_FB6_Pos)

#define	CAN_F21R2_FB6 CAN_F21R2_FB6_Msk

#define	CAN_F21R2_FB7_Pos (7U)

#define	CAN_F21R2_FB7_Msk (0x1UL << CAN_F21R2_FB7_Pos)

#define	CAN_F21R2_FB7 CAN_F21R2_FB7_Msk

#define	CAN_F21R2_FB8_Pos (8U)

#define	CAN_F21R2_FB8_Msk (0x1UL << CAN_F21R2_FB8_Pos)

#define	CAN_F21R2_FB8 CAN_F21R2_FB8_Msk

#define	CAN_F21R2_FB9_Pos (9U)

#define	CAN_F21R2_FB9_Msk (0x1UL << CAN_F21R2_FB9_Pos)

#define	CAN_F21R2_FB9 CAN_F21R2_FB9_Msk

#define	CAN_F21R2_FB10_Pos (10U)

#define	CAN_F21R2_FB10_Msk (0x1UL << CAN_F21R2_FB10_Pos)

#define	CAN_F21R2_FB10 CAN_F21R2_FB10_Msk

#define	CAN_F21R2_FB11_Pos (11U)

#define	CAN_F21R2_FB11_Msk (0x1UL << CAN_F21R2_FB11_Pos)

#define	CAN_F21R2_FB11 CAN_F21R2_FB11_Msk

#define	CAN_F21R2_FB12_Pos (12U)

#define	CAN_F21R2_FB12_Msk (0x1UL << CAN_F21R2_FB12_Pos)

#define	CAN_F21R2_FB12 CAN_F21R2_FB12_Msk

#define	CAN_F21R2_FB13_Pos (13U)

#define	CAN_F21R2_FB13_Msk (0x1UL << CAN_F21R2_FB13_Pos)

#define	CAN_F21R2_FB13 CAN_F21R2_FB13_Msk

#define	CAN_F21R2_FB14_Pos (14U)

#define	CAN_F21R2_FB14_Msk (0x1UL << CAN_F21R2_FB14_Pos)

#define	CAN_F21R2_FB14 CAN_F21R2_FB14_Msk

#define	CAN_F21R2_FB15_Pos (15U)

#define	CAN_F21R2_FB15_Msk (0x1UL << CAN_F21R2_FB15_Pos)

#define	CAN_F21R2_FB15 CAN_F21R2_FB15_Msk

#define	CAN_F21R2_FB16_Pos (16U)

#define	CAN_F21R2_FB16_Msk (0x1UL << CAN_F21R2_FB16_Pos)

#define	CAN_F21R2_FB16 CAN_F21R2_FB16_Msk

#define	CAN_F21R2_FB17_Pos (17U)

#define	CAN_F21R2_FB17_Msk (0x1UL << CAN_F21R2_FB17_Pos)

#define	CAN_F21R2_FB17 CAN_F21R2_FB17_Msk

#define	CAN_F21R2_FB18_Pos (18U)

#define	CAN_F21R2_FB18_Msk (0x1UL << CAN_F21R2_FB18_Pos)

#define	CAN_F21R2_FB18 CAN_F21R2_FB18_Msk

#define	CAN_F21R2_FB19_Pos (19U)

#define	CAN_F21R2_FB19_Msk (0x1UL << CAN_F21R2_FB19_Pos)

#define	CAN_F21R2_FB19 CAN_F21R2_FB19_Msk

#define	CAN_F21R2_FB20_Pos (20U)

#define	CAN_F21R2_FB20_Msk (0x1UL << CAN_F21R2_FB20_Pos)

#define	CAN_F21R2_FB20 CAN_F21R2_FB20_Msk

#define	CAN_F21R2_FB21_Pos (21U)

#define	CAN_F21R2_FB21_Msk (0x1UL << CAN_F21R2_FB21_Pos)

#define	CAN_F21R2_FB21 CAN_F21R2_FB21_Msk

#define	CAN_F21R2_FB22_Pos (22U)

#define	CAN_F21R2_FB22_Msk (0x1UL << CAN_F21R2_FB22_Pos)

#define	CAN_F21R2_FB22 CAN_F21R2_FB22_Msk

#define	CAN_F21R2_FB23_Pos (23U)

#define	CAN_F21R2_FB23_Msk (0x1UL << CAN_F21R2_FB23_Pos)

#define	CAN_F21R2_FB23 CAN_F21R2_FB23_Msk

#define	CAN_F21R2_FB24_Pos (24U)

#define	CAN_F21R2_FB24_Msk (0x1UL << CAN_F21R2_FB24_Pos)

#define	CAN_F21R2_FB24 CAN_F21R2_FB24_Msk

#define	CAN_F21R2_FB25_Pos (25U)

#define	CAN_F21R2_FB25_Msk (0x1UL << CAN_F21R2_FB25_Pos)

#define	CAN_F21R2_FB25 CAN_F21R2_FB25_Msk

#define	CAN_F21R2_FB26_Pos (26U)

#define	CAN_F21R2_FB26_Msk (0x1UL << CAN_F21R2_FB26_Pos)

#define	CAN_F21R2_FB26 CAN_F21R2_FB26_Msk

#define	CAN_F21R2_FB27_Pos (27U)

#define	CAN_F21R2_FB27_Msk (0x1UL << CAN_F21R2_FB27_Pos)

#define	CAN_F21R2_FB27 CAN_F21R2_FB27_Msk

#define	CAN_F21R2_FB28_Pos (28U)

#define	CAN_F21R2_FB28_Msk (0x1UL << CAN_F21R2_FB28_Pos)

#define	CAN_F21R2_FB28 CAN_F21R2_FB28_Msk

#define	CAN_F21R2_FB29_Pos (29U)

#define	CAN_F21R2_FB29_Msk (0x1UL << CAN_F21R2_FB29_Pos)

#define	CAN_F21R2_FB29 CAN_F21R2_FB29_Msk

#define	CAN_F21R2_FB30_Pos (30U)

#define	CAN_F21R2_FB30_Msk (0x1UL << CAN_F21R2_FB30_Pos)

#define	CAN_F21R2_FB30 CAN_F21R2_FB30_Msk

#define	CAN_F21R2_FB31_Pos (31U)

#define	CAN_F21R2_FB31_Msk (0x1UL << CAN_F21R2_FB31_Pos)

#define	CAN_F21R2_FB31 CAN_F21R2_FB31_Msk

#define	CAN_F22R2_FB0_Pos (0U)

#define	CAN_F22R2_FB0_Msk (0x1UL << CAN_F22R2_FB0_Pos)

#define	CAN_F22R2_FB0 CAN_F22R2_FB0_Msk

#define	CAN_F22R2_FB1_Pos (1U)

#define	CAN_F22R2_FB1_Msk (0x1UL << CAN_F22R2_FB1_Pos)

#define	CAN_F22R2_FB1 CAN_F22R2_FB1_Msk

#define	CAN_F22R2_FB2_Pos (2U)

#define	CAN_F22R2_FB2_Msk (0x1UL << CAN_F22R2_FB2_Pos)

#define	CAN_F22R2_FB2 CAN_F22R2_FB2_Msk

#define	CAN_F22R2_FB3_Pos (3U)

#define	CAN_F22R2_FB3_Msk (0x1UL << CAN_F22R2_FB3_Pos)

#define	CAN_F22R2_FB3 CAN_F22R2_FB3_Msk

#define	CAN_F22R2_FB4_Pos (4U)

#define	CAN_F22R2_FB4_Msk (0x1UL << CAN_F22R2_FB4_Pos)

#define	CAN_F22R2_FB4 CAN_F22R2_FB4_Msk

#define	CAN_F22R2_FB5_Pos (5U)

#define	CAN_F22R2_FB5_Msk (0x1UL << CAN_F22R2_FB5_Pos)

#define	CAN_F22R2_FB5 CAN_F22R2_FB5_Msk

#define	CAN_F22R2_FB6_Pos (6U)

#define	CAN_F22R2_FB6_Msk (0x1UL << CAN_F22R2_FB6_Pos)

#define	CAN_F22R2_FB6 CAN_F22R2_FB6_Msk

#define	CAN_F22R2_FB7_Pos (7U)

#define	CAN_F22R2_FB7_Msk (0x1UL << CAN_F22R2_FB7_Pos)

#define	CAN_F22R2_FB7 CAN_F22R2_FB7_Msk

#define	CAN_F22R2_FB8_Pos (8U)

#define	CAN_F22R2_FB8_Msk (0x1UL << CAN_F22R2_FB8_Pos)

#define	CAN_F22R2_FB8 CAN_F22R2_FB8_Msk

#define	CAN_F22R2_FB9_Pos (9U)

#define	CAN_F22R2_FB9_Msk (0x1UL << CAN_F22R2_FB9_Pos)

#define	CAN_F22R2_FB9 CAN_F22R2_FB9_Msk

#define	CAN_F22R2_FB10_Pos (10U)

#define	CAN_F22R2_FB10_Msk (0x1UL << CAN_F22R2_FB10_Pos)

#define	CAN_F22R2_FB10 CAN_F22R2_FB10_Msk

#define	CAN_F22R2_FB11_Pos (11U)

#define	CAN_F22R2_FB11_Msk (0x1UL << CAN_F22R2_FB11_Pos)

#define	CAN_F22R2_FB11 CAN_F22R2_FB11_Msk

#define	CAN_F22R2_FB12_Pos (12U)

#define	CAN_F22R2_FB12_Msk (0x1UL << CAN_F22R2_FB12_Pos)

#define	CAN_F22R2_FB12 CAN_F22R2_FB12_Msk

#define	CAN_F22R2_FB13_Pos (13U)

#define	CAN_F22R2_FB13_Msk (0x1UL << CAN_F22R2_FB13_Pos)

#define	CAN_F22R2_FB13 CAN_F22R2_FB13_Msk

#define	CAN_F22R2_FB14_Pos (14U)

#define	CAN_F22R2_FB14_Msk (0x1UL << CAN_F22R2_FB14_Pos)

#define	CAN_F22R2_FB14 CAN_F22R2_FB14_Msk

#define	CAN_F22R2_FB15_Pos (15U)

#define	CAN_F22R2_FB15_Msk (0x1UL << CAN_F22R2_FB15_Pos)

#define	CAN_F22R2_FB15 CAN_F22R2_FB15_Msk

#define	CAN_F22R2_FB16_Pos (16U)

#define	CAN_F22R2_FB16_Msk (0x1UL << CAN_F22R2_FB16_Pos)

#define	CAN_F22R2_FB16 CAN_F22R2_FB16_Msk

#define	CAN_F22R2_FB17_Pos (17U)

#define	CAN_F22R2_FB17_Msk (0x1UL << CAN_F22R2_FB17_Pos)

#define	CAN_F22R2_FB17 CAN_F22R2_FB17_Msk

#define	CAN_F22R2_FB18_Pos (18U)

#define	CAN_F22R2_FB18_Msk (0x1UL << CAN_F22R2_FB18_Pos)

#define	CAN_F22R2_FB18 CAN_F22R2_FB18_Msk

#define	CAN_F22R2_FB19_Pos (19U)

#define	CAN_F22R2_FB19_Msk (0x1UL << CAN_F22R2_FB19_Pos)

#define	CAN_F22R2_FB19 CAN_F22R2_FB19_Msk

#define	CAN_F22R2_FB20_Pos (20U)

#define	CAN_F22R2_FB20_Msk (0x1UL << CAN_F22R2_FB20_Pos)

#define	CAN_F22R2_FB20 CAN_F22R2_FB20_Msk

#define	CAN_F22R2_FB21_Pos (21U)

#define	CAN_F22R2_FB21_Msk (0x1UL << CAN_F22R2_FB21_Pos)

#define	CAN_F22R2_FB21 CAN_F22R2_FB21_Msk

#define	CAN_F22R2_FB22_Pos (22U)

#define	CAN_F22R2_FB22_Msk (0x1UL << CAN_F22R2_FB22_Pos)

#define	CAN_F22R2_FB22 CAN_F22R2_FB22_Msk

#define	CAN_F22R2_FB23_Pos (23U)

#define	CAN_F22R2_FB23_Msk (0x1UL << CAN_F22R2_FB23_Pos)

#define	CAN_F22R2_FB23 CAN_F22R2_FB23_Msk

#define	CAN_F22R2_FB24_Pos (24U)

#define	CAN_F22R2_FB24_Msk (0x1UL << CAN_F22R2_FB24_Pos)

#define	CAN_F22R2_FB24 CAN_F22R2_FB24_Msk

#define	CAN_F22R2_FB25_Pos (25U)

#define	CAN_F22R2_FB25_Msk (0x1UL << CAN_F22R2_FB25_Pos)

#define	CAN_F22R2_FB25 CAN_F22R2_FB25_Msk

#define	CAN_F22R2_FB26_Pos (26U)

#define	CAN_F22R2_FB26_Msk (0x1UL << CAN_F22R2_FB26_Pos)

#define	CAN_F22R2_FB26 CAN_F22R2_FB26_Msk

#define	CAN_F22R2_FB27_Pos (27U)

#define	CAN_F22R2_FB27_Msk (0x1UL << CAN_F22R2_FB27_Pos)

#define	CAN_F22R2_FB27 CAN_F22R2_FB27_Msk

#define	CAN_F22R2_FB28_Pos (28U)

#define	CAN_F22R2_FB28_Msk (0x1UL << CAN_F22R2_FB28_Pos)

#define	CAN_F22R2_FB28 CAN_F22R2_FB28_Msk

#define	CAN_F22R2_FB29_Pos (29U)

#define	CAN_F22R2_FB29_Msk (0x1UL << CAN_F22R2_FB29_Pos)

#define	CAN_F22R2_FB29 CAN_F22R2_FB29_Msk

#define	CAN_F22R2_FB30_Pos (30U)

#define	CAN_F22R2_FB30_Msk (0x1UL << CAN_F22R2_FB30_Pos)

#define	CAN_F22R2_FB30 CAN_F22R2_FB30_Msk

#define	CAN_F22R2_FB31_Pos (31U)

#define	CAN_F22R2_FB31_Msk (0x1UL << CAN_F22R2_FB31_Pos)

#define	CAN_F22R2_FB31 CAN_F22R2_FB31_Msk

#define	CAN_F23R2_FB0_Pos (0U)

#define	CAN_F23R2_FB0_Msk (0x1UL << CAN_F23R2_FB0_Pos)

#define	CAN_F23R2_FB0 CAN_F23R2_FB0_Msk

#define	CAN_F23R2_FB1_Pos (1U)

#define	CAN_F23R2_FB1_Msk (0x1UL << CAN_F23R2_FB1_Pos)

#define	CAN_F23R2_FB1 CAN_F23R2_FB1_Msk

#define	CAN_F23R2_FB2_Pos (2U)

#define	CAN_F23R2_FB2_Msk (0x1UL << CAN_F23R2_FB2_Pos)

#define	CAN_F23R2_FB2 CAN_F23R2_FB2_Msk

#define	CAN_F23R2_FB3_Pos (3U)

#define	CAN_F23R2_FB3_Msk (0x1UL << CAN_F23R2_FB3_Pos)

#define	CAN_F23R2_FB3 CAN_F23R2_FB3_Msk

#define	CAN_F23R2_FB4_Pos (4U)

#define	CAN_F23R2_FB4_Msk (0x1UL << CAN_F23R2_FB4_Pos)

#define	CAN_F23R2_FB4 CAN_F23R2_FB4_Msk

#define	CAN_F23R2_FB5_Pos (5U)

#define	CAN_F23R2_FB5_Msk (0x1UL << CAN_F23R2_FB5_Pos)

#define	CAN_F23R2_FB5 CAN_F23R2_FB5_Msk

#define	CAN_F23R2_FB6_Pos (6U)

#define	CAN_F23R2_FB6_Msk (0x1UL << CAN_F23R2_FB6_Pos)

#define	CAN_F23R2_FB6 CAN_F23R2_FB6_Msk

#define	CAN_F23R2_FB7_Pos (7U)

#define	CAN_F23R2_FB7_Msk (0x1UL << CAN_F23R2_FB7_Pos)

#define	CAN_F23R2_FB7 CAN_F23R2_FB7_Msk

#define	CAN_F23R2_FB8_Pos (8U)

#define	CAN_F23R2_FB8_Msk (0x1UL << CAN_F23R2_FB8_Pos)

#define	CAN_F23R2_FB8 CAN_F23R2_FB8_Msk

#define	CAN_F23R2_FB9_Pos (9U)

#define	CAN_F23R2_FB9_Msk (0x1UL << CAN_F23R2_FB9_Pos)

#define	CAN_F23R2_FB9 CAN_F23R2_FB9_Msk

#define	CAN_F23R2_FB10_Pos (10U)

#define	CAN_F23R2_FB10_Msk (0x1UL << CAN_F23R2_FB10_Pos)

#define	CAN_F23R2_FB10 CAN_F23R2_FB10_Msk

#define	CAN_F23R2_FB11_Pos (11U)

#define	CAN_F23R2_FB11_Msk (0x1UL << CAN_F23R2_FB11_Pos)

#define	CAN_F23R2_FB11 CAN_F23R2_FB11_Msk

#define	CAN_F23R2_FB12_Pos (12U)

#define	CAN_F23R2_FB12_Msk (0x1UL << CAN_F23R2_FB12_Pos)

#define	CAN_F23R2_FB12 CAN_F23R2_FB12_Msk

#define	CAN_F23R2_FB13_Pos (13U)

#define	CAN_F23R2_FB13_Msk (0x1UL << CAN_F23R2_FB13_Pos)

#define	CAN_F23R2_FB13 CAN_F23R2_FB13_Msk

#define	CAN_F23R2_FB14_Pos (14U)

#define	CAN_F23R2_FB14_Msk (0x1UL << CAN_F23R2_FB14_Pos)

#define	CAN_F23R2_FB14 CAN_F23R2_FB14_Msk

#define	CAN_F23R2_FB15_Pos (15U)

#define	CAN_F23R2_FB15_Msk (0x1UL << CAN_F23R2_FB15_Pos)

#define	CAN_F23R2_FB15 CAN_F23R2_FB15_Msk

#define	CAN_F23R2_FB16_Pos (16U)

#define	CAN_F23R2_FB16_Msk (0x1UL << CAN_F23R2_FB16_Pos)

#define	CAN_F23R2_FB16 CAN_F23R2_FB16_Msk

#define	CAN_F23R2_FB17_Pos (17U)

#define	CAN_F23R2_FB17_Msk (0x1UL << CAN_F23R2_FB17_Pos)

#define	CAN_F23R2_FB17 CAN_F23R2_FB17_Msk

#define	CAN_F23R2_FB18_Pos (18U)

#define	CAN_F23R2_FB18_Msk (0x1UL << CAN_F23R2_FB18_Pos)

#define	CAN_F23R2_FB18 CAN_F23R2_FB18_Msk

#define	CAN_F23R2_FB19_Pos (19U)

#define	CAN_F23R2_FB19_Msk (0x1UL << CAN_F23R2_FB19_Pos)

#define	CAN_F23R2_FB19 CAN_F23R2_FB19_Msk

#define	CAN_F23R2_FB20_Pos (20U)

#define	CAN_F23R2_FB20_Msk (0x1UL << CAN_F23R2_FB20_Pos)

#define	CAN_F23R2_FB20 CAN_F23R2_FB20_Msk

#define	CAN_F23R2_FB21_Pos (21U)

#define	CAN_F23R2_FB21_Msk (0x1UL << CAN_F23R2_FB21_Pos)

#define	CAN_F23R2_FB21 CAN_F23R2_FB21_Msk

#define	CAN_F23R2_FB22_Pos (22U)

#define	CAN_F23R2_FB22_Msk (0x1UL << CAN_F23R2_FB22_Pos)

#define	CAN_F23R2_FB22 CAN_F23R2_FB22_Msk

#define	CAN_F23R2_FB23_Pos (23U)

#define	CAN_F23R2_FB23_Msk (0x1UL << CAN_F23R2_FB23_Pos)

#define	CAN_F23R2_FB23 CAN_F23R2_FB23_Msk

#define	CAN_F23R2_FB24_Pos (24U)

#define	CAN_F23R2_FB24_Msk (0x1UL << CAN_F23R2_FB24_Pos)

#define	CAN_F23R2_FB24 CAN_F23R2_FB24_Msk

#define	CAN_F23R2_FB25_Pos (25U)

#define	CAN_F23R2_FB25_Msk (0x1UL << CAN_F23R2_FB25_Pos)

#define	CAN_F23R2_FB25 CAN_F23R2_FB25_Msk

#define	CAN_F23R2_FB26_Pos (26U)

#define	CAN_F23R2_FB26_Msk (0x1UL << CAN_F23R2_FB26_Pos)

#define	CAN_F23R2_FB26 CAN_F23R2_FB26_Msk

#define	CAN_F23R2_FB27_Pos (27U)

#define	CAN_F23R2_FB27_Msk (0x1UL << CAN_F23R2_FB27_Pos)

#define	CAN_F23R2_FB27 CAN_F23R2_FB27_Msk

#define	CAN_F23R2_FB28_Pos (28U)

#define	CAN_F23R2_FB28_Msk (0x1UL << CAN_F23R2_FB28_Pos)

#define	CAN_F23R2_FB28 CAN_F23R2_FB28_Msk

#define	CAN_F23R2_FB29_Pos (29U)

#define	CAN_F23R2_FB29_Msk (0x1UL << CAN_F23R2_FB29_Pos)

#define	CAN_F23R2_FB29 CAN_F23R2_FB29_Msk

#define	CAN_F23R2_FB30_Pos (30U)

#define	CAN_F23R2_FB30_Msk (0x1UL << CAN_F23R2_FB30_Pos)

#define	CAN_F23R2_FB30 CAN_F23R2_FB30_Msk

#define	CAN_F23R2_FB31_Pos (31U)

#define	CAN_F23R2_FB31_Msk (0x1UL << CAN_F23R2_FB31_Pos)

#define	CAN_F23R2_FB31 CAN_F23R2_FB31_Msk

#define	CAN_F24R2_FB0_Pos (0U)

#define	CAN_F24R2_FB0_Msk (0x1UL << CAN_F24R2_FB0_Pos)

#define	CAN_F24R2_FB0 CAN_F24R2_FB0_Msk

#define	CAN_F24R2_FB1_Pos (1U)

#define	CAN_F24R2_FB1_Msk (0x1UL << CAN_F24R2_FB1_Pos)

#define	CAN_F24R2_FB1 CAN_F24R2_FB1_Msk

#define	CAN_F24R2_FB2_Pos (2U)

#define	CAN_F24R2_FB2_Msk (0x1UL << CAN_F24R2_FB2_Pos)

#define	CAN_F24R2_FB2 CAN_F24R2_FB2_Msk

#define	CAN_F24R2_FB3_Pos (3U)

#define	CAN_F24R2_FB3_Msk (0x1UL << CAN_F24R2_FB3_Pos)

#define	CAN_F24R2_FB3 CAN_F24R2_FB3_Msk

#define	CAN_F24R2_FB4_Pos (4U)

#define	CAN_F24R2_FB4_Msk (0x1UL << CAN_F24R2_FB4_Pos)

#define	CAN_F24R2_FB4 CAN_F24R2_FB4_Msk

#define	CAN_F24R2_FB5_Pos (5U)

#define	CAN_F24R2_FB5_Msk (0x1UL << CAN_F24R2_FB5_Pos)

#define	CAN_F24R2_FB5 CAN_F24R2_FB5_Msk

#define	CAN_F24R2_FB6_Pos (6U)

#define	CAN_F24R2_FB6_Msk (0x1UL << CAN_F24R2_FB6_Pos)

#define	CAN_F24R2_FB6 CAN_F24R2_FB6_Msk

#define	CAN_F24R2_FB7_Pos (7U)

#define	CAN_F24R2_FB7_Msk (0x1UL << CAN_F24R2_FB7_Pos)

#define	CAN_F24R2_FB7 CAN_F24R2_FB7_Msk

#define	CAN_F24R2_FB8_Pos (8U)

#define	CAN_F24R2_FB8_Msk (0x1UL << CAN_F24R2_FB8_Pos)

#define	CAN_F24R2_FB8 CAN_F24R2_FB8_Msk

#define	CAN_F24R2_FB9_Pos (9U)

#define	CAN_F24R2_FB9_Msk (0x1UL << CAN_F24R2_FB9_Pos)

#define	CAN_F24R2_FB9 CAN_F24R2_FB9_Msk

#define	CAN_F24R2_FB10_Pos (10U)

#define	CAN_F24R2_FB10_Msk (0x1UL << CAN_F24R2_FB10_Pos)

#define	CAN_F24R2_FB10 CAN_F24R2_FB10_Msk

#define	CAN_F24R2_FB11_Pos (11U)

#define	CAN_F24R2_FB11_Msk (0x1UL << CAN_F24R2_FB11_Pos)

#define	CAN_F24R2_FB11 CAN_F24R2_FB11_Msk

#define	CAN_F24R2_FB12_Pos (12U)

#define	CAN_F24R2_FB12_Msk (0x1UL << CAN_F24R2_FB12_Pos)

#define	CAN_F24R2_FB12 CAN_F24R2_FB12_Msk

#define	CAN_F24R2_FB13_Pos (13U)

#define	CAN_F24R2_FB13_Msk (0x1UL << CAN_F24R2_FB13_Pos)

#define	CAN_F24R2_FB13 CAN_F24R2_FB13_Msk

#define	CAN_F24R2_FB14_Pos (14U)

#define	CAN_F24R2_FB14_Msk (0x1UL << CAN_F24R2_FB14_Pos)

#define	CAN_F24R2_FB14 CAN_F24R2_FB14_Msk

#define	CAN_F24R2_FB15_Pos (15U)

#define	CAN_F24R2_FB15_Msk (0x1UL << CAN_F24R2_FB15_Pos)

#define	CAN_F24R2_FB15 CAN_F24R2_FB15_Msk

#define	CAN_F24R2_FB16_Pos (16U)

#define	CAN_F24R2_FB16_Msk (0x1UL << CAN_F24R2_FB16_Pos)

#define	CAN_F24R2_FB16 CAN_F24R2_FB16_Msk

#define	CAN_F24R2_FB17_Pos (17U)

#define	CAN_F24R2_FB17_Msk (0x1UL << CAN_F24R2_FB17_Pos)

#define	CAN_F24R2_FB17 CAN_F24R2_FB17_Msk

#define	CAN_F24R2_FB18_Pos (18U)

#define	CAN_F24R2_FB18_Msk (0x1UL << CAN_F24R2_FB18_Pos)

#define	CAN_F24R2_FB18 CAN_F24R2_FB18_Msk

#define	CAN_F24R2_FB19_Pos (19U)

#define	CAN_F24R2_FB19_Msk (0x1UL << CAN_F24R2_FB19_Pos)

#define	CAN_F24R2_FB19 CAN_F24R2_FB19_Msk

#define	CAN_F24R2_FB20_Pos (20U)

#define	CAN_F24R2_FB20_Msk (0x1UL << CAN_F24R2_FB20_Pos)

#define	CAN_F24R2_FB20 CAN_F24R2_FB20_Msk

#define	CAN_F24R2_FB21_Pos (21U)

#define	CAN_F24R2_FB21_Msk (0x1UL << CAN_F24R2_FB21_Pos)

#define	CAN_F24R2_FB21 CAN_F24R2_FB21_Msk

#define	CAN_F24R2_FB22_Pos (22U)

#define	CAN_F24R2_FB22_Msk (0x1UL << CAN_F24R2_FB22_Pos)

#define	CAN_F24R2_FB22 CAN_F24R2_FB22_Msk

#define	CAN_F24R2_FB23_Pos (23U)

#define	CAN_F24R2_FB23_Msk (0x1UL << CAN_F24R2_FB23_Pos)

#define	CAN_F24R2_FB23 CAN_F24R2_FB23_Msk

#define	CAN_F24R2_FB24_Pos (24U)

#define	CAN_F24R2_FB24_Msk (0x1UL << CAN_F24R2_FB24_Pos)

#define	CAN_F24R2_FB24 CAN_F24R2_FB24_Msk

#define	CAN_F24R2_FB25_Pos (25U)

#define	CAN_F24R2_FB25_Msk (0x1UL << CAN_F24R2_FB25_Pos)

#define	CAN_F24R2_FB25 CAN_F24R2_FB25_Msk

#define	CAN_F24R2_FB26_Pos (26U)

#define	CAN_F24R2_FB26_Msk (0x1UL << CAN_F24R2_FB26_Pos)

#define	CAN_F24R2_FB26 CAN_F24R2_FB26_Msk

#define	CAN_F24R2_FB27_Pos (27U)

#define	CAN_F24R2_FB27_Msk (0x1UL << CAN_F24R2_FB27_Pos)

#define	CAN_F24R2_FB27 CAN_F24R2_FB27_Msk

#define	CAN_F24R2_FB28_Pos (28U)

#define	CAN_F24R2_FB28_Msk (0x1UL << CAN_F24R2_FB28_Pos)

#define	CAN_F24R2_FB28 CAN_F24R2_FB28_Msk

#define	CAN_F24R2_FB29_Pos (29U)

#define	CAN_F24R2_FB29_Msk (0x1UL << CAN_F24R2_FB29_Pos)

#define	CAN_F24R2_FB29 CAN_F24R2_FB29_Msk

#define	CAN_F24R2_FB30_Pos (30U)

#define	CAN_F24R2_FB30_Msk (0x1UL << CAN_F24R2_FB30_Pos)

#define	CAN_F24R2_FB30 CAN_F24R2_FB30_Msk

#define	CAN_F24R2_FB31_Pos (31U)

#define	CAN_F24R2_FB31_Msk (0x1UL << CAN_F24R2_FB31_Pos)

#define	CAN_F24R2_FB31 CAN_F24R2_FB31_Msk

#define	CAN_F25R2_FB0_Pos (0U)

#define	CAN_F25R2_FB0_Msk (0x1UL << CAN_F25R2_FB0_Pos)

#define	CAN_F25R2_FB0 CAN_F25R2_FB0_Msk

#define	CAN_F25R2_FB1_Pos (1U)

#define	CAN_F25R2_FB1_Msk (0x1UL << CAN_F25R2_FB1_Pos)

#define	CAN_F25R2_FB1 CAN_F25R2_FB1_Msk

#define	CAN_F25R2_FB2_Pos (2U)

#define	CAN_F25R2_FB2_Msk (0x1UL << CAN_F25R2_FB2_Pos)

#define	CAN_F25R2_FB2 CAN_F25R2_FB2_Msk

#define	CAN_F25R2_FB3_Pos (3U)

#define	CAN_F25R2_FB3_Msk (0x1UL << CAN_F25R2_FB3_Pos)

#define	CAN_F25R2_FB3 CAN_F25R2_FB3_Msk

#define	CAN_F25R2_FB4_Pos (4U)

#define	CAN_F25R2_FB4_Msk (0x1UL << CAN_F25R2_FB4_Pos)

#define	CAN_F25R2_FB4 CAN_F25R2_FB4_Msk

#define	CAN_F25R2_FB5_Pos (5U)

#define	CAN_F25R2_FB5_Msk (0x1UL << CAN_F25R2_FB5_Pos)

#define	CAN_F25R2_FB5 CAN_F25R2_FB5_Msk

#define	CAN_F25R2_FB6_Pos (6U)

#define	CAN_F25R2_FB6_Msk (0x1UL << CAN_F25R2_FB6_Pos)

#define	CAN_F25R2_FB6 CAN_F25R2_FB6_Msk

#define	CAN_F25R2_FB7_Pos (7U)

#define	CAN_F25R2_FB7_Msk (0x1UL << CAN_F25R2_FB7_Pos)

#define	CAN_F25R2_FB7 CAN_F25R2_FB7_Msk

#define	CAN_F25R2_FB8_Pos (8U)

#define	CAN_F25R2_FB8_Msk (0x1UL << CAN_F25R2_FB8_Pos)

#define	CAN_F25R2_FB8 CAN_F25R2_FB8_Msk

#define	CAN_F25R2_FB9_Pos (9U)

#define	CAN_F25R2_FB9_Msk (0x1UL << CAN_F25R2_FB9_Pos)

#define	CAN_F25R2_FB9 CAN_F25R2_FB9_Msk

#define	CAN_F25R2_FB10_Pos (10U)

#define	CAN_F25R2_FB10_Msk (0x1UL << CAN_F25R2_FB10_Pos)

#define	CAN_F25R2_FB10 CAN_F25R2_FB10_Msk

#define	CAN_F25R2_FB11_Pos (11U)

#define	CAN_F25R2_FB11_Msk (0x1UL << CAN_F25R2_FB11_Pos)

#define	CAN_F25R2_FB11 CAN_F25R2_FB11_Msk

#define	CAN_F25R2_FB12_Pos (12U)

#define	CAN_F25R2_FB12_Msk (0x1UL << CAN_F25R2_FB12_Pos)

#define	CAN_F25R2_FB12 CAN_F25R2_FB12_Msk

#define	CAN_F25R2_FB13_Pos (13U)

#define	CAN_F25R2_FB13_Msk (0x1UL << CAN_F25R2_FB13_Pos)

#define	CAN_F25R2_FB13 CAN_F25R2_FB13_Msk

#define	CAN_F25R2_FB14_Pos (14U)

#define	CAN_F25R2_FB14_Msk (0x1UL << CAN_F25R2_FB14_Pos)

#define	CAN_F25R2_FB14 CAN_F25R2_FB14_Msk

#define	CAN_F25R2_FB15_Pos (15U)

#define	CAN_F25R2_FB15_Msk (0x1UL << CAN_F25R2_FB15_Pos)

#define	CAN_F25R2_FB15 CAN_F25R2_FB15_Msk

#define	CAN_F25R2_FB16_Pos (16U)

#define	CAN_F25R2_FB16_Msk (0x1UL << CAN_F25R2_FB16_Pos)

#define	CAN_F25R2_FB16 CAN_F25R2_FB16_Msk

#define	CAN_F25R2_FB17_Pos (17U)

#define	CAN_F25R2_FB17_Msk (0x1UL << CAN_F25R2_FB17_Pos)

#define	CAN_F25R2_FB17 CAN_F25R2_FB17_Msk

#define	CAN_F25R2_FB18_Pos (18U)

#define	CAN_F25R2_FB18_Msk (0x1UL << CAN_F25R2_FB18_Pos)

#define	CAN_F25R2_FB18 CAN_F25R2_FB18_Msk

#define	CAN_F25R2_FB19_Pos (19U)

#define	CAN_F25R2_FB19_Msk (0x1UL << CAN_F25R2_FB19_Pos)

#define	CAN_F25R2_FB19 CAN_F25R2_FB19_Msk

#define	CAN_F25R2_FB20_Pos (20U)

#define	CAN_F25R2_FB20_Msk (0x1UL << CAN_F25R2_FB20_Pos)

#define	CAN_F25R2_FB20 CAN_F25R2_FB20_Msk

#define	CAN_F25R2_FB21_Pos (21U)

#define	CAN_F25R2_FB21_Msk (0x1UL << CAN_F25R2_FB21_Pos)

#define	CAN_F25R2_FB21 CAN_F25R2_FB21_Msk

#define	CAN_F25R2_FB22_Pos (22U)

#define	CAN_F25R2_FB22_Msk (0x1UL << CAN_F25R2_FB22_Pos)

#define	CAN_F25R2_FB22 CAN_F25R2_FB22_Msk

#define	CAN_F25R2_FB23_Pos (23U)

#define	CAN_F25R2_FB23_Msk (0x1UL << CAN_F25R2_FB23_Pos)

#define	CAN_F25R2_FB23 CAN_F25R2_FB23_Msk

#define	CAN_F25R2_FB24_Pos (24U)

#define	CAN_F25R2_FB24_Msk (0x1UL << CAN_F25R2_FB24_Pos)

#define	CAN_F25R2_FB24 CAN_F25R2_FB24_Msk

#define	CAN_F25R2_FB25_Pos (25U)

#define	CAN_F25R2_FB25_Msk (0x1UL << CAN_F25R2_FB25_Pos)

#define	CAN_F25R2_FB25 CAN_F25R2_FB25_Msk

#define	CAN_F25R2_FB26_Pos (26U)

#define	CAN_F25R2_FB26_Msk (0x1UL << CAN_F25R2_FB26_Pos)

#define	CAN_F25R2_FB26 CAN_F25R2_FB26_Msk

#define	CAN_F25R2_FB27_Pos (27U)

#define	CAN_F25R2_FB27_Msk (0x1UL << CAN_F25R2_FB27_Pos)

#define	CAN_F25R2_FB27 CAN_F25R2_FB27_Msk

#define	CAN_F25R2_FB28_Pos (28U)

#define	CAN_F25R2_FB28_Msk (0x1UL << CAN_F25R2_FB28_Pos)

#define	CAN_F25R2_FB28 CAN_F25R2_FB28_Msk

#define	CAN_F25R2_FB29_Pos (29U)

#define	CAN_F25R2_FB29_Msk (0x1UL << CAN_F25R2_FB29_Pos)

#define	CAN_F25R2_FB29 CAN_F25R2_FB29_Msk

#define	CAN_F25R2_FB30_Pos (30U)

#define	CAN_F25R2_FB30_Msk (0x1UL << CAN_F25R2_FB30_Pos)

#define	CAN_F25R2_FB30 CAN_F25R2_FB30_Msk

#define	CAN_F25R2_FB31_Pos (31U)

#define	CAN_F25R2_FB31_Msk (0x1UL << CAN_F25R2_FB31_Pos)

#define	CAN_F25R2_FB31 CAN_F25R2_FB31_Msk

#define	CAN_F26R2_FB0_Pos (0U)

#define	CAN_F26R2_FB0_Msk (0x1UL << CAN_F26R2_FB0_Pos)

#define	CAN_F26R2_FB0 CAN_F26R2_FB0_Msk

#define	CAN_F26R2_FB1_Pos (1U)

#define	CAN_F26R2_FB1_Msk (0x1UL << CAN_F26R2_FB1_Pos)

#define	CAN_F26R2_FB1 CAN_F26R2_FB1_Msk

#define	CAN_F26R2_FB2_Pos (2U)

#define	CAN_F26R2_FB2_Msk (0x1UL << CAN_F26R2_FB2_Pos)

#define	CAN_F26R2_FB2 CAN_F26R2_FB2_Msk

#define	CAN_F26R2_FB3_Pos (3U)

#define	CAN_F26R2_FB3_Msk (0x1UL << CAN_F26R2_FB3_Pos)

#define	CAN_F26R2_FB3 CAN_F26R2_FB3_Msk

#define	CAN_F26R2_FB4_Pos (4U)

#define	CAN_F26R2_FB4_Msk (0x1UL << CAN_F26R2_FB4_Pos)

#define	CAN_F26R2_FB4 CAN_F26R2_FB4_Msk

#define	CAN_F26R2_FB5_Pos (5U)

#define	CAN_F26R2_FB5_Msk (0x1UL << CAN_F26R2_FB5_Pos)

#define	CAN_F26R2_FB5 CAN_F26R2_FB5_Msk

#define	CAN_F26R2_FB6_Pos (6U)

#define	CAN_F26R2_FB6_Msk (0x1UL << CAN_F26R2_FB6_Pos)

#define	CAN_F26R2_FB6 CAN_F26R2_FB6_Msk

#define	CAN_F26R2_FB7_Pos (7U)

#define	CAN_F26R2_FB7_Msk (0x1UL << CAN_F26R2_FB7_Pos)

#define	CAN_F26R2_FB7 CAN_F26R2_FB7_Msk

#define	CAN_F26R2_FB8_Pos (8U)

#define	CAN_F26R2_FB8_Msk (0x1UL << CAN_F26R2_FB8_Pos)

#define	CAN_F26R2_FB8 CAN_F26R2_FB8_Msk

#define	CAN_F26R2_FB9_Pos (9U)

#define	CAN_F26R2_FB9_Msk (0x1UL << CAN_F26R2_FB9_Pos)

#define	CAN_F26R2_FB9 CAN_F26R2_FB9_Msk

#define	CAN_F26R2_FB10_Pos (10U)

#define	CAN_F26R2_FB10_Msk (0x1UL << CAN_F26R2_FB10_Pos)

#define	CAN_F26R2_FB10 CAN_F26R2_FB10_Msk

#define	CAN_F26R2_FB11_Pos (11U)

#define	CAN_F26R2_FB11_Msk (0x1UL << CAN_F26R2_FB11_Pos)

#define	CAN_F26R2_FB11 CAN_F26R2_FB11_Msk

#define	CAN_F26R2_FB12_Pos (12U)

#define	CAN_F26R2_FB12_Msk (0x1UL << CAN_F26R2_FB12_Pos)

#define	CAN_F26R2_FB12 CAN_F26R2_FB12_Msk

#define	CAN_F26R2_FB13_Pos (13U)

#define	CAN_F26R2_FB13_Msk (0x1UL << CAN_F26R2_FB13_Pos)

#define	CAN_F26R2_FB13 CAN_F26R2_FB13_Msk

#define	CAN_F26R2_FB14_Pos (14U)

#define	CAN_F26R2_FB14_Msk (0x1UL << CAN_F26R2_FB14_Pos)

#define	CAN_F26R2_FB14 CAN_F26R2_FB14_Msk

#define	CAN_F26R2_FB15_Pos (15U)

#define	CAN_F26R2_FB15_Msk (0x1UL << CAN_F26R2_FB15_Pos)

#define	CAN_F26R2_FB15 CAN_F26R2_FB15_Msk

#define	CAN_F26R2_FB16_Pos (16U)

#define	CAN_F26R2_FB16_Msk (0x1UL << CAN_F26R2_FB16_Pos)

#define	CAN_F26R2_FB16 CAN_F26R2_FB16_Msk

#define	CAN_F26R2_FB17_Pos (17U)

#define	CAN_F26R2_FB17_Msk (0x1UL << CAN_F26R2_FB17_Pos)

#define	CAN_F26R2_FB17 CAN_F26R2_FB17_Msk

#define	CAN_F26R2_FB18_Pos (18U)

#define	CAN_F26R2_FB18_Msk (0x1UL << CAN_F26R2_FB18_Pos)

#define	CAN_F26R2_FB18 CAN_F26R2_FB18_Msk

#define	CAN_F26R2_FB19_Pos (19U)

#define	CAN_F26R2_FB19_Msk (0x1UL << CAN_F26R2_FB19_Pos)

#define	CAN_F26R2_FB19 CAN_F26R2_FB19_Msk

#define	CAN_F26R2_FB20_Pos (20U)

#define	CAN_F26R2_FB20_Msk (0x1UL << CAN_F26R2_FB20_Pos)

#define	CAN_F26R2_FB20 CAN_F26R2_FB20_Msk

#define	CAN_F26R2_FB21_Pos (21U)

#define	CAN_F26R2_FB21_Msk (0x1UL << CAN_F26R2_FB21_Pos)

#define	CAN_F26R2_FB21 CAN_F26R2_FB21_Msk

#define	CAN_F26R2_FB22_Pos (22U)

#define	CAN_F26R2_FB22_Msk (0x1UL << CAN_F26R2_FB22_Pos)

#define	CAN_F26R2_FB22 CAN_F26R2_FB22_Msk

#define	CAN_F26R2_FB23_Pos (23U)

#define	CAN_F26R2_FB23_Msk (0x1UL << CAN_F26R2_FB23_Pos)

#define	CAN_F26R2_FB23 CAN_F26R2_FB23_Msk

#define	CAN_F26R2_FB24_Pos (24U)

#define	CAN_F26R2_FB24_Msk (0x1UL << CAN_F26R2_FB24_Pos)

#define	CAN_F26R2_FB24 CAN_F26R2_FB24_Msk

#define	CAN_F26R2_FB25_Pos (25U)

#define	CAN_F26R2_FB25_Msk (0x1UL << CAN_F26R2_FB25_Pos)

#define	CAN_F26R2_FB25 CAN_F26R2_FB25_Msk

#define	CAN_F26R2_FB26_Pos (26U)

#define	CAN_F26R2_FB26_Msk (0x1UL << CAN_F26R2_FB26_Pos)

#define	CAN_F26R2_FB26 CAN_F26R2_FB26_Msk

#define	CAN_F26R2_FB27_Pos (27U)

#define	CAN_F26R2_FB27_Msk (0x1UL << CAN_F26R2_FB27_Pos)

#define	CAN_F26R2_FB27 CAN_F26R2_FB27_Msk

#define	CAN_F26R2_FB28_Pos (28U)

#define	CAN_F26R2_FB28_Msk (0x1UL << CAN_F26R2_FB28_Pos)

#define	CAN_F26R2_FB28 CAN_F26R2_FB28_Msk

#define	CAN_F26R2_FB29_Pos (29U)

#define	CAN_F26R2_FB29_Msk (0x1UL << CAN_F26R2_FB29_Pos)

#define	CAN_F26R2_FB29 CAN_F26R2_FB29_Msk

#define	CAN_F26R2_FB30_Pos (30U)

#define	CAN_F26R2_FB30_Msk (0x1UL << CAN_F26R2_FB30_Pos)

#define	CAN_F26R2_FB30 CAN_F26R2_FB30_Msk

#define	CAN_F26R2_FB31_Pos (31U)

#define	CAN_F26R2_FB31_Msk (0x1UL << CAN_F26R2_FB31_Pos)

#define	CAN_F26R2_FB31 CAN_F26R2_FB31_Msk

#define	CAN_F27R2_FB0_Pos (0U)

#define	CAN_F27R2_FB0_Msk (0x1UL << CAN_F27R2_FB0_Pos)

#define	CAN_F27R2_FB0 CAN_F27R2_FB0_Msk

#define	CAN_F27R2_FB1_Pos (1U)

#define	CAN_F27R2_FB1_Msk (0x1UL << CAN_F27R2_FB1_Pos)

#define	CAN_F27R2_FB1 CAN_F27R2_FB1_Msk

#define	CAN_F27R2_FB2_Pos (2U)

#define	CAN_F27R2_FB2_Msk (0x1UL << CAN_F27R2_FB2_Pos)

#define	CAN_F27R2_FB2 CAN_F27R2_FB2_Msk

#define	CAN_F27R2_FB3_Pos (3U)

#define	CAN_F27R2_FB3_Msk (0x1UL << CAN_F27R2_FB3_Pos)

#define	CAN_F27R2_FB3 CAN_F27R2_FB3_Msk

#define	CAN_F27R2_FB4_Pos (4U)

#define	CAN_F27R2_FB4_Msk (0x1UL << CAN_F27R2_FB4_Pos)

#define	CAN_F27R2_FB4 CAN_F27R2_FB4_Msk

#define	CAN_F27R2_FB5_Pos (5U)

#define	CAN_F27R2_FB5_Msk (0x1UL << CAN_F27R2_FB5_Pos)

#define	CAN_F27R2_FB5 CAN_F27R2_FB5_Msk

#define	CAN_F27R2_FB6_Pos (6U)

#define	CAN_F27R2_FB6_Msk (0x1UL << CAN_F27R2_FB6_Pos)

#define	CAN_F27R2_FB6 CAN_F27R2_FB6_Msk

#define	CAN_F27R2_FB7_Pos (7U)

#define	CAN_F27R2_FB7_Msk (0x1UL << CAN_F27R2_FB7_Pos)

#define	CAN_F27R2_FB7 CAN_F27R2_FB7_Msk

#define	CAN_F27R2_FB8_Pos (8U)

#define	CAN_F27R2_FB8_Msk (0x1UL << CAN_F27R2_FB8_Pos)

#define	CAN_F27R2_FB8 CAN_F27R2_FB8_Msk

#define	CAN_F27R2_FB9_Pos (9U)

#define	CAN_F27R2_FB9_Msk (0x1UL << CAN_F27R2_FB9_Pos)

#define	CAN_F27R2_FB9 CAN_F27R2_FB9_Msk

#define	CAN_F27R2_FB10_Pos (10U)

#define	CAN_F27R2_FB10_Msk (0x1UL << CAN_F27R2_FB10_Pos)

#define	CAN_F27R2_FB10 CAN_F27R2_FB10_Msk

#define	CAN_F27R2_FB11_Pos (11U)

#define	CAN_F27R2_FB11_Msk (0x1UL << CAN_F27R2_FB11_Pos)

#define	CAN_F27R2_FB11 CAN_F27R2_FB11_Msk

#define	CAN_F27R2_FB12_Pos (12U)

#define	CAN_F27R2_FB12_Msk (0x1UL << CAN_F27R2_FB12_Pos)

#define	CAN_F27R2_FB12 CAN_F27R2_FB12_Msk

#define	CAN_F27R2_FB13_Pos (13U)

#define	CAN_F27R2_FB13_Msk (0x1UL << CAN_F27R2_FB13_Pos)

#define	CAN_F27R2_FB13 CAN_F27R2_FB13_Msk

#define	CAN_F27R2_FB14_Pos (14U)

#define	CAN_F27R2_FB14_Msk (0x1UL << CAN_F27R2_FB14_Pos)

#define	CAN_F27R2_FB14 CAN_F27R2_FB14_Msk

#define	CAN_F27R2_FB15_Pos (15U)

#define	CAN_F27R2_FB15_Msk (0x1UL << CAN_F27R2_FB15_Pos)

#define	CAN_F27R2_FB15 CAN_F27R2_FB15_Msk

#define	CAN_F27R2_FB16_Pos (16U)

#define	CAN_F27R2_FB16_Msk (0x1UL << CAN_F27R2_FB16_Pos)

#define	CAN_F27R2_FB16 CAN_F27R2_FB16_Msk

#define	CAN_F27R2_FB17_Pos (17U)

#define	CAN_F27R2_FB17_Msk (0x1UL << CAN_F27R2_FB17_Pos)

#define	CAN_F27R2_FB17 CAN_F27R2_FB17_Msk

#define	CAN_F27R2_FB18_Pos (18U)

#define	CAN_F27R2_FB18_Msk (0x1UL << CAN_F27R2_FB18_Pos)

#define	CAN_F27R2_FB18 CAN_F27R2_FB18_Msk

#define	CAN_F27R2_FB19_Pos (19U)

#define	CAN_F27R2_FB19_Msk (0x1UL << CAN_F27R2_FB19_Pos)

#define	CAN_F27R2_FB19 CAN_F27R2_FB19_Msk

#define	CAN_F27R2_FB20_Pos (20U)

#define	CAN_F27R2_FB20_Msk (0x1UL << CAN_F27R2_FB20_Pos)

#define	CAN_F27R2_FB20 CAN_F27R2_FB20_Msk

#define	CAN_F27R2_FB21_Pos (21U)

#define	CAN_F27R2_FB21_Msk (0x1UL << CAN_F27R2_FB21_Pos)

#define	CAN_F27R2_FB21 CAN_F27R2_FB21_Msk

#define	CAN_F27R2_FB22_Pos (22U)

#define	CAN_F27R2_FB22_Msk (0x1UL << CAN_F27R2_FB22_Pos)

#define	CAN_F27R2_FB22 CAN_F27R2_FB22_Msk

#define	CAN_F27R2_FB23_Pos (23U)

#define	CAN_F27R2_FB23_Msk (0x1UL << CAN_F27R2_FB23_Pos)

#define	CAN_F27R2_FB23 CAN_F27R2_FB23_Msk

#define	CAN_F27R2_FB24_Pos (24U)

#define	CAN_F27R2_FB24_Msk (0x1UL << CAN_F27R2_FB24_Pos)

#define	CAN_F27R2_FB24 CAN_F27R2_FB24_Msk

#define	CAN_F27R2_FB25_Pos (25U)

#define	CAN_F27R2_FB25_Msk (0x1UL << CAN_F27R2_FB25_Pos)

#define	CAN_F27R2_FB25 CAN_F27R2_FB25_Msk

#define	CAN_F27R2_FB26_Pos (26U)

#define	CAN_F27R2_FB26_Msk (0x1UL << CAN_F27R2_FB26_Pos)

#define	CAN_F27R2_FB26 CAN_F27R2_FB26_Msk

#define	CAN_F27R2_FB27_Pos (27U)

#define	CAN_F27R2_FB27_Msk (0x1UL << CAN_F27R2_FB27_Pos)

#define	CAN_F27R2_FB27 CAN_F27R2_FB27_Msk

#define	CAN_F27R2_FB28_Pos (28U)

#define	CAN_F27R2_FB28_Msk (0x1UL << CAN_F27R2_FB28_Pos)

#define	CAN_F27R2_FB28 CAN_F27R2_FB28_Msk

#define	CAN_F27R2_FB29_Pos (29U)

#define	CAN_F27R2_FB29_Msk (0x1UL << CAN_F27R2_FB29_Pos)

#define	CAN_F27R2_FB29 CAN_F27R2_FB29_Msk

#define	CAN_F27R2_FB30_Pos (30U)

#define	CAN_F27R2_FB30_Msk (0x1UL << CAN_F27R2_FB30_Pos)

#define	CAN_F27R2_FB30 CAN_F27R2_FB30_Msk

#define	CAN_F27R2_FB31_Pos (31U)

#define	CAN_F27R2_FB31_Msk (0x1UL << CAN_F27R2_FB31_Pos)

#define	CAN_F27R2_FB31 CAN_F27R2_FB31_Msk

#define	SPI_I2S_SUPPORT

#define	I2S2_I2S3_CLOCK_FEATURE

#define	SPI_CR1_CPHA_Pos (0U)

#define	SPI_CR1_CPHA_Msk (0x1UL << SPI_CR1_CPHA_Pos)

#define	SPI_CR1_CPHA SPI_CR1_CPHA_Msk

#define	SPI_CR1_CPOL_Pos (1U)

#define	SPI_CR1_CPOL_Msk (0x1UL << SPI_CR1_CPOL_Pos)

#define	SPI_CR1_CPOL SPI_CR1_CPOL_Msk

#define	SPI_CR1_MSTR_Pos (2U)

#define	SPI_CR1_MSTR_Msk (0x1UL << SPI_CR1_MSTR_Pos)

#define	SPI_CR1_MSTR SPI_CR1_MSTR_Msk

#define	SPI_CR1_BR_Pos (3U)

#define	SPI_CR1_BR_Msk (0x7UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR SPI_CR1_BR_Msk

#define	SPI_CR1_BR_0 (0x1UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_1 (0x2UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_BR_2 (0x4UL << SPI_CR1_BR_Pos)

#define	SPI_CR1_SPE_Pos (6U)

#define	SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos)

#define	SPI_CR1_SPE SPI_CR1_SPE_Msk

#define	SPI_CR1_LSBFIRST_Pos (7U)

#define	SPI_CR1_LSBFIRST_Msk (0x1UL << SPI_CR1_LSBFIRST_Pos)

#define	SPI_CR1_LSBFIRST SPI_CR1_LSBFIRST_Msk

#define	SPI_CR1_SSI_Pos (8U)

#define	SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos)

#define	SPI_CR1_SSI SPI_CR1_SSI_Msk

#define	SPI_CR1_SSM_Pos (9U)

#define	SPI_CR1_SSM_Msk (0x1UL << SPI_CR1_SSM_Pos)

#define	SPI_CR1_SSM SPI_CR1_SSM_Msk

#define	SPI_CR1_RXONLY_Pos (10U)

#define	SPI_CR1_RXONLY_Msk (0x1UL << SPI_CR1_RXONLY_Pos)

#define	SPI_CR1_RXONLY SPI_CR1_RXONLY_Msk

#define	SPI_CR1_DFF_Pos (11U)

#define	SPI_CR1_DFF_Msk (0x1UL << SPI_CR1_DFF_Pos)

#define	SPI_CR1_DFF SPI_CR1_DFF_Msk

#define	SPI_CR1_CRCNEXT_Pos (12U)

#define	SPI_CR1_CRCNEXT_Msk (0x1UL << SPI_CR1_CRCNEXT_Pos)

#define	SPI_CR1_CRCNEXT SPI_CR1_CRCNEXT_Msk

#define	SPI_CR1_CRCEN_Pos (13U)

#define	SPI_CR1_CRCEN_Msk (0x1UL << SPI_CR1_CRCEN_Pos)

#define	SPI_CR1_CRCEN SPI_CR1_CRCEN_Msk

#define	SPI_CR1_BIDIOE_Pos (14U)

#define	SPI_CR1_BIDIOE_Msk (0x1UL << SPI_CR1_BIDIOE_Pos)

#define	SPI_CR1_BIDIOE SPI_CR1_BIDIOE_Msk

#define	SPI_CR1_BIDIMODE_Pos (15U)

#define	SPI_CR1_BIDIMODE_Msk (0x1UL << SPI_CR1_BIDIMODE_Pos)

#define	SPI_CR1_BIDIMODE SPI_CR1_BIDIMODE_Msk

#define	SPI_CR2_RXDMAEN_Pos (0U)

#define	SPI_CR2_RXDMAEN_Msk (0x1UL << SPI_CR2_RXDMAEN_Pos)

#define	SPI_CR2_RXDMAEN SPI_CR2_RXDMAEN_Msk

#define	SPI_CR2_TXDMAEN_Pos (1U)

#define	SPI_CR2_TXDMAEN_Msk (0x1UL << SPI_CR2_TXDMAEN_Pos)

#define	SPI_CR2_TXDMAEN SPI_CR2_TXDMAEN_Msk

#define	SPI_CR2_SSOE_Pos (2U)

#define	SPI_CR2_SSOE_Msk (0x1UL << SPI_CR2_SSOE_Pos)

#define	SPI_CR2_SSOE SPI_CR2_SSOE_Msk

#define	SPI_CR2_ERRIE_Pos (5U)

#define	SPI_CR2_ERRIE_Msk (0x1UL << SPI_CR2_ERRIE_Pos)

#define	SPI_CR2_ERRIE SPI_CR2_ERRIE_Msk

#define	SPI_CR2_RXNEIE_Pos (6U)

#define	SPI_CR2_RXNEIE_Msk (0x1UL << SPI_CR2_RXNEIE_Pos)

#define	SPI_CR2_RXNEIE SPI_CR2_RXNEIE_Msk

#define	SPI_CR2_TXEIE_Pos (7U)

#define	SPI_CR2_TXEIE_Msk (0x1UL << SPI_CR2_TXEIE_Pos)

#define	SPI_CR2_TXEIE SPI_CR2_TXEIE_Msk

#define	SPI_SR_RXNE_Pos (0U)

#define	SPI_SR_RXNE_Msk (0x1UL << SPI_SR_RXNE_Pos)

#define	SPI_SR_RXNE SPI_SR_RXNE_Msk

#define	SPI_SR_TXE_Pos (1U)

#define	SPI_SR_TXE_Msk (0x1UL << SPI_SR_TXE_Pos)

#define	SPI_SR_TXE SPI_SR_TXE_Msk

#define	SPI_SR_CHSIDE_Pos (2U)

#define	SPI_SR_CHSIDE_Msk (0x1UL << SPI_SR_CHSIDE_Pos)

#define	SPI_SR_CHSIDE SPI_SR_CHSIDE_Msk

#define	SPI_SR_UDR_Pos (3U)

#define	SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos)

#define	SPI_SR_UDR SPI_SR_UDR_Msk

#define	SPI_SR_CRCERR_Pos (4U)

#define	SPI_SR_CRCERR_Msk (0x1UL << SPI_SR_CRCERR_Pos)

#define	SPI_SR_CRCERR SPI_SR_CRCERR_Msk

#define	SPI_SR_MODF_Pos (5U)

#define	SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos)

#define	SPI_SR_MODF SPI_SR_MODF_Msk

#define	SPI_SR_OVR_Pos (6U)

#define	SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos)

#define	SPI_SR_OVR SPI_SR_OVR_Msk

#define	SPI_SR_BSY_Pos (7U)

#define	SPI_SR_BSY_Msk (0x1UL << SPI_SR_BSY_Pos)

#define	SPI_SR_BSY SPI_SR_BSY_Msk

#define	SPI_DR_DR_Pos (0U)

#define	SPI_DR_DR_Msk (0xFFFFUL << SPI_DR_DR_Pos)

#define	SPI_DR_DR SPI_DR_DR_Msk

#define	SPI_CRCPR_CRCPOLY_Pos (0U)

#define	SPI_CRCPR_CRCPOLY_Msk (0xFFFFUL << SPI_CRCPR_CRCPOLY_Pos)

#define	SPI_CRCPR_CRCPOLY SPI_CRCPR_CRCPOLY_Msk

#define	SPI_RXCRCR_RXCRC_Pos (0U)

#define	SPI_RXCRCR_RXCRC_Msk (0xFFFFUL << SPI_RXCRCR_RXCRC_Pos)

#define	SPI_RXCRCR_RXCRC SPI_RXCRCR_RXCRC_Msk

#define	SPI_TXCRCR_TXCRC_Pos (0U)

#define	SPI_TXCRCR_TXCRC_Msk (0xFFFFUL << SPI_TXCRCR_TXCRC_Pos)

#define	SPI_TXCRCR_TXCRC SPI_TXCRCR_TXCRC_Msk

#define	SPI_I2SCFGR_CHLEN_Pos (0U)

#define	SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos)

#define	SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk

#define	SPI_I2SCFGR_DATLEN_Pos (1U)

#define	SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk

#define	SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos)

#define	SPI_I2SCFGR_CKPOL_Pos (3U)

#define	SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos)

#define	SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk

#define	SPI_I2SCFGR_I2SSTD_Pos (4U)

#define	SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk

#define	SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos)

#define	SPI_I2SCFGR_PCMSYNC_Pos (7U)

#define	SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos)

#define	SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk

#define	SPI_I2SCFGR_I2SCFG_Pos (8U)

#define	SPI_I2SCFGR_I2SCFG_Msk (0x3UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk

#define	SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos)

#define	SPI_I2SCFGR_I2SE_Pos (10U)

#define	SPI_I2SCFGR_I2SE_Msk (0x1UL << SPI_I2SCFGR_I2SE_Pos)

#define	SPI_I2SCFGR_I2SE SPI_I2SCFGR_I2SE_Msk

#define	SPI_I2SCFGR_I2SMOD_Pos (11U)

#define	SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos)

#define	SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk

#define	SPI_I2SPR_I2SDIV_Pos (0U)

#define	SPI_I2SPR_I2SDIV_Msk (0xFFUL << SPI_I2SPR_I2SDIV_Pos)

#define	SPI_I2SPR_I2SDIV SPI_I2SPR_I2SDIV_Msk

#define	SPI_I2SPR_ODD_Pos (8U)

#define	SPI_I2SPR_ODD_Msk (0x1UL << SPI_I2SPR_ODD_Pos)

#define	SPI_I2SPR_ODD SPI_I2SPR_ODD_Msk

#define	SPI_I2SPR_MCKOE_Pos (9U)

#define	SPI_I2SPR_MCKOE_Msk (0x1UL << SPI_I2SPR_MCKOE_Pos)

#define	SPI_I2SPR_MCKOE SPI_I2SPR_MCKOE_Msk

#define	I2C_CR1_PE_Pos (0U)

#define	I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos)

#define	I2C_CR1_PE I2C_CR1_PE_Msk

#define	I2C_CR1_SMBUS_Pos (1U)

#define	I2C_CR1_SMBUS_Msk (0x1UL << I2C_CR1_SMBUS_Pos)

#define	I2C_CR1_SMBUS I2C_CR1_SMBUS_Msk

#define	I2C_CR1_SMBTYPE_Pos (3U)

#define	I2C_CR1_SMBTYPE_Msk (0x1UL << I2C_CR1_SMBTYPE_Pos)

#define	I2C_CR1_SMBTYPE I2C_CR1_SMBTYPE_Msk

#define	I2C_CR1_ENARP_Pos (4U)

#define	I2C_CR1_ENARP_Msk (0x1UL << I2C_CR1_ENARP_Pos)

#define	I2C_CR1_ENARP I2C_CR1_ENARP_Msk

#define	I2C_CR1_ENPEC_Pos (5U)

#define	I2C_CR1_ENPEC_Msk (0x1UL << I2C_CR1_ENPEC_Pos)

#define	I2C_CR1_ENPEC I2C_CR1_ENPEC_Msk

#define	I2C_CR1_ENGC_Pos (6U)

#define	I2C_CR1_ENGC_Msk (0x1UL << I2C_CR1_ENGC_Pos)

#define	I2C_CR1_ENGC I2C_CR1_ENGC_Msk

#define	I2C_CR1_NOSTRETCH_Pos (7U)

#define	I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos)

#define	I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk

#define	I2C_CR1_START_Pos (8U)

#define	I2C_CR1_START_Msk (0x1UL << I2C_CR1_START_Pos)

#define	I2C_CR1_START I2C_CR1_START_Msk

#define	I2C_CR1_STOP_Pos (9U)

#define	I2C_CR1_STOP_Msk (0x1UL << I2C_CR1_STOP_Pos)

#define	I2C_CR1_STOP I2C_CR1_STOP_Msk

#define	I2C_CR1_ACK_Pos (10U)

#define	I2C_CR1_ACK_Msk (0x1UL << I2C_CR1_ACK_Pos)

#define	I2C_CR1_ACK I2C_CR1_ACK_Msk

#define	I2C_CR1_POS_Pos (11U)

#define	I2C_CR1_POS_Msk (0x1UL << I2C_CR1_POS_Pos)

#define	I2C_CR1_POS I2C_CR1_POS_Msk

#define	I2C_CR1_PEC_Pos (12U)

#define	I2C_CR1_PEC_Msk (0x1UL << I2C_CR1_PEC_Pos)

#define	I2C_CR1_PEC I2C_CR1_PEC_Msk

#define	I2C_CR1_ALERT_Pos (13U)

#define	I2C_CR1_ALERT_Msk (0x1UL << I2C_CR1_ALERT_Pos)

#define	I2C_CR1_ALERT I2C_CR1_ALERT_Msk

#define	I2C_CR1_SWRST_Pos (15U)

#define	I2C_CR1_SWRST_Msk (0x1UL << I2C_CR1_SWRST_Pos)

#define	I2C_CR1_SWRST I2C_CR1_SWRST_Msk

#define	I2C_CR2_FREQ_Pos (0U)

#define	I2C_CR2_FREQ_Msk (0x3FUL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_FREQ I2C_CR2_FREQ_Msk

#define	I2C_CR2_FREQ_0 (0x01UL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_FREQ_1 (0x02UL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_FREQ_2 (0x04UL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_FREQ_3 (0x08UL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_FREQ_4 (0x10UL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_FREQ_5 (0x20UL << I2C_CR2_FREQ_Pos)

#define	I2C_CR2_ITERREN_Pos (8U)

#define	I2C_CR2_ITERREN_Msk (0x1UL << I2C_CR2_ITERREN_Pos)

#define	I2C_CR2_ITERREN I2C_CR2_ITERREN_Msk

#define	I2C_CR2_ITEVTEN_Pos (9U)

#define	I2C_CR2_ITEVTEN_Msk (0x1UL << I2C_CR2_ITEVTEN_Pos)

#define	I2C_CR2_ITEVTEN I2C_CR2_ITEVTEN_Msk

#define	I2C_CR2_ITBUFEN_Pos (10U)

#define	I2C_CR2_ITBUFEN_Msk (0x1UL << I2C_CR2_ITBUFEN_Pos)

#define	I2C_CR2_ITBUFEN I2C_CR2_ITBUFEN_Msk

#define	I2C_CR2_DMAEN_Pos (11U)

#define	I2C_CR2_DMAEN_Msk (0x1UL << I2C_CR2_DMAEN_Pos)

#define	I2C_CR2_DMAEN I2C_CR2_DMAEN_Msk

#define	I2C_CR2_LAST_Pos (12U)

#define	I2C_CR2_LAST_Msk (0x1UL << I2C_CR2_LAST_Pos)

#define	I2C_CR2_LAST I2C_CR2_LAST_Msk

#define	I2C_OAR1_ADD1_7 0x000000FEU

#define	I2C_OAR1_ADD8_9 0x00000300U

#define	I2C_OAR1_ADD0_Pos (0U)

#define	I2C_OAR1_ADD0_Msk (0x1UL << I2C_OAR1_ADD0_Pos)

#define	I2C_OAR1_ADD0 I2C_OAR1_ADD0_Msk

#define	I2C_OAR1_ADD1_Pos (1U)

#define	I2C_OAR1_ADD1_Msk (0x1UL << I2C_OAR1_ADD1_Pos)

#define	I2C_OAR1_ADD1 I2C_OAR1_ADD1_Msk

#define	I2C_OAR1_ADD2_Pos (2U)

#define	I2C_OAR1_ADD2_Msk (0x1UL << I2C_OAR1_ADD2_Pos)

#define	I2C_OAR1_ADD2 I2C_OAR1_ADD2_Msk

#define	I2C_OAR1_ADD3_Pos (3U)

#define	I2C_OAR1_ADD3_Msk (0x1UL << I2C_OAR1_ADD3_Pos)

#define	I2C_OAR1_ADD3 I2C_OAR1_ADD3_Msk

#define	I2C_OAR1_ADD4_Pos (4U)

#define	I2C_OAR1_ADD4_Msk (0x1UL << I2C_OAR1_ADD4_Pos)

#define	I2C_OAR1_ADD4 I2C_OAR1_ADD4_Msk

#define	I2C_OAR1_ADD5_Pos (5U)

#define	I2C_OAR1_ADD5_Msk (0x1UL << I2C_OAR1_ADD5_Pos)

#define	I2C_OAR1_ADD5 I2C_OAR1_ADD5_Msk

#define	I2C_OAR1_ADD6_Pos (6U)

#define	I2C_OAR1_ADD6_Msk (0x1UL << I2C_OAR1_ADD6_Pos)

#define	I2C_OAR1_ADD6 I2C_OAR1_ADD6_Msk

#define	I2C_OAR1_ADD7_Pos (7U)

#define	I2C_OAR1_ADD7_Msk (0x1UL << I2C_OAR1_ADD7_Pos)

#define	I2C_OAR1_ADD7 I2C_OAR1_ADD7_Msk

#define	I2C_OAR1_ADD8_Pos (8U)

#define	I2C_OAR1_ADD8_Msk (0x1UL << I2C_OAR1_ADD8_Pos)

#define	I2C_OAR1_ADD8 I2C_OAR1_ADD8_Msk

#define	I2C_OAR1_ADD9_Pos (9U)

#define	I2C_OAR1_ADD9_Msk (0x1UL << I2C_OAR1_ADD9_Pos)

#define	I2C_OAR1_ADD9 I2C_OAR1_ADD9_Msk

#define	I2C_OAR1_ADDMODE_Pos (15U)

#define	I2C_OAR1_ADDMODE_Msk (0x1UL << I2C_OAR1_ADDMODE_Pos)

#define	I2C_OAR1_ADDMODE I2C_OAR1_ADDMODE_Msk

#define	I2C_OAR2_ENDUAL_Pos (0U)

#define	I2C_OAR2_ENDUAL_Msk (0x1UL << I2C_OAR2_ENDUAL_Pos)

#define	I2C_OAR2_ENDUAL I2C_OAR2_ENDUAL_Msk

#define	I2C_OAR2_ADD2_Pos (1U)

#define	I2C_OAR2_ADD2_Msk (0x7FUL << I2C_OAR2_ADD2_Pos)

#define	I2C_OAR2_ADD2 I2C_OAR2_ADD2_Msk

#define	I2C_DR_DR_Pos (0U)

#define	I2C_DR_DR_Msk (0xFFUL << I2C_DR_DR_Pos)

#define	I2C_DR_DR I2C_DR_DR_Msk

#define	I2C_SR1_SB_Pos (0U)

#define	I2C_SR1_SB_Msk (0x1UL << I2C_SR1_SB_Pos)

#define	I2C_SR1_SB I2C_SR1_SB_Msk

#define	I2C_SR1_ADDR_Pos (1U)

#define	I2C_SR1_ADDR_Msk (0x1UL << I2C_SR1_ADDR_Pos)

#define	I2C_SR1_ADDR I2C_SR1_ADDR_Msk

#define	I2C_SR1_BTF_Pos (2U)

#define	I2C_SR1_BTF_Msk (0x1UL << I2C_SR1_BTF_Pos)

#define	I2C_SR1_BTF I2C_SR1_BTF_Msk

#define	I2C_SR1_ADD10_Pos (3U)

#define	I2C_SR1_ADD10_Msk (0x1UL << I2C_SR1_ADD10_Pos)

#define	I2C_SR1_ADD10 I2C_SR1_ADD10_Msk

#define	I2C_SR1_STOPF_Pos (4U)

#define	I2C_SR1_STOPF_Msk (0x1UL << I2C_SR1_STOPF_Pos)

#define	I2C_SR1_STOPF I2C_SR1_STOPF_Msk

#define	I2C_SR1_RXNE_Pos (6U)

#define	I2C_SR1_RXNE_Msk (0x1UL << I2C_SR1_RXNE_Pos)

#define	I2C_SR1_RXNE I2C_SR1_RXNE_Msk

#define	I2C_SR1_TXE_Pos (7U)

#define	I2C_SR1_TXE_Msk (0x1UL << I2C_SR1_TXE_Pos)

#define	I2C_SR1_TXE I2C_SR1_TXE_Msk

#define	I2C_SR1_BERR_Pos (8U)

#define	I2C_SR1_BERR_Msk (0x1UL << I2C_SR1_BERR_Pos)

#define	I2C_SR1_BERR I2C_SR1_BERR_Msk

#define	I2C_SR1_ARLO_Pos (9U)

#define	I2C_SR1_ARLO_Msk (0x1UL << I2C_SR1_ARLO_Pos)

#define	I2C_SR1_ARLO I2C_SR1_ARLO_Msk

#define	I2C_SR1_AF_Pos (10U)

#define	I2C_SR1_AF_Msk (0x1UL << I2C_SR1_AF_Pos)

#define	I2C_SR1_AF I2C_SR1_AF_Msk

#define	I2C_SR1_OVR_Pos (11U)

#define	I2C_SR1_OVR_Msk (0x1UL << I2C_SR1_OVR_Pos)

#define	I2C_SR1_OVR I2C_SR1_OVR_Msk

#define	I2C_SR1_PECERR_Pos (12U)

#define	I2C_SR1_PECERR_Msk (0x1UL << I2C_SR1_PECERR_Pos)

#define	I2C_SR1_PECERR I2C_SR1_PECERR_Msk

#define	I2C_SR1_TIMEOUT_Pos (14U)

#define	I2C_SR1_TIMEOUT_Msk (0x1UL << I2C_SR1_TIMEOUT_Pos)

#define	I2C_SR1_TIMEOUT I2C_SR1_TIMEOUT_Msk

#define	I2C_SR1_SMBALERT_Pos (15U)

#define	I2C_SR1_SMBALERT_Msk (0x1UL << I2C_SR1_SMBALERT_Pos)

#define	I2C_SR1_SMBALERT I2C_SR1_SMBALERT_Msk

#define	I2C_SR2_MSL_Pos (0U)

#define	I2C_SR2_MSL_Msk (0x1UL << I2C_SR2_MSL_Pos)

#define	I2C_SR2_MSL I2C_SR2_MSL_Msk

#define	I2C_SR2_BUSY_Pos (1U)

#define	I2C_SR2_BUSY_Msk (0x1UL << I2C_SR2_BUSY_Pos)

#define	I2C_SR2_BUSY I2C_SR2_BUSY_Msk

#define	I2C_SR2_TRA_Pos (2U)

#define	I2C_SR2_TRA_Msk (0x1UL << I2C_SR2_TRA_Pos)

#define	I2C_SR2_TRA I2C_SR2_TRA_Msk

#define	I2C_SR2_GENCALL_Pos (4U)

#define	I2C_SR2_GENCALL_Msk (0x1UL << I2C_SR2_GENCALL_Pos)

#define	I2C_SR2_GENCALL I2C_SR2_GENCALL_Msk

#define	I2C_SR2_SMBDEFAULT_Pos (5U)

#define	I2C_SR2_SMBDEFAULT_Msk (0x1UL << I2C_SR2_SMBDEFAULT_Pos)

#define	I2C_SR2_SMBDEFAULT I2C_SR2_SMBDEFAULT_Msk

#define	I2C_SR2_SMBHOST_Pos (6U)

#define	I2C_SR2_SMBHOST_Msk (0x1UL << I2C_SR2_SMBHOST_Pos)

#define	I2C_SR2_SMBHOST I2C_SR2_SMBHOST_Msk

#define	I2C_SR2_DUALF_Pos (7U)

#define	I2C_SR2_DUALF_Msk (0x1UL << I2C_SR2_DUALF_Pos)

#define	I2C_SR2_DUALF I2C_SR2_DUALF_Msk

#define	I2C_SR2_PEC_Pos (8U)

#define	I2C_SR2_PEC_Msk (0xFFUL << I2C_SR2_PEC_Pos)

#define	I2C_SR2_PEC I2C_SR2_PEC_Msk

#define	I2C_CCR_CCR_Pos (0U)

#define	I2C_CCR_CCR_Msk (0xFFFUL << I2C_CCR_CCR_Pos)

#define	I2C_CCR_CCR I2C_CCR_CCR_Msk

#define	I2C_CCR_DUTY_Pos (14U)

#define	I2C_CCR_DUTY_Msk (0x1UL << I2C_CCR_DUTY_Pos)

#define	I2C_CCR_DUTY I2C_CCR_DUTY_Msk

#define	I2C_CCR_FS_Pos (15U)

#define	I2C_CCR_FS_Msk (0x1UL << I2C_CCR_FS_Pos)

#define	I2C_CCR_FS I2C_CCR_FS_Msk

#define	I2C_TRISE_TRISE_Pos (0U)

#define	I2C_TRISE_TRISE_Msk (0x3FUL << I2C_TRISE_TRISE_Pos)

#define	I2C_TRISE_TRISE I2C_TRISE_TRISE_Msk

#define	USART_SR_PE_Pos (0U)

#define	USART_SR_PE_Msk (0x1UL << USART_SR_PE_Pos)

#define	USART_SR_PE USART_SR_PE_Msk

#define	USART_SR_FE_Pos (1U)

#define	USART_SR_FE_Msk (0x1UL << USART_SR_FE_Pos)

#define	USART_SR_FE USART_SR_FE_Msk

#define	USART_SR_NE_Pos (2U)

#define	USART_SR_NE_Msk (0x1UL << USART_SR_NE_Pos)

#define	USART_SR_NE USART_SR_NE_Msk

#define	USART_SR_ORE_Pos (3U)

#define	USART_SR_ORE_Msk (0x1UL << USART_SR_ORE_Pos)

#define	USART_SR_ORE USART_SR_ORE_Msk

#define	USART_SR_IDLE_Pos (4U)

#define	USART_SR_IDLE_Msk (0x1UL << USART_SR_IDLE_Pos)

#define	USART_SR_IDLE USART_SR_IDLE_Msk

#define	USART_SR_RXNE_Pos (5U)

#define	USART_SR_RXNE_Msk (0x1UL << USART_SR_RXNE_Pos)

#define	USART_SR_RXNE USART_SR_RXNE_Msk

#define	USART_SR_TC_Pos (6U)

#define	USART_SR_TC_Msk (0x1UL << USART_SR_TC_Pos)

#define	USART_SR_TC USART_SR_TC_Msk

#define	USART_SR_TXE_Pos (7U)

#define	USART_SR_TXE_Msk (0x1UL << USART_SR_TXE_Pos)

#define	USART_SR_TXE USART_SR_TXE_Msk

#define	USART_SR_LBD_Pos (8U)

#define	USART_SR_LBD_Msk (0x1UL << USART_SR_LBD_Pos)

#define	USART_SR_LBD USART_SR_LBD_Msk

#define	USART_SR_CTS_Pos (9U)

#define	USART_SR_CTS_Msk (0x1UL << USART_SR_CTS_Pos)

#define	USART_SR_CTS USART_SR_CTS_Msk

#define	USART_DR_DR_Pos (0U)

#define	USART_DR_DR_Msk (0x1FFUL << USART_DR_DR_Pos)

#define	USART_DR_DR USART_DR_DR_Msk

#define	USART_BRR_DIV_Fraction_Pos (0U)

#define	USART_BRR_DIV_Fraction_Msk (0xFUL << USART_BRR_DIV_Fraction_Pos)

#define	USART_BRR_DIV_Fraction USART_BRR_DIV_Fraction_Msk

#define	USART_BRR_DIV_Mantissa_Pos (4U)

#define	USART_BRR_DIV_Mantissa_Msk (0xFFFUL << USART_BRR_DIV_Mantissa_Pos)

#define	USART_BRR_DIV_Mantissa USART_BRR_DIV_Mantissa_Msk

#define	USART_CR1_SBK_Pos (0U)

#define	USART_CR1_SBK_Msk (0x1UL << USART_CR1_SBK_Pos)

#define	USART_CR1_SBK USART_CR1_SBK_Msk

#define	USART_CR1_RWU_Pos (1U)

#define	USART_CR1_RWU_Msk (0x1UL << USART_CR1_RWU_Pos)

#define	USART_CR1_RWU USART_CR1_RWU_Msk

#define	USART_CR1_RE_Pos (2U)

#define	USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos)

#define	USART_CR1_RE USART_CR1_RE_Msk

#define	USART_CR1_TE_Pos (3U)

#define	USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos)

#define	USART_CR1_TE USART_CR1_TE_Msk

#define	USART_CR1_IDLEIE_Pos (4U)

#define	USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos)

#define	USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk

#define	USART_CR1_RXNEIE_Pos (5U)

#define	USART_CR1_RXNEIE_Msk (0x1UL << USART_CR1_RXNEIE_Pos)

#define	USART_CR1_RXNEIE USART_CR1_RXNEIE_Msk

#define	USART_CR1_TCIE_Pos (6U)

#define	USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos)

#define	USART_CR1_TCIE USART_CR1_TCIE_Msk

#define	USART_CR1_TXEIE_Pos (7U)

#define	USART_CR1_TXEIE_Msk (0x1UL << USART_CR1_TXEIE_Pos)

#define	USART_CR1_TXEIE USART_CR1_TXEIE_Msk

#define	USART_CR1_PEIE_Pos (8U)

#define	USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos)

#define	USART_CR1_PEIE USART_CR1_PEIE_Msk

#define	USART_CR1_PS_Pos (9U)

#define	USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos)

#define	USART_CR1_PS USART_CR1_PS_Msk

#define	USART_CR1_PCE_Pos (10U)

#define	USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos)

#define	USART_CR1_PCE USART_CR1_PCE_Msk

#define	USART_CR1_WAKE_Pos (11U)

#define	USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos)

#define	USART_CR1_WAKE USART_CR1_WAKE_Msk

#define	USART_CR1_M_Pos (12U)

#define	USART_CR1_M_Msk (0x1UL << USART_CR1_M_Pos)

#define	USART_CR1_M USART_CR1_M_Msk

#define	USART_CR1_UE_Pos (13U)

#define	USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos)

#define	USART_CR1_UE USART_CR1_UE_Msk

#define	USART_CR2_ADD_Pos (0U)

#define	USART_CR2_ADD_Msk (0xFUL << USART_CR2_ADD_Pos)

#define	USART_CR2_ADD USART_CR2_ADD_Msk

#define	USART_CR2_LBDL_Pos (5U)

#define	USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos)

#define	USART_CR2_LBDL USART_CR2_LBDL_Msk

#define	USART_CR2_LBDIE_Pos (6U)

#define	USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos)

#define	USART_CR2_LBDIE USART_CR2_LBDIE_Msk

#define	USART_CR2_LBCL_Pos (8U)

#define	USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos)

#define	USART_CR2_LBCL USART_CR2_LBCL_Msk

#define	USART_CR2_CPHA_Pos (9U)

#define	USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos)

#define	USART_CR2_CPHA USART_CR2_CPHA_Msk

#define	USART_CR2_CPOL_Pos (10U)

#define	USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos)

#define	USART_CR2_CPOL USART_CR2_CPOL_Msk

#define	USART_CR2_CLKEN_Pos (11U)

#define	USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos)

#define	USART_CR2_CLKEN USART_CR2_CLKEN_Msk

#define	USART_CR2_STOP_Pos (12U)

#define	USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP USART_CR2_STOP_Msk

#define	USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos)

#define	USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos)

#define	USART_CR2_LINEN_Pos (14U)

#define	USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos)

#define	USART_CR2_LINEN USART_CR2_LINEN_Msk

#define	USART_CR3_EIE_Pos (0U)

#define	USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos)

#define	USART_CR3_EIE USART_CR3_EIE_Msk

#define	USART_CR3_IREN_Pos (1U)

#define	USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos)

#define	USART_CR3_IREN USART_CR3_IREN_Msk

#define	USART_CR3_IRLP_Pos (2U)

#define	USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos)

#define	USART_CR3_IRLP USART_CR3_IRLP_Msk

#define	USART_CR3_HDSEL_Pos (3U)

#define	USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos)

#define	USART_CR3_HDSEL USART_CR3_HDSEL_Msk

#define	USART_CR3_NACK_Pos (4U)

#define	USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos)

#define	USART_CR3_NACK USART_CR3_NACK_Msk

#define	USART_CR3_SCEN_Pos (5U)

#define	USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos)

#define	USART_CR3_SCEN USART_CR3_SCEN_Msk

#define	USART_CR3_DMAR_Pos (6U)

#define	USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos)

#define	USART_CR3_DMAR USART_CR3_DMAR_Msk

#define	USART_CR3_DMAT_Pos (7U)

#define	USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos)

#define	USART_CR3_DMAT USART_CR3_DMAT_Msk

#define	USART_CR3_RTSE_Pos (8U)

#define	USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos)

#define	USART_CR3_RTSE USART_CR3_RTSE_Msk

#define	USART_CR3_CTSE_Pos (9U)

#define	USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos)

#define	USART_CR3_CTSE USART_CR3_CTSE_Msk

#define	USART_CR3_CTSIE_Pos (10U)

#define	USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos)

#define	USART_CR3_CTSIE USART_CR3_CTSIE_Msk

#define	USART_GTPR_PSC_Pos (0U)

#define	USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC USART_GTPR_PSC_Msk

#define	USART_GTPR_PSC_0 (0x01UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_1 (0x02UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_2 (0x04UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_3 (0x08UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_4 (0x10UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_5 (0x20UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_6 (0x40UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_PSC_7 (0x80UL << USART_GTPR_PSC_Pos)

#define	USART_GTPR_GT_Pos (8U)

#define	USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos)

#define	USART_GTPR_GT USART_GTPR_GT_Msk

#define	DBGMCU_IDCODE_DEV_ID_Pos (0U)

#define	DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos)

#define	DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk

#define	DBGMCU_IDCODE_REV_ID_Pos (16U)

#define	DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk

#define	DBGMCU_IDCODE_REV_ID_0 (0x0001UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_1 (0x0002UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_2 (0x0004UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_3 (0x0008UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_4 (0x0010UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_5 (0x0020UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_6 (0x0040UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_7 (0x0080UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_8 (0x0100UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_9 (0x0200UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_10 (0x0400UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_11 (0x0800UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_12 (0x1000UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_13 (0x2000UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_14 (0x4000UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_IDCODE_REV_ID_15 (0x8000UL << DBGMCU_IDCODE_REV_ID_Pos)

#define	DBGMCU_CR_DBG_SLEEP_Pos (0U)

#define	DBGMCU_CR_DBG_SLEEP_Msk (0x1UL << DBGMCU_CR_DBG_SLEEP_Pos)

#define	DBGMCU_CR_DBG_SLEEP DBGMCU_CR_DBG_SLEEP_Msk

#define	DBGMCU_CR_DBG_STOP_Pos (1U)

#define	DBGMCU_CR_DBG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_STOP_Pos)

#define	DBGMCU_CR_DBG_STOP DBGMCU_CR_DBG_STOP_Msk

#define	DBGMCU_CR_DBG_STANDBY_Pos (2U)

#define	DBGMCU_CR_DBG_STANDBY_Msk (0x1UL << DBGMCU_CR_DBG_STANDBY_Pos)

#define	DBGMCU_CR_DBG_STANDBY DBGMCU_CR_DBG_STANDBY_Msk

#define	DBGMCU_CR_TRACE_IOEN_Pos (5U)

#define	DBGMCU_CR_TRACE_IOEN_Msk (0x1UL << DBGMCU_CR_TRACE_IOEN_Pos)

#define	DBGMCU_CR_TRACE_IOEN DBGMCU_CR_TRACE_IOEN_Msk

#define	DBGMCU_CR_TRACE_MODE_Pos (6U)

#define	DBGMCU_CR_TRACE_MODE_Msk (0x3UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE DBGMCU_CR_TRACE_MODE_Msk

#define	DBGMCU_CR_TRACE_MODE_0 (0x1UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_TRACE_MODE_1 (0x2UL << DBGMCU_CR_TRACE_MODE_Pos)

#define	DBGMCU_CR_DBG_IWDG_STOP_Pos (8U)

#define	DBGMCU_CR_DBG_IWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_IWDG_STOP_Pos)

#define	DBGMCU_CR_DBG_IWDG_STOP DBGMCU_CR_DBG_IWDG_STOP_Msk

#define	DBGMCU_CR_DBG_WWDG_STOP_Pos (9U)

#define	DBGMCU_CR_DBG_WWDG_STOP_Msk (0x1UL << DBGMCU_CR_DBG_WWDG_STOP_Pos)

#define	DBGMCU_CR_DBG_WWDG_STOP DBGMCU_CR_DBG_WWDG_STOP_Msk

#define	DBGMCU_CR_DBG_TIM1_STOP_Pos (10U)

#define	DBGMCU_CR_DBG_TIM1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM1_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM1_STOP DBGMCU_CR_DBG_TIM1_STOP_Msk

#define	DBGMCU_CR_DBG_TIM2_STOP_Pos (11U)

#define	DBGMCU_CR_DBG_TIM2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM2_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM2_STOP DBGMCU_CR_DBG_TIM2_STOP_Msk

#define	DBGMCU_CR_DBG_TIM3_STOP_Pos (12U)

#define	DBGMCU_CR_DBG_TIM3_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM3_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM3_STOP DBGMCU_CR_DBG_TIM3_STOP_Msk

#define	DBGMCU_CR_DBG_TIM4_STOP_Pos (13U)

#define	DBGMCU_CR_DBG_TIM4_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM4_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM4_STOP DBGMCU_CR_DBG_TIM4_STOP_Msk

#define	DBGMCU_CR_DBG_CAN1_STOP_Pos (14U)

#define	DBGMCU_CR_DBG_CAN1_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN1_STOP_Pos)

#define	DBGMCU_CR_DBG_CAN1_STOP DBGMCU_CR_DBG_CAN1_STOP_Msk

#define	DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos (15U)

#define	DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Pos)

#define	DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C1_SMBUS_TIMEOUT_Msk

#define	DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos (16U)

#define	DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk (0x1UL << DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Pos)

#define	DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT DBGMCU_CR_DBG_I2C2_SMBUS_TIMEOUT_Msk

#define	DBGMCU_CR_DBG_TIM5_STOP_Pos (18U)

#define	DBGMCU_CR_DBG_TIM5_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM5_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM5_STOP DBGMCU_CR_DBG_TIM5_STOP_Msk

#define	DBGMCU_CR_DBG_TIM6_STOP_Pos (19U)

#define	DBGMCU_CR_DBG_TIM6_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM6_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM6_STOP DBGMCU_CR_DBG_TIM6_STOP_Msk

#define	DBGMCU_CR_DBG_TIM7_STOP_Pos (20U)

#define	DBGMCU_CR_DBG_TIM7_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM7_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM7_STOP DBGMCU_CR_DBG_TIM7_STOP_Msk

#define	DBGMCU_CR_DBG_CAN2_STOP_Pos (21U)

#define	DBGMCU_CR_DBG_CAN2_STOP_Msk (0x1UL << DBGMCU_CR_DBG_CAN2_STOP_Pos)

#define	DBGMCU_CR_DBG_CAN2_STOP DBGMCU_CR_DBG_CAN2_STOP_Msk

#define	DBGMCU_CR_DBG_TIM9_STOP_Pos (28U)

#define	DBGMCU_CR_DBG_TIM9_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM9_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM9_STOP DBGMCU_CR_DBG_TIM9_STOP_Msk

#define	DBGMCU_CR_DBG_TIM10_STOP_Pos (29U)

#define	DBGMCU_CR_DBG_TIM10_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM10_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM10_STOP DBGMCU_CR_DBG_TIM10_STOP_Msk

#define	DBGMCU_CR_DBG_TIM11_STOP_Pos (30U)

#define	DBGMCU_CR_DBG_TIM11_STOP_Msk (0x1UL << DBGMCU_CR_DBG_TIM11_STOP_Pos)

#define	DBGMCU_CR_DBG_TIM11_STOP DBGMCU_CR_DBG_TIM11_STOP_Msk

#define	FLASH_ACR_LATENCY_Pos (0U)

#define	FLASH_ACR_LATENCY_Msk (0x7UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk

#define	FLASH_ACR_LATENCY_0 (0x1UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_1 (0x2UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_LATENCY_2 (0x4UL << FLASH_ACR_LATENCY_Pos)

#define	FLASH_ACR_HLFCYA_Pos (3U)

#define	FLASH_ACR_HLFCYA_Msk (0x1UL << FLASH_ACR_HLFCYA_Pos)

#define	FLASH_ACR_HLFCYA FLASH_ACR_HLFCYA_Msk

#define	FLASH_ACR_PRFTBE_Pos (4U)

#define	FLASH_ACR_PRFTBE_Msk (0x1UL << FLASH_ACR_PRFTBE_Pos)

#define	FLASH_ACR_PRFTBE FLASH_ACR_PRFTBE_Msk

#define	FLASH_ACR_PRFTBS_Pos (5U)

#define	FLASH_ACR_PRFTBS_Msk (0x1UL << FLASH_ACR_PRFTBS_Pos)

#define	FLASH_ACR_PRFTBS FLASH_ACR_PRFTBS_Msk

#define	FLASH_KEYR_FKEYR_Pos (0U)

#define	FLASH_KEYR_FKEYR_Msk (0xFFFFFFFFUL << FLASH_KEYR_FKEYR_Pos)

#define	FLASH_KEYR_FKEYR FLASH_KEYR_FKEYR_Msk

#define	RDP_KEY_Pos (0U)

#define	RDP_KEY_Msk (0xA5UL << RDP_KEY_Pos)

#define	RDP_KEY RDP_KEY_Msk

#define	FLASH_KEY1_Pos (0U)

#define	FLASH_KEY1_Msk (0x45670123UL << FLASH_KEY1_Pos)

#define	FLASH_KEY1 FLASH_KEY1_Msk

#define	FLASH_KEY2_Pos (0U)

#define	FLASH_KEY2_Msk (0xCDEF89ABUL << FLASH_KEY2_Pos)

#define	FLASH_KEY2 FLASH_KEY2_Msk

#define	FLASH_OPTKEYR_OPTKEYR_Pos (0U)

#define	FLASH_OPTKEYR_OPTKEYR_Msk (0xFFFFFFFFUL << FLASH_OPTKEYR_OPTKEYR_Pos)

#define	FLASH_OPTKEYR_OPTKEYR FLASH_OPTKEYR_OPTKEYR_Msk

#define	FLASH_OPTKEY1 FLASH_KEY1

#define	FLASH_OPTKEY2 FLASH_KEY2

#define	FLASH_SR_BSY_Pos (0U)

#define	FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos)

#define	FLASH_SR_BSY FLASH_SR_BSY_Msk

#define	FLASH_SR_PGERR_Pos (2U)

#define	FLASH_SR_PGERR_Msk (0x1UL << FLASH_SR_PGERR_Pos)

#define	FLASH_SR_PGERR FLASH_SR_PGERR_Msk

#define	FLASH_SR_WRPRTERR_Pos (4U)

#define	FLASH_SR_WRPRTERR_Msk (0x1UL << FLASH_SR_WRPRTERR_Pos)

#define	FLASH_SR_WRPRTERR FLASH_SR_WRPRTERR_Msk

#define	FLASH_SR_EOP_Pos (5U)

#define	FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos)

#define	FLASH_SR_EOP FLASH_SR_EOP_Msk

#define	FLASH_CR_PG_Pos (0U)

#define	FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos)

#define	FLASH_CR_PG FLASH_CR_PG_Msk

#define	FLASH_CR_PER_Pos (1U)

#define	FLASH_CR_PER_Msk (0x1UL << FLASH_CR_PER_Pos)

#define	FLASH_CR_PER FLASH_CR_PER_Msk

#define	FLASH_CR_MER_Pos (2U)

#define	FLASH_CR_MER_Msk (0x1UL << FLASH_CR_MER_Pos)

#define	FLASH_CR_MER FLASH_CR_MER_Msk

#define	FLASH_CR_OPTPG_Pos (4U)

#define	FLASH_CR_OPTPG_Msk (0x1UL << FLASH_CR_OPTPG_Pos)

#define	FLASH_CR_OPTPG FLASH_CR_OPTPG_Msk

#define	FLASH_CR_OPTER_Pos (5U)

#define	FLASH_CR_OPTER_Msk (0x1UL << FLASH_CR_OPTER_Pos)

#define	FLASH_CR_OPTER FLASH_CR_OPTER_Msk

#define	FLASH_CR_STRT_Pos (6U)

#define	FLASH_CR_STRT_Msk (0x1UL << FLASH_CR_STRT_Pos)

#define	FLASH_CR_STRT FLASH_CR_STRT_Msk

#define	FLASH_CR_LOCK_Pos (7U)

#define	FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos)

#define	FLASH_CR_LOCK FLASH_CR_LOCK_Msk

#define	FLASH_CR_OPTWRE_Pos (9U)

#define	FLASH_CR_OPTWRE_Msk (0x1UL << FLASH_CR_OPTWRE_Pos)

#define	FLASH_CR_OPTWRE FLASH_CR_OPTWRE_Msk

#define	FLASH_CR_ERRIE_Pos (10U)

#define	FLASH_CR_ERRIE_Msk (0x1UL << FLASH_CR_ERRIE_Pos)

#define	FLASH_CR_ERRIE FLASH_CR_ERRIE_Msk

#define	FLASH_CR_EOPIE_Pos (12U)

#define	FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos)

#define	FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk

#define	FLASH_AR_FAR_Pos (0U)

#define	FLASH_AR_FAR_Msk (0xFFFFFFFFUL << FLASH_AR_FAR_Pos)

#define	FLASH_AR_FAR FLASH_AR_FAR_Msk

#define	FLASH_OBR_OPTERR_Pos (0U)

#define	FLASH_OBR_OPTERR_Msk (0x1UL << FLASH_OBR_OPTERR_Pos)

#define	FLASH_OBR_OPTERR FLASH_OBR_OPTERR_Msk

#define	FLASH_OBR_RDPRT_Pos (1U)

#define	FLASH_OBR_RDPRT_Msk (0x1UL << FLASH_OBR_RDPRT_Pos)

#define	FLASH_OBR_RDPRT FLASH_OBR_RDPRT_Msk

#define	FLASH_OBR_IWDG_SW_Pos (2U)

#define	FLASH_OBR_IWDG_SW_Msk (0x1UL << FLASH_OBR_IWDG_SW_Pos)

#define	FLASH_OBR_IWDG_SW FLASH_OBR_IWDG_SW_Msk

#define	FLASH_OBR_nRST_STOP_Pos (3U)

#define	FLASH_OBR_nRST_STOP_Msk (0x1UL << FLASH_OBR_nRST_STOP_Pos)

#define	FLASH_OBR_nRST_STOP FLASH_OBR_nRST_STOP_Msk

#define	FLASH_OBR_nRST_STDBY_Pos (4U)

#define	FLASH_OBR_nRST_STDBY_Msk (0x1UL << FLASH_OBR_nRST_STDBY_Pos)

#define	FLASH_OBR_nRST_STDBY FLASH_OBR_nRST_STDBY_Msk

#define	FLASH_OBR_USER_Pos (2U)

#define	FLASH_OBR_USER_Msk (0x7UL << FLASH_OBR_USER_Pos)

#define	FLASH_OBR_USER FLASH_OBR_USER_Msk

#define	FLASH_OBR_DATA0_Pos (10U)

#define	FLASH_OBR_DATA0_Msk (0xFFUL << FLASH_OBR_DATA0_Pos)

#define	FLASH_OBR_DATA0 FLASH_OBR_DATA0_Msk

#define	FLASH_OBR_DATA1_Pos (18U)

#define	FLASH_OBR_DATA1_Msk (0xFFUL << FLASH_OBR_DATA1_Pos)

#define	FLASH_OBR_DATA1 FLASH_OBR_DATA1_Msk

#define	FLASH_WRPR_WRP_Pos (0U)

#define	FLASH_WRPR_WRP_Msk (0xFFFFFFFFUL << FLASH_WRPR_WRP_Pos)

#define	FLASH_WRPR_WRP FLASH_WRPR_WRP_Msk

#define	FLASH_RDP_RDP_Pos (0U)

#define	FLASH_RDP_RDP_Msk (0xFFUL << FLASH_RDP_RDP_Pos)

#define	FLASH_RDP_RDP FLASH_RDP_RDP_Msk

#define	FLASH_RDP_nRDP_Pos (8U)

#define	FLASH_RDP_nRDP_Msk (0xFFUL << FLASH_RDP_nRDP_Pos)

#define	FLASH_RDP_nRDP FLASH_RDP_nRDP_Msk

#define	FLASH_USER_USER_Pos (16U)

#define	FLASH_USER_USER_Msk (0xFFUL << FLASH_USER_USER_Pos)

#define	FLASH_USER_USER FLASH_USER_USER_Msk

#define	FLASH_USER_nUSER_Pos (24U)

#define	FLASH_USER_nUSER_Msk (0xFFUL << FLASH_USER_nUSER_Pos)

#define	FLASH_USER_nUSER FLASH_USER_nUSER_Msk

#define	FLASH_DATA0_DATA0_Pos (0U)

#define	FLASH_DATA0_DATA0_Msk (0xFFUL << FLASH_DATA0_DATA0_Pos)

#define	FLASH_DATA0_DATA0 FLASH_DATA0_DATA0_Msk

#define	FLASH_DATA0_nDATA0_Pos (8U)

#define	FLASH_DATA0_nDATA0_Msk (0xFFUL << FLASH_DATA0_nDATA0_Pos)

#define	FLASH_DATA0_nDATA0 FLASH_DATA0_nDATA0_Msk

#define	FLASH_DATA1_DATA1_Pos (16U)

#define	FLASH_DATA1_DATA1_Msk (0xFFUL << FLASH_DATA1_DATA1_Pos)

#define	FLASH_DATA1_DATA1 FLASH_DATA1_DATA1_Msk

#define	FLASH_DATA1_nDATA1_Pos (24U)

#define	FLASH_DATA1_nDATA1_Msk (0xFFUL << FLASH_DATA1_nDATA1_Pos)

#define	FLASH_DATA1_nDATA1 FLASH_DATA1_nDATA1_Msk

#define	FLASH_WRP0_WRP0_Pos (0U)

#define	FLASH_WRP0_WRP0_Msk (0xFFUL << FLASH_WRP0_WRP0_Pos)

#define	FLASH_WRP0_WRP0 FLASH_WRP0_WRP0_Msk

#define	FLASH_WRP0_nWRP0_Pos (8U)

#define	FLASH_WRP0_nWRP0_Msk (0xFFUL << FLASH_WRP0_nWRP0_Pos)

#define	FLASH_WRP0_nWRP0 FLASH_WRP0_nWRP0_Msk

#define	FLASH_WRP1_WRP1_Pos (16U)

#define	FLASH_WRP1_WRP1_Msk (0xFFUL << FLASH_WRP1_WRP1_Pos)

#define	FLASH_WRP1_WRP1 FLASH_WRP1_WRP1_Msk

#define	FLASH_WRP1_nWRP1_Pos (24U)

#define	FLASH_WRP1_nWRP1_Msk (0xFFUL << FLASH_WRP1_nWRP1_Pos)

#define	FLASH_WRP1_nWRP1 FLASH_WRP1_nWRP1_Msk

#define	FLASH_WRP2_WRP2_Pos (0U)

#define	FLASH_WRP2_WRP2_Msk (0xFFUL << FLASH_WRP2_WRP2_Pos)

#define	FLASH_WRP2_WRP2 FLASH_WRP2_WRP2_Msk

#define	FLASH_WRP2_nWRP2_Pos (8U)

#define	FLASH_WRP2_nWRP2_Msk (0xFFUL << FLASH_WRP2_nWRP2_Pos)

#define	FLASH_WRP2_nWRP2 FLASH_WRP2_nWRP2_Msk

#define	FLASH_WRP3_WRP3_Pos (16U)

#define	FLASH_WRP3_WRP3_Msk (0xFFUL << FLASH_WRP3_WRP3_Pos)

#define	FLASH_WRP3_WRP3 FLASH_WRP3_WRP3_Msk

#define	FLASH_WRP3_nWRP3_Pos (24U)

#define	FLASH_WRP3_nWRP3_Msk (0xFFUL << FLASH_WRP3_nWRP3_Pos)

#define	FLASH_WRP3_nWRP3 FLASH_WRP3_nWRP3_Msk

#define	ETH_MACCR_WD_Pos (23U)

#define	ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos)

#define	ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */

#define	ETH_MACCR_JD_Pos (22U)

#define	ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos)

#define	ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */

#define	ETH_MACCR_IFG_Pos (17U)

#define	ETH_MACCR_IFG_Msk (0x7UL << ETH_MACCR_IFG_Pos)

#define	ETH_MACCR_IFG ETH_MACCR_IFG_Msk /* Inter-frame gap */

#define	ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */

#define	ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */

#define	ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */

#define	ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */

#define	ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */

#define	ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */

#define	ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */

#define	ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */

#define	ETH_MACCR_CSD_Pos (16U)

#define	ETH_MACCR_CSD_Msk (0x1UL << ETH_MACCR_CSD_Pos)

#define	ETH_MACCR_CSD ETH_MACCR_CSD_Msk /* Carrier sense disable (during transmission) */

#define	ETH_MACCR_FES_Pos (14U)

#define	ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos)

#define	ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */

#define	ETH_MACCR_ROD_Pos (13U)

#define	ETH_MACCR_ROD_Msk (0x1UL << ETH_MACCR_ROD_Pos)

#define	ETH_MACCR_ROD ETH_MACCR_ROD_Msk /* Receive own disable */

#define	ETH_MACCR_LM_Pos (12U)

#define	ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos)

#define	ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */

#define	ETH_MACCR_DM_Pos (11U)

#define	ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos)

#define	ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */

#define	ETH_MACCR_IPCO_Pos (10U)

#define	ETH_MACCR_IPCO_Msk (0x1UL << ETH_MACCR_IPCO_Pos)

#define	ETH_MACCR_IPCO ETH_MACCR_IPCO_Msk /* IP Checksum offload */

#define	ETH_MACCR_RD_Pos (9U)

#define	ETH_MACCR_RD_Msk (0x1UL << ETH_MACCR_RD_Pos)

#define	ETH_MACCR_RD ETH_MACCR_RD_Msk /* Retry disable */

#define	ETH_MACCR_APCS_Pos (7U)

#define	ETH_MACCR_APCS_Msk (0x1UL << ETH_MACCR_APCS_Pos)

#define	ETH_MACCR_APCS ETH_MACCR_APCS_Msk /* Automatic Pad/CRC stripping */

#define	ETH_MACCR_BL_Pos (5U)

#define	ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos)

#define	ETH_MACCR_BL

#define	ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */

#define	ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */

#define	ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */

#define	ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */

#define	ETH_MACCR_DC_Pos (4U)

#define	ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos)

#define	ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */

#define	ETH_MACCR_TE_Pos (3U)

#define	ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos)

#define	ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */

#define	ETH_MACCR_RE_Pos (2U)

#define	ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos)

#define	ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */

#define	ETH_MACFFR_RA_Pos (31U)

#define	ETH_MACFFR_RA_Msk (0x1UL << ETH_MACFFR_RA_Pos)

#define	ETH_MACFFR_RA ETH_MACFFR_RA_Msk /* Receive all */

#define	ETH_MACFFR_HPF_Pos (10U)

#define	ETH_MACFFR_HPF_Msk (0x1UL << ETH_MACFFR_HPF_Pos)

#define	ETH_MACFFR_HPF ETH_MACFFR_HPF_Msk /* Hash or perfect filter */

#define	ETH_MACFFR_SAF_Pos (9U)

#define	ETH_MACFFR_SAF_Msk (0x1UL << ETH_MACFFR_SAF_Pos)

#define	ETH_MACFFR_SAF ETH_MACFFR_SAF_Msk /* Source address filter enable */

#define	ETH_MACFFR_SAIF_Pos (8U)

#define	ETH_MACFFR_SAIF_Msk (0x1UL << ETH_MACFFR_SAIF_Pos)

#define	ETH_MACFFR_SAIF ETH_MACFFR_SAIF_Msk /* SA inverse filtering */

#define	ETH_MACFFR_PCF_Pos (6U)

#define	ETH_MACFFR_PCF_Msk (0x3UL << ETH_MACFFR_PCF_Pos)

#define	ETH_MACFFR_PCF ETH_MACFFR_PCF_Msk /* Pass control frames: 3 cases */

#define	ETH_MACFFR_PCF_BlockAll_Pos (6U)

#define	ETH_MACFFR_PCF_BlockAll_Msk (0x1UL << ETH_MACFFR_PCF_BlockAll_Pos)

#define	ETH_MACFFR_PCF_BlockAll ETH_MACFFR_PCF_BlockAll_Msk /* MAC filters all control frames from reaching the application */

#define	ETH_MACFFR_PCF_ForwardAll_Pos (7U)

#define	ETH_MACFFR_PCF_ForwardAll_Msk (0x1UL << ETH_MACFFR_PCF_ForwardAll_Pos)

#define	ETH_MACFFR_PCF_ForwardAll ETH_MACFFR_PCF_ForwardAll_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */

#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos (6U)

#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk (0x3UL << ETH_MACFFR_PCF_ForwardPassedAddrFilter_Pos)

#define	ETH_MACFFR_PCF_ForwardPassedAddrFilter ETH_MACFFR_PCF_ForwardPassedAddrFilter_Msk /* MAC forwards control frames that pass the Address Filter. */

#define	ETH_MACFFR_BFD_Pos (5U)

#define	ETH_MACFFR_BFD_Msk (0x1UL << ETH_MACFFR_BFD_Pos)

#define	ETH_MACFFR_BFD ETH_MACFFR_BFD_Msk /* Broadcast frame disable */

#define	ETH_MACFFR_PAM_Pos (4U)

#define	ETH_MACFFR_PAM_Msk (0x1UL << ETH_MACFFR_PAM_Pos)

#define	ETH_MACFFR_PAM ETH_MACFFR_PAM_Msk /* Pass all mutlicast */

#define	ETH_MACFFR_DAIF_Pos (3U)

#define	ETH_MACFFR_DAIF_Msk (0x1UL << ETH_MACFFR_DAIF_Pos)

#define	ETH_MACFFR_DAIF ETH_MACFFR_DAIF_Msk /* DA Inverse filtering */

#define	ETH_MACFFR_HM_Pos (2U)

#define	ETH_MACFFR_HM_Msk (0x1UL << ETH_MACFFR_HM_Pos)

#define	ETH_MACFFR_HM ETH_MACFFR_HM_Msk /* Hash multicast */

#define	ETH_MACFFR_HU_Pos (1U)

#define	ETH_MACFFR_HU_Msk (0x1UL << ETH_MACFFR_HU_Pos)

#define	ETH_MACFFR_HU ETH_MACFFR_HU_Msk /* Hash unicast */

#define	ETH_MACFFR_PM_Pos (0U)

#define	ETH_MACFFR_PM_Msk (0x1UL << ETH_MACFFR_PM_Pos)

#define	ETH_MACFFR_PM ETH_MACFFR_PM_Msk /* Promiscuous mode */

#define	ETH_MACHTHR_HTH_Pos (0U)

#define	ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos)

#define	ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */

#define	ETH_MACHTLR_HTL_Pos (0U)

#define	ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos)

#define	ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */

#define	ETH_MACMIIAR_PA_Pos (11U)

#define	ETH_MACMIIAR_PA_Msk (0x1FUL << ETH_MACMIIAR_PA_Pos)

#define	ETH_MACMIIAR_PA ETH_MACMIIAR_PA_Msk /* Physical layer address */

#define	ETH_MACMIIAR_MR_Pos (6U)

#define	ETH_MACMIIAR_MR_Msk (0x1FUL << ETH_MACMIIAR_MR_Pos)

#define	ETH_MACMIIAR_MR ETH_MACMIIAR_MR_Msk /* MII register in the selected PHY */

#define	ETH_MACMIIAR_CR_Pos (2U)

#define	ETH_MACMIIAR_CR_Msk (0x7UL << ETH_MACMIIAR_CR_Pos)

#define	ETH_MACMIIAR_CR ETH_MACMIIAR_CR_Msk /* CR clock range: 6 cases */

#define	ETH_MACMIIAR_CR_DIV42 0x00000000U /* HCLK:60-72 MHz; MDC clock= HCLK/42 */

#define	ETH_MACMIIAR_CR_DIV16_Pos (3U)

#define	ETH_MACMIIAR_CR_DIV16_Msk (0x1UL << ETH_MACMIIAR_CR_DIV16_Pos)

#define	ETH_MACMIIAR_CR_DIV16 ETH_MACMIIAR_CR_DIV16_Msk /* HCLK:20-35 MHz; MDC clock= HCLK/16 */

#define	ETH_MACMIIAR_CR_DIV26_Pos (2U)

#define	ETH_MACMIIAR_CR_DIV26_Msk (0x3UL << ETH_MACMIIAR_CR_DIV26_Pos)

#define	ETH_MACMIIAR_CR_DIV26 ETH_MACMIIAR_CR_DIV26_Msk /* HCLK:35-60 MHz; MDC clock= HCLK/26 */

#define	ETH_MACMIIAR_MW_Pos (1U)

#define	ETH_MACMIIAR_MW_Msk (0x1UL << ETH_MACMIIAR_MW_Pos)

#define	ETH_MACMIIAR_MW ETH_MACMIIAR_MW_Msk /* MII write */

#define	ETH_MACMIIAR_MB_Pos (0U)

#define	ETH_MACMIIAR_MB_Msk (0x1UL << ETH_MACMIIAR_MB_Pos)

#define	ETH_MACMIIAR_MB ETH_MACMIIAR_MB_Msk /* MII busy */

#define	ETH_MACMIIDR_MD_Pos (0U)

#define	ETH_MACMIIDR_MD_Msk (0xFFFFUL << ETH_MACMIIDR_MD_Pos)

#define	ETH_MACMIIDR_MD ETH_MACMIIDR_MD_Msk /* MII data: read/write data from/to PHY */

#define	ETH_MACFCR_PT_Pos (16U)

#define	ETH_MACFCR_PT_Msk (0xFFFFUL << ETH_MACFCR_PT_Pos)

#define	ETH_MACFCR_PT ETH_MACFCR_PT_Msk /* Pause time */

#define	ETH_MACFCR_ZQPD_Pos (7U)

#define	ETH_MACFCR_ZQPD_Msk (0x1UL << ETH_MACFCR_ZQPD_Pos)

#define	ETH_MACFCR_ZQPD ETH_MACFCR_ZQPD_Msk /* Zero-quanta pause disable */

#define	ETH_MACFCR_PLT_Pos (4U)

#define	ETH_MACFCR_PLT_Msk (0x3UL << ETH_MACFCR_PLT_Pos)

#define	ETH_MACFCR_PLT ETH_MACFCR_PLT_Msk /* Pause low threshold: 4 cases */

#define	ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */

#define	ETH_MACFCR_PLT_Minus28_Pos (4U)

#define	ETH_MACFCR_PLT_Minus28_Msk (0x1UL << ETH_MACFCR_PLT_Minus28_Pos)

#define	ETH_MACFCR_PLT_Minus28 ETH_MACFCR_PLT_Minus28_Msk /* Pause time minus 28 slot times */

#define	ETH_MACFCR_PLT_Minus144_Pos (5U)

#define	ETH_MACFCR_PLT_Minus144_Msk (0x1UL << ETH_MACFCR_PLT_Minus144_Pos)

#define	ETH_MACFCR_PLT_Minus144 ETH_MACFCR_PLT_Minus144_Msk /* Pause time minus 144 slot times */

#define	ETH_MACFCR_PLT_Minus256_Pos (4U)

#define	ETH_MACFCR_PLT_Minus256_Msk (0x3UL << ETH_MACFCR_PLT_Minus256_Pos)

#define	ETH_MACFCR_PLT_Minus256 ETH_MACFCR_PLT_Minus256_Msk /* Pause time minus 256 slot times */

#define	ETH_MACFCR_UPFD_Pos (3U)

#define	ETH_MACFCR_UPFD_Msk (0x1UL << ETH_MACFCR_UPFD_Pos)

#define	ETH_MACFCR_UPFD ETH_MACFCR_UPFD_Msk /* Unicast pause frame detect */

#define	ETH_MACFCR_RFCE_Pos (2U)

#define	ETH_MACFCR_RFCE_Msk (0x1UL << ETH_MACFCR_RFCE_Pos)

#define	ETH_MACFCR_RFCE ETH_MACFCR_RFCE_Msk /* Receive flow control enable */

#define	ETH_MACFCR_TFCE_Pos (1U)

#define	ETH_MACFCR_TFCE_Msk (0x1UL << ETH_MACFCR_TFCE_Pos)

#define	ETH_MACFCR_TFCE ETH_MACFCR_TFCE_Msk /* Transmit flow control enable */

#define	ETH_MACFCR_FCBBPA_Pos (0U)

#define	ETH_MACFCR_FCBBPA_Msk (0x1UL << ETH_MACFCR_FCBBPA_Pos)

#define	ETH_MACFCR_FCBBPA ETH_MACFCR_FCBBPA_Msk /* Flow control busy/backpressure activate */

#define	ETH_MACVLANTR_VLANTC_Pos (16U)

#define	ETH_MACVLANTR_VLANTC_Msk (0x1UL << ETH_MACVLANTR_VLANTC_Pos)

#define	ETH_MACVLANTR_VLANTC ETH_MACVLANTR_VLANTC_Msk /* 12-bit VLAN tag comparison */

#define	ETH_MACVLANTR_VLANTI_Pos (0U)

#define	ETH_MACVLANTR_VLANTI_Msk (0xFFFFUL << ETH_MACVLANTR_VLANTI_Pos)

#define	ETH_MACVLANTR_VLANTI ETH_MACVLANTR_VLANTI_Msk /* VLAN tag identifier (for receive frames) */

#define	ETH_MACRWUFFR_D_Pos (0U)

#define	ETH_MACRWUFFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUFFR_D_Pos)

#define	ETH_MACRWUFFR_D ETH_MACRWUFFR_D_Msk /* Wake-up frame filter register data */

#define	ETH_MACPMTCSR_WFFRPR_Pos (31U)

#define	ETH_MACPMTCSR_WFFRPR_Msk (0x1UL << ETH_MACPMTCSR_WFFRPR_Pos)

#define	ETH_MACPMTCSR_WFFRPR ETH_MACPMTCSR_WFFRPR_Msk /* Wake-Up Frame Filter Register Pointer Reset */

#define	ETH_MACPMTCSR_GU_Pos (9U)

#define	ETH_MACPMTCSR_GU_Msk (0x1UL << ETH_MACPMTCSR_GU_Pos)

#define	ETH_MACPMTCSR_GU ETH_MACPMTCSR_GU_Msk /* Global Unicast */

#define	ETH_MACPMTCSR_WFR_Pos (6U)

#define	ETH_MACPMTCSR_WFR_Msk (0x1UL << ETH_MACPMTCSR_WFR_Pos)

#define	ETH_MACPMTCSR_WFR ETH_MACPMTCSR_WFR_Msk /* Wake-Up Frame Received */

#define	ETH_MACPMTCSR_MPR_Pos (5U)

#define	ETH_MACPMTCSR_MPR_Msk (0x1UL << ETH_MACPMTCSR_MPR_Pos)

#define	ETH_MACPMTCSR_MPR ETH_MACPMTCSR_MPR_Msk /* Magic Packet Received */

#define	ETH_MACPMTCSR_WFE_Pos (2U)

#define	ETH_MACPMTCSR_WFE_Msk (0x1UL << ETH_MACPMTCSR_WFE_Pos)

#define	ETH_MACPMTCSR_WFE ETH_MACPMTCSR_WFE_Msk /* Wake-Up Frame Enable */

#define	ETH_MACPMTCSR_MPE_Pos (1U)

#define	ETH_MACPMTCSR_MPE_Msk (0x1UL << ETH_MACPMTCSR_MPE_Pos)

#define	ETH_MACPMTCSR_MPE ETH_MACPMTCSR_MPE_Msk /* Magic Packet Enable */

#define	ETH_MACPMTCSR_PD_Pos (0U)

#define	ETH_MACPMTCSR_PD_Msk (0x1UL << ETH_MACPMTCSR_PD_Pos)

#define	ETH_MACPMTCSR_PD ETH_MACPMTCSR_PD_Msk /* Power Down */

#define	ETH_MACSR_TSTS_Pos (9U)

#define	ETH_MACSR_TSTS_Msk (0x1UL << ETH_MACSR_TSTS_Pos)

#define	ETH_MACSR_TSTS ETH_MACSR_TSTS_Msk /* Time stamp trigger status */

#define	ETH_MACSR_MMCTS_Pos (6U)

#define	ETH_MACSR_MMCTS_Msk (0x1UL << ETH_MACSR_MMCTS_Pos)

#define	ETH_MACSR_MMCTS ETH_MACSR_MMCTS_Msk /* MMC transmit status */

#define	ETH_MACSR_MMMCRS_Pos (5U)

#define	ETH_MACSR_MMMCRS_Msk (0x1UL << ETH_MACSR_MMMCRS_Pos)

#define	ETH_MACSR_MMMCRS ETH_MACSR_MMMCRS_Msk /* MMC receive status */

#define	ETH_MACSR_MMCS_Pos (4U)

#define	ETH_MACSR_MMCS_Msk (0x1UL << ETH_MACSR_MMCS_Pos)

#define	ETH_MACSR_MMCS ETH_MACSR_MMCS_Msk /* MMC status */

#define	ETH_MACSR_PMTS_Pos (3U)

#define	ETH_MACSR_PMTS_Msk (0x1UL << ETH_MACSR_PMTS_Pos)

#define	ETH_MACSR_PMTS ETH_MACSR_PMTS_Msk /* PMT status */

#define	ETH_MACIMR_TSTIM_Pos (9U)

#define	ETH_MACIMR_TSTIM_Msk (0x1UL << ETH_MACIMR_TSTIM_Pos)

#define	ETH_MACIMR_TSTIM ETH_MACIMR_TSTIM_Msk /* Time stamp trigger interrupt mask */

#define	ETH_MACIMR_PMTIM_Pos (3U)

#define	ETH_MACIMR_PMTIM_Msk (0x1UL << ETH_MACIMR_PMTIM_Pos)

#define	ETH_MACIMR_PMTIM ETH_MACIMR_PMTIM_Msk /* PMT interrupt mask */

#define	ETH_MACA0HR_MACA0H_Pos (0U)

#define	ETH_MACA0HR_MACA0H_Msk (0xFFFFUL << ETH_MACA0HR_MACA0H_Pos)

#define	ETH_MACA0HR_MACA0H ETH_MACA0HR_MACA0H_Msk /* MAC address0 high */

#define	ETH_MACA0LR_MACA0L_Pos (0U)

#define	ETH_MACA0LR_MACA0L_Msk (0xFFFFFFFFUL << ETH_MACA0LR_MACA0L_Pos)

#define	ETH_MACA0LR_MACA0L ETH_MACA0LR_MACA0L_Msk /* MAC address0 low */

#define	ETH_MACA1HR_AE_Pos (31U)

#define	ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos)

#define	ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address enable */

#define	ETH_MACA1HR_SA_Pos (30U)

#define	ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos)

#define	ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source address */

#define	ETH_MACA1HR_MBC_Pos (24U)

#define	ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos)

#define	ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */

#define	ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */

#define	ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */

#define	ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */

#define	ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */

#define	ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */

#define	ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */

#define	ETH_MACA1HR_MACA1H_Pos (0U)

#define	ETH_MACA1HR_MACA1H_Msk (0xFFFFUL << ETH_MACA1HR_MACA1H_Pos)

#define	ETH_MACA1HR_MACA1H ETH_MACA1HR_MACA1H_Msk /* MAC address1 high */

#define	ETH_MACA1LR_MACA1L_Pos (0U)

#define	ETH_MACA1LR_MACA1L_Msk (0xFFFFFFFFUL << ETH_MACA1LR_MACA1L_Pos)

#define	ETH_MACA1LR_MACA1L ETH_MACA1LR_MACA1L_Msk /* MAC address1 low */

#define	ETH_MACA2HR_AE_Pos (31U)

#define	ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos)

#define	ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address enable */

#define	ETH_MACA2HR_SA_Pos (30U)

#define	ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos)

#define	ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source address */

#define	ETH_MACA2HR_MBC_Pos (24U)

#define	ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos)

#define	ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask byte control */

#define	ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */

#define	ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */

#define	ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */

#define	ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */

#define	ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */

#define	ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */

#define	ETH_MACA2HR_MACA2H_Pos (0U)

#define	ETH_MACA2HR_MACA2H_Msk (0xFFFFUL << ETH_MACA2HR_MACA2H_Pos)

#define	ETH_MACA2HR_MACA2H ETH_MACA2HR_MACA2H_Msk /* MAC address1 high */

#define	ETH_MACA2LR_MACA2L_Pos (0U)

#define	ETH_MACA2LR_MACA2L_Msk (0xFFFFFFFFUL << ETH_MACA2LR_MACA2L_Pos)

#define	ETH_MACA2LR_MACA2L ETH_MACA2LR_MACA2L_Msk /* MAC address2 low */

#define	ETH_MACA3HR_AE_Pos (31U)

#define	ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos)

#define	ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address enable */

#define	ETH_MACA3HR_SA_Pos (30U)

#define	ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos)

#define	ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source address */

#define	ETH_MACA3HR_MBC_Pos (24U)

#define	ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos)

#define	ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask byte control */

#define	ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */

#define	ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */

#define	ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */

#define	ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */

#define	ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */

#define	ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */

#define	ETH_MACA3HR_MACA3H_Pos (0U)

#define	ETH_MACA3HR_MACA3H_Msk (0xFFFFUL << ETH_MACA3HR_MACA3H_Pos)

#define	ETH_MACA3HR_MACA3H ETH_MACA3HR_MACA3H_Msk /* MAC address3 high */

#define	ETH_MACA3LR_MACA3L_Pos (0U)

#define	ETH_MACA3LR_MACA3L_Msk (0xFFFFFFFFUL << ETH_MACA3LR_MACA3L_Pos)

#define	ETH_MACA3LR_MACA3L ETH_MACA3LR_MACA3L_Msk /* MAC address3 low */

#define	ETH_MMCCR_MCF_Pos (3U)

#define	ETH_MMCCR_MCF_Msk (0x1UL << ETH_MMCCR_MCF_Pos)

#define	ETH_MMCCR_MCF ETH_MMCCR_MCF_Msk /* MMC Counter Freeze */

#define	ETH_MMCCR_ROR_Pos (2U)

#define	ETH_MMCCR_ROR_Msk (0x1UL << ETH_MMCCR_ROR_Pos)

#define	ETH_MMCCR_ROR ETH_MMCCR_ROR_Msk /* Reset on Read */

#define	ETH_MMCCR_CSR_Pos (1U)

#define	ETH_MMCCR_CSR_Msk (0x1UL << ETH_MMCCR_CSR_Pos)

#define	ETH_MMCCR_CSR ETH_MMCCR_CSR_Msk /* Counter Stop Rollover */

#define	ETH_MMCCR_CR_Pos (0U)

#define	ETH_MMCCR_CR_Msk (0x1UL << ETH_MMCCR_CR_Pos)

#define	ETH_MMCCR_CR ETH_MMCCR_CR_Msk /* Counters Reset */

#define	ETH_MMCRIR_RGUFS_Pos (17U)

#define	ETH_MMCRIR_RGUFS_Msk (0x1UL << ETH_MMCRIR_RGUFS_Pos)

#define	ETH_MMCRIR_RGUFS ETH_MMCRIR_RGUFS_Msk /* Set when Rx good unicast frames counter reaches half the maximum value */

#define	ETH_MMCRIR_RFAES_Pos (6U)

#define	ETH_MMCRIR_RFAES_Msk (0x1UL << ETH_MMCRIR_RFAES_Pos)

#define	ETH_MMCRIR_RFAES ETH_MMCRIR_RFAES_Msk /* Set when Rx alignment error counter reaches half the maximum value */

#define	ETH_MMCRIR_RFCES_Pos (5U)

#define	ETH_MMCRIR_RFCES_Msk (0x1UL << ETH_MMCRIR_RFCES_Pos)

#define	ETH_MMCRIR_RFCES ETH_MMCRIR_RFCES_Msk /* Set when Rx crc error counter reaches half the maximum value */

#define	ETH_MMCTIR_TGFS_Pos (21U)

#define	ETH_MMCTIR_TGFS_Msk (0x1UL << ETH_MMCTIR_TGFS_Pos)

#define	ETH_MMCTIR_TGFS ETH_MMCTIR_TGFS_Msk /* Set when Tx good frame count counter reaches half the maximum value */

#define	ETH_MMCTIR_TGFMSCS_Pos (15U)

#define	ETH_MMCTIR_TGFMSCS_Msk (0x1UL << ETH_MMCTIR_TGFMSCS_Pos)

#define	ETH_MMCTIR_TGFMSCS ETH_MMCTIR_TGFMSCS_Msk /* Set when Tx good multi col counter reaches half the maximum value */

#define	ETH_MMCTIR_TGFSCS_Pos (14U)

#define	ETH_MMCTIR_TGFSCS_Msk (0x1UL << ETH_MMCTIR_TGFSCS_Pos)

#define	ETH_MMCTIR_TGFSCS ETH_MMCTIR_TGFSCS_Msk /* Set when Tx good single col counter reaches half the maximum value */

#define	ETH_MMCRIMR_RGUFM_Pos (17U)

#define	ETH_MMCRIMR_RGUFM_Msk (0x1UL << ETH_MMCRIMR_RGUFM_Pos)

#define	ETH_MMCRIMR_RGUFM ETH_MMCRIMR_RGUFM_Msk /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */

#define	ETH_MMCRIMR_RFAEM_Pos (6U)

#define	ETH_MMCRIMR_RFAEM_Msk (0x1UL << ETH_MMCRIMR_RFAEM_Pos)

#define	ETH_MMCRIMR_RFAEM ETH_MMCRIMR_RFAEM_Msk /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */

#define	ETH_MMCRIMR_RFCEM_Pos (5U)

#define	ETH_MMCRIMR_RFCEM_Msk (0x1UL << ETH_MMCRIMR_RFCEM_Pos)

#define	ETH_MMCRIMR_RFCEM ETH_MMCRIMR_RFCEM_Msk /* Mask the interrupt when Rx crc error counter reaches half the maximum value */

#define	ETH_MMCTIMR_TGFM_Pos (21U)

#define	ETH_MMCTIMR_TGFM_Msk (0x1UL << ETH_MMCTIMR_TGFM_Pos)

#define	ETH_MMCTIMR_TGFM ETH_MMCTIMR_TGFM_Msk /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */

#define	ETH_MMCTIMR_TGFMSCM_Pos (15U)

#define	ETH_MMCTIMR_TGFMSCM_Msk (0x1UL << ETH_MMCTIMR_TGFMSCM_Pos)

#define	ETH_MMCTIMR_TGFMSCM ETH_MMCTIMR_TGFMSCM_Msk /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */

#define	ETH_MMCTIMR_TGFSCM_Pos (14U)

#define	ETH_MMCTIMR_TGFSCM_Msk (0x1UL << ETH_MMCTIMR_TGFSCM_Pos)

#define	ETH_MMCTIMR_TGFSCM ETH_MMCTIMR_TGFSCM_Msk /* Mask the interrupt when Tx good single col counter reaches half the maximum value */

#define	ETH_MMCTGFSCCR_TGFSCC_Pos (0U)

#define	ETH_MMCTGFSCCR_TGFSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFSCCR_TGFSCC_Pos)

#define	ETH_MMCTGFSCCR_TGFSCC ETH_MMCTGFSCCR_TGFSCC_Msk /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */

#define	ETH_MMCTGFMSCCR_TGFMSCC_Pos (0U)

#define	ETH_MMCTGFMSCCR_TGFMSCC_Msk (0xFFFFFFFFUL << ETH_MMCTGFMSCCR_TGFMSCC_Pos)

#define	ETH_MMCTGFMSCCR_TGFMSCC ETH_MMCTGFMSCCR_TGFMSCC_Msk /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */

#define	ETH_MMCTGFCR_TGFC_Pos (0U)

#define	ETH_MMCTGFCR_TGFC_Msk (0xFFFFFFFFUL << ETH_MMCTGFCR_TGFC_Pos)

#define	ETH_MMCTGFCR_TGFC ETH_MMCTGFCR_TGFC_Msk /* Number of good frames transmitted. */

#define	ETH_MMCRFCECR_RFCEC_Pos (0U)

#define	ETH_MMCRFCECR_RFCEC_Msk (0xFFFFFFFFUL << ETH_MMCRFCECR_RFCEC_Pos)

#define	ETH_MMCRFCECR_RFCEC ETH_MMCRFCECR_RFCEC_Msk /* Number of frames received with CRC error. */

#define	ETH_MMCRFAECR_RFAEC_Pos (0U)

#define	ETH_MMCRFAECR_RFAEC_Msk (0xFFFFFFFFUL << ETH_MMCRFAECR_RFAEC_Pos)

#define	ETH_MMCRFAECR_RFAEC ETH_MMCRFAECR_RFAEC_Msk /* Number of frames received with alignment (dribble) error */

#define	ETH_MMCRGUFCR_RGUFC_Pos (0U)

#define	ETH_MMCRGUFCR_RGUFC_Msk (0xFFFFFFFFUL << ETH_MMCRGUFCR_RGUFC_Pos)

#define	ETH_MMCRGUFCR_RGUFC ETH_MMCRGUFCR_RGUFC_Msk /* Number of good unicast frames received. */

#define	ETH_PTPTSCR_TSARU_Pos (5U)

#define	ETH_PTPTSCR_TSARU_Msk (0x1UL << ETH_PTPTSCR_TSARU_Pos)

#define	ETH_PTPTSCR_TSARU ETH_PTPTSCR_TSARU_Msk /* Addend register update */

#define	ETH_PTPTSCR_TSITE_Pos (4U)

#define	ETH_PTPTSCR_TSITE_Msk (0x1UL << ETH_PTPTSCR_TSITE_Pos)

#define	ETH_PTPTSCR_TSITE ETH_PTPTSCR_TSITE_Msk /* Time stamp interrupt trigger enable */

#define	ETH_PTPTSCR_TSSTU_Pos (3U)

#define	ETH_PTPTSCR_TSSTU_Msk (0x1UL << ETH_PTPTSCR_TSSTU_Pos)

#define	ETH_PTPTSCR_TSSTU ETH_PTPTSCR_TSSTU_Msk /* Time stamp update */

#define	ETH_PTPTSCR_TSSTI_Pos (2U)

#define	ETH_PTPTSCR_TSSTI_Msk (0x1UL << ETH_PTPTSCR_TSSTI_Pos)

#define	ETH_PTPTSCR_TSSTI ETH_PTPTSCR_TSSTI_Msk /* Time stamp initialize */

#define	ETH_PTPTSCR_TSFCU_Pos (1U)

#define	ETH_PTPTSCR_TSFCU_Msk (0x1UL << ETH_PTPTSCR_TSFCU_Pos)

#define	ETH_PTPTSCR_TSFCU ETH_PTPTSCR_TSFCU_Msk /* Time stamp fine or coarse update */

#define	ETH_PTPTSCR_TSE_Pos (0U)

#define	ETH_PTPTSCR_TSE_Msk (0x1UL << ETH_PTPTSCR_TSE_Pos)

#define	ETH_PTPTSCR_TSE ETH_PTPTSCR_TSE_Msk /* Time stamp enable */

#define	ETH_PTPSSIR_STSSI_Pos (0U)

#define	ETH_PTPSSIR_STSSI_Msk (0xFFUL << ETH_PTPSSIR_STSSI_Pos)

#define	ETH_PTPSSIR_STSSI ETH_PTPSSIR_STSSI_Msk /* System time Sub-second increment value */

#define	ETH_PTPTSHR_STS_Pos (0U)

#define	ETH_PTPTSHR_STS_Msk (0xFFFFFFFFUL << ETH_PTPTSHR_STS_Pos)

#define	ETH_PTPTSHR_STS ETH_PTPTSHR_STS_Msk /* System Time second */

#define	ETH_PTPTSLR_STPNS_Pos (31U)

#define	ETH_PTPTSLR_STPNS_Msk (0x1UL << ETH_PTPTSLR_STPNS_Pos)

#define	ETH_PTPTSLR_STPNS ETH_PTPTSLR_STPNS_Msk /* System Time Positive or negative time */

#define	ETH_PTPTSLR_STSS_Pos (0U)

#define	ETH_PTPTSLR_STSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLR_STSS_Pos)

#define	ETH_PTPTSLR_STSS ETH_PTPTSLR_STSS_Msk /* System Time sub-seconds */

#define	ETH_PTPTSHUR_TSUS_Pos (0U)

#define	ETH_PTPTSHUR_TSUS_Msk (0xFFFFFFFFUL << ETH_PTPTSHUR_TSUS_Pos)

#define	ETH_PTPTSHUR_TSUS ETH_PTPTSHUR_TSUS_Msk /* Time stamp update seconds */

#define	ETH_PTPTSLUR_TSUPNS_Pos (31U)

#define	ETH_PTPTSLUR_TSUPNS_Msk (0x1UL << ETH_PTPTSLUR_TSUPNS_Pos)

#define	ETH_PTPTSLUR_TSUPNS ETH_PTPTSLUR_TSUPNS_Msk /* Time stamp update Positive or negative time */

#define	ETH_PTPTSLUR_TSUSS_Pos (0U)

#define	ETH_PTPTSLUR_TSUSS_Msk (0x7FFFFFFFUL << ETH_PTPTSLUR_TSUSS_Pos)

#define	ETH_PTPTSLUR_TSUSS ETH_PTPTSLUR_TSUSS_Msk /* Time stamp update sub-seconds */

#define	ETH_PTPTSAR_TSA_Pos (0U)

#define	ETH_PTPTSAR_TSA_Msk (0xFFFFFFFFUL << ETH_PTPTSAR_TSA_Pos)

#define	ETH_PTPTSAR_TSA ETH_PTPTSAR_TSA_Msk /* Time stamp addend */

#define	ETH_PTPTTHR_TTSH_Pos (0U)

#define	ETH_PTPTTHR_TTSH_Msk (0xFFFFFFFFUL << ETH_PTPTTHR_TTSH_Pos)

#define	ETH_PTPTTHR_TTSH ETH_PTPTTHR_TTSH_Msk /* Target time stamp high */

#define	ETH_PTPTTLR_TTSL_Pos (0U)

#define	ETH_PTPTTLR_TTSL_Msk (0xFFFFFFFFUL << ETH_PTPTTLR_TTSL_Pos)

#define	ETH_PTPTTLR_TTSL ETH_PTPTTLR_TTSL_Msk /* Target time stamp low */

#define	ETH_DMABMR_AAB_Pos (25U)

#define	ETH_DMABMR_AAB_Msk (0x1UL << ETH_DMABMR_AAB_Pos)

#define	ETH_DMABMR_AAB ETH_DMABMR_AAB_Msk /* Address-Aligned beats */

#define	ETH_DMABMR_FPM_Pos (24U)

#define	ETH_DMABMR_FPM_Msk (0x1UL << ETH_DMABMR_FPM_Pos)

#define	ETH_DMABMR_FPM ETH_DMABMR_FPM_Msk /* 4xPBL mode */

#define	ETH_DMABMR_USP_Pos (23U)

#define	ETH_DMABMR_USP_Msk (0x1UL << ETH_DMABMR_USP_Pos)

#define	ETH_DMABMR_USP ETH_DMABMR_USP_Msk /* Use separate PBL */

#define	ETH_DMABMR_RDP_Pos (17U)

#define	ETH_DMABMR_RDP_Msk (0x3FUL << ETH_DMABMR_RDP_Pos)

#define	ETH_DMABMR_RDP ETH_DMABMR_RDP_Msk /* RxDMA PBL */

#define	ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */

#define	ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */

#define	ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

#define	ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

#define	ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

#define	ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

#define	ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */

#define	ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */

#define	ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */

#define	ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */

#define	ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */

#define	ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */

#define	ETH_DMABMR_FB_Pos (16U)

#define	ETH_DMABMR_FB_Msk (0x1UL << ETH_DMABMR_FB_Pos)

#define	ETH_DMABMR_FB ETH_DMABMR_FB_Msk /* Fixed Burst */

#define	ETH_DMABMR_RTPR_Pos (14U)

#define	ETH_DMABMR_RTPR_Msk (0x3UL << ETH_DMABMR_RTPR_Pos)

#define	ETH_DMABMR_RTPR ETH_DMABMR_RTPR_Msk /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */

#define	ETH_DMABMR_PBL_Pos (8U)

#define	ETH_DMABMR_PBL_Msk (0x3FUL << ETH_DMABMR_PBL_Pos)

#define	ETH_DMABMR_PBL ETH_DMABMR_PBL_Msk /* Programmable burst length */

#define	ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */

#define	ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */

#define	ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

#define	ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

#define	ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

#define	ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

#define	ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */

#define	ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */

#define	ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */

#define	ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */

#define	ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */

#define	ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */

#define	ETH_DMABMR_DSL_Pos (2U)

#define	ETH_DMABMR_DSL_Msk (0x1FUL << ETH_DMABMR_DSL_Pos)

#define	ETH_DMABMR_DSL ETH_DMABMR_DSL_Msk /* Descriptor Skip Length */

#define	ETH_DMABMR_DA_Pos (1U)

#define	ETH_DMABMR_DA_Msk (0x1UL << ETH_DMABMR_DA_Pos)

#define	ETH_DMABMR_DA ETH_DMABMR_DA_Msk /* DMA arbitration scheme */

#define	ETH_DMABMR_SR_Pos (0U)

#define	ETH_DMABMR_SR_Msk (0x1UL << ETH_DMABMR_SR_Pos)

#define	ETH_DMABMR_SR ETH_DMABMR_SR_Msk /* Software reset */

#define	ETH_DMATPDR_TPD_Pos (0U)

#define	ETH_DMATPDR_TPD_Msk (0xFFFFFFFFUL << ETH_DMATPDR_TPD_Pos)

#define	ETH_DMATPDR_TPD ETH_DMATPDR_TPD_Msk /* Transmit poll demand */

#define	ETH_DMARPDR_RPD_Pos (0U)

#define	ETH_DMARPDR_RPD_Msk (0xFFFFFFFFUL << ETH_DMARPDR_RPD_Pos)

#define	ETH_DMARPDR_RPD ETH_DMARPDR_RPD_Msk /* Receive poll demand */

#define	ETH_DMARDLAR_SRL_Pos (0U)

#define	ETH_DMARDLAR_SRL_Msk (0xFFFFFFFFUL << ETH_DMARDLAR_SRL_Pos)

#define	ETH_DMARDLAR_SRL ETH_DMARDLAR_SRL_Msk /* Start of receive list */

#define	ETH_DMATDLAR_STL_Pos (0U)

#define	ETH_DMATDLAR_STL_Msk (0xFFFFFFFFUL << ETH_DMATDLAR_STL_Pos)

#define	ETH_DMATDLAR_STL ETH_DMATDLAR_STL_Msk /* Start of transmit list */

#define	ETH_DMASR_TSTS_Pos (29U)

#define	ETH_DMASR_TSTS_Msk (0x1UL << ETH_DMASR_TSTS_Pos)

#define	ETH_DMASR_TSTS ETH_DMASR_TSTS_Msk /* Time-stamp trigger status */

#define	ETH_DMASR_PMTS_Pos (28U)

#define	ETH_DMASR_PMTS_Msk (0x1UL << ETH_DMASR_PMTS_Pos)

#define	ETH_DMASR_PMTS ETH_DMASR_PMTS_Msk /* PMT status */

#define	ETH_DMASR_MMCS_Pos (27U)

#define	ETH_DMASR_MMCS_Msk (0x1UL << ETH_DMASR_MMCS_Pos)

#define	ETH_DMASR_MMCS ETH_DMASR_MMCS_Msk /* MMC status */

#define	ETH_DMASR_EBS_Pos (23U)

#define	ETH_DMASR_EBS_Msk (0x7UL << ETH_DMASR_EBS_Pos)

#define	ETH_DMASR_EBS ETH_DMASR_EBS_Msk /* Error bits status */

#define	ETH_DMASR_EBS_DescAccess_Pos (25U)

#define	ETH_DMASR_EBS_DescAccess_Msk (0x1UL << ETH_DMASR_EBS_DescAccess_Pos)

#define	ETH_DMASR_EBS_DescAccess ETH_DMASR_EBS_DescAccess_Msk /* Error bits 0-data buffer, 1-desc. access */

#define	ETH_DMASR_EBS_ReadTransf_Pos (24U)

#define	ETH_DMASR_EBS_ReadTransf_Msk (0x1UL << ETH_DMASR_EBS_ReadTransf_Pos)

#define	ETH_DMASR_EBS_ReadTransf ETH_DMASR_EBS_ReadTransf_Msk /* Error bits 0-write trnsf, 1-read transfr */

#define	ETH_DMASR_EBS_DataTransfTx_Pos (23U)

#define	ETH_DMASR_EBS_DataTransfTx_Msk (0x1UL << ETH_DMASR_EBS_DataTransfTx_Pos)

#define	ETH_DMASR_EBS_DataTransfTx ETH_DMASR_EBS_DataTransfTx_Msk /* Error bits 0-Rx DMA, 1-Tx DMA */

#define	ETH_DMASR_TPS_Pos (20U)

#define	ETH_DMASR_TPS_Msk (0x7UL << ETH_DMASR_TPS_Pos)

#define	ETH_DMASR_TPS ETH_DMASR_TPS_Msk /* Transmit process state */

#define	ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */

#define	ETH_DMASR_TPS_Fetching_Pos (20U)

#define	ETH_DMASR_TPS_Fetching_Msk (0x1UL << ETH_DMASR_TPS_Fetching_Pos)

#define	ETH_DMASR_TPS_Fetching ETH_DMASR_TPS_Fetching_Msk /* Running - fetching the Tx descriptor */

#define	ETH_DMASR_TPS_Waiting_Pos (21U)

#define	ETH_DMASR_TPS_Waiting_Msk (0x1UL << ETH_DMASR_TPS_Waiting_Pos)

#define	ETH_DMASR_TPS_Waiting ETH_DMASR_TPS_Waiting_Msk /* Running - waiting for status */

#define	ETH_DMASR_TPS_Reading_Pos (20U)

#define	ETH_DMASR_TPS_Reading_Msk (0x3UL << ETH_DMASR_TPS_Reading_Pos)

#define	ETH_DMASR_TPS_Reading ETH_DMASR_TPS_Reading_Msk /* Running - reading the data from host memory */

#define	ETH_DMASR_TPS_Suspended_Pos (21U)

#define	ETH_DMASR_TPS_Suspended_Msk (0x3UL << ETH_DMASR_TPS_Suspended_Pos)

#define	ETH_DMASR_TPS_Suspended ETH_DMASR_TPS_Suspended_Msk /* Suspended - Tx Descriptor unavailabe */

#define	ETH_DMASR_TPS_Closing_Pos (20U)

#define	ETH_DMASR_TPS_Closing_Msk (0x7UL << ETH_DMASR_TPS_Closing_Pos)

#define	ETH_DMASR_TPS_Closing ETH_DMASR_TPS_Closing_Msk /* Running - closing Rx descriptor */

#define	ETH_DMASR_RPS_Pos (17U)

#define	ETH_DMASR_RPS_Msk (0x7UL << ETH_DMASR_RPS_Pos)

#define	ETH_DMASR_RPS ETH_DMASR_RPS_Msk /* Receive process state */

#define	ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */

#define	ETH_DMASR_RPS_Fetching_Pos (17U)

#define	ETH_DMASR_RPS_Fetching_Msk (0x1UL << ETH_DMASR_RPS_Fetching_Pos)

#define	ETH_DMASR_RPS_Fetching ETH_DMASR_RPS_Fetching_Msk /* Running - fetching the Rx descriptor */

#define	ETH_DMASR_RPS_Waiting_Pos (17U)

#define	ETH_DMASR_RPS_Waiting_Msk (0x3UL << ETH_DMASR_RPS_Waiting_Pos)

#define	ETH_DMASR_RPS_Waiting ETH_DMASR_RPS_Waiting_Msk /* Running - waiting for packet */

#define	ETH_DMASR_RPS_Suspended_Pos (19U)

#define	ETH_DMASR_RPS_Suspended_Msk (0x1UL << ETH_DMASR_RPS_Suspended_Pos)

#define	ETH_DMASR_RPS_Suspended ETH_DMASR_RPS_Suspended_Msk /* Suspended - Rx Descriptor unavailable */

#define	ETH_DMASR_RPS_Closing_Pos (17U)

#define	ETH_DMASR_RPS_Closing_Msk (0x5UL << ETH_DMASR_RPS_Closing_Pos)

#define	ETH_DMASR_RPS_Closing ETH_DMASR_RPS_Closing_Msk /* Running - closing descriptor */

#define	ETH_DMASR_RPS_Queuing_Pos (17U)

#define	ETH_DMASR_RPS_Queuing_Msk (0x7UL << ETH_DMASR_RPS_Queuing_Pos)

#define	ETH_DMASR_RPS_Queuing ETH_DMASR_RPS_Queuing_Msk /* Running - queuing the recieve frame into host memory */

#define	ETH_DMASR_NIS_Pos (16U)

#define	ETH_DMASR_NIS_Msk (0x1UL << ETH_DMASR_NIS_Pos)

#define	ETH_DMASR_NIS ETH_DMASR_NIS_Msk /* Normal interrupt summary */

#define	ETH_DMASR_AIS_Pos (15U)

#define	ETH_DMASR_AIS_Msk (0x1UL << ETH_DMASR_AIS_Pos)

#define	ETH_DMASR_AIS ETH_DMASR_AIS_Msk /* Abnormal interrupt summary */

#define	ETH_DMASR_ERS_Pos (14U)

#define	ETH_DMASR_ERS_Msk (0x1UL << ETH_DMASR_ERS_Pos)

#define	ETH_DMASR_ERS ETH_DMASR_ERS_Msk /* Early receive status */

#define	ETH_DMASR_FBES_Pos (13U)

#define	ETH_DMASR_FBES_Msk (0x1UL << ETH_DMASR_FBES_Pos)

#define	ETH_DMASR_FBES ETH_DMASR_FBES_Msk /* Fatal bus error status */

#define	ETH_DMASR_ETS_Pos (10U)

#define	ETH_DMASR_ETS_Msk (0x1UL << ETH_DMASR_ETS_Pos)

#define	ETH_DMASR_ETS ETH_DMASR_ETS_Msk /* Early transmit status */

#define	ETH_DMASR_RWTS_Pos (9U)

#define	ETH_DMASR_RWTS_Msk (0x1UL << ETH_DMASR_RWTS_Pos)

#define	ETH_DMASR_RWTS ETH_DMASR_RWTS_Msk /* Receive watchdog timeout status */

#define	ETH_DMASR_RPSS_Pos (8U)

#define	ETH_DMASR_RPSS_Msk (0x1UL << ETH_DMASR_RPSS_Pos)

#define	ETH_DMASR_RPSS ETH_DMASR_RPSS_Msk /* Receive process stopped status */

#define	ETH_DMASR_RBUS_Pos (7U)

#define	ETH_DMASR_RBUS_Msk (0x1UL << ETH_DMASR_RBUS_Pos)

#define	ETH_DMASR_RBUS ETH_DMASR_RBUS_Msk /* Receive buffer unavailable status */

#define	ETH_DMASR_RS_Pos (6U)

#define	ETH_DMASR_RS_Msk (0x1UL << ETH_DMASR_RS_Pos)

#define	ETH_DMASR_RS ETH_DMASR_RS_Msk /* Receive status */

#define	ETH_DMASR_TUS_Pos (5U)

#define	ETH_DMASR_TUS_Msk (0x1UL << ETH_DMASR_TUS_Pos)

#define	ETH_DMASR_TUS ETH_DMASR_TUS_Msk /* Transmit underflow status */

#define	ETH_DMASR_ROS_Pos (4U)

#define	ETH_DMASR_ROS_Msk (0x1UL << ETH_DMASR_ROS_Pos)

#define	ETH_DMASR_ROS ETH_DMASR_ROS_Msk /* Receive overflow status */

#define	ETH_DMASR_TJTS_Pos (3U)

#define	ETH_DMASR_TJTS_Msk (0x1UL << ETH_DMASR_TJTS_Pos)

#define	ETH_DMASR_TJTS ETH_DMASR_TJTS_Msk /* Transmit jabber timeout status */

#define	ETH_DMASR_TBUS_Pos (2U)

#define	ETH_DMASR_TBUS_Msk (0x1UL << ETH_DMASR_TBUS_Pos)

#define	ETH_DMASR_TBUS ETH_DMASR_TBUS_Msk /* Transmit buffer unavailable status */

#define	ETH_DMASR_TPSS_Pos (1U)

#define	ETH_DMASR_TPSS_Msk (0x1UL << ETH_DMASR_TPSS_Pos)

#define	ETH_DMASR_TPSS ETH_DMASR_TPSS_Msk /* Transmit process stopped status */

#define	ETH_DMASR_TS_Pos (0U)

#define	ETH_DMASR_TS_Msk (0x1UL << ETH_DMASR_TS_Pos)

#define	ETH_DMASR_TS ETH_DMASR_TS_Msk /* Transmit status */

#define	ETH_DMAOMR_DTCEFD_Pos (26U)

#define	ETH_DMAOMR_DTCEFD_Msk (0x1UL << ETH_DMAOMR_DTCEFD_Pos)

#define	ETH_DMAOMR_DTCEFD ETH_DMAOMR_DTCEFD_Msk /* Disable Dropping of TCP/IP checksum error frames */

#define	ETH_DMAOMR_RSF_Pos (25U)

#define	ETH_DMAOMR_RSF_Msk (0x1UL << ETH_DMAOMR_RSF_Pos)

#define	ETH_DMAOMR_RSF ETH_DMAOMR_RSF_Msk /* Receive store and forward */

#define	ETH_DMAOMR_DFRF_Pos (24U)

#define	ETH_DMAOMR_DFRF_Msk (0x1UL << ETH_DMAOMR_DFRF_Pos)

#define	ETH_DMAOMR_DFRF ETH_DMAOMR_DFRF_Msk /* Disable flushing of received frames */

#define	ETH_DMAOMR_TSF_Pos (21U)

#define	ETH_DMAOMR_TSF_Msk (0x1UL << ETH_DMAOMR_TSF_Pos)

#define	ETH_DMAOMR_TSF ETH_DMAOMR_TSF_Msk /* Transmit store and forward */

#define	ETH_DMAOMR_FTF_Pos (20U)

#define	ETH_DMAOMR_FTF_Msk (0x1UL << ETH_DMAOMR_FTF_Pos)

#define	ETH_DMAOMR_FTF ETH_DMAOMR_FTF_Msk /* Flush transmit FIFO */

#define	ETH_DMAOMR_TTC_Pos (14U)

#define	ETH_DMAOMR_TTC_Msk (0x7UL << ETH_DMAOMR_TTC_Pos)

#define	ETH_DMAOMR_TTC ETH_DMAOMR_TTC_Msk /* Transmit threshold control */

#define	ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */

#define	ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */

#define	ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */

#define	ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */

#define	ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */

#define	ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */

#define	ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */

#define	ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */

#define	ETH_DMAOMR_ST_Pos (13U)

#define	ETH_DMAOMR_ST_Msk (0x1UL << ETH_DMAOMR_ST_Pos)

#define	ETH_DMAOMR_ST ETH_DMAOMR_ST_Msk /* Start/stop transmission command */

#define	ETH_DMAOMR_FEF_Pos (7U)

#define	ETH_DMAOMR_FEF_Msk (0x1UL << ETH_DMAOMR_FEF_Pos)

#define	ETH_DMAOMR_FEF ETH_DMAOMR_FEF_Msk /* Forward error frames */

#define	ETH_DMAOMR_FUGF_Pos (6U)

#define	ETH_DMAOMR_FUGF_Msk (0x1UL << ETH_DMAOMR_FUGF_Pos)

#define	ETH_DMAOMR_FUGF ETH_DMAOMR_FUGF_Msk /* Forward undersized good frames */

#define	ETH_DMAOMR_RTC_Pos (3U)

#define	ETH_DMAOMR_RTC_Msk (0x3UL << ETH_DMAOMR_RTC_Pos)

#define	ETH_DMAOMR_RTC ETH_DMAOMR_RTC_Msk /* receive threshold control */

#define	ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */

#define	ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */

#define	ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */

#define	ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */

#define	ETH_DMAOMR_OSF_Pos (2U)

#define	ETH_DMAOMR_OSF_Msk (0x1UL << ETH_DMAOMR_OSF_Pos)

#define	ETH_DMAOMR_OSF ETH_DMAOMR_OSF_Msk /* operate on second frame */

#define	ETH_DMAOMR_SR_Pos (1U)

#define	ETH_DMAOMR_SR_Msk (0x1UL << ETH_DMAOMR_SR_Pos)

#define	ETH_DMAOMR_SR ETH_DMAOMR_SR_Msk /* Start/stop receive */

#define	ETH_DMAIER_NISE_Pos (16U)

#define	ETH_DMAIER_NISE_Msk (0x1UL << ETH_DMAIER_NISE_Pos)

#define	ETH_DMAIER_NISE ETH_DMAIER_NISE_Msk /* Normal interrupt summary enable */

#define	ETH_DMAIER_AISE_Pos (15U)

#define	ETH_DMAIER_AISE_Msk (0x1UL << ETH_DMAIER_AISE_Pos)

#define	ETH_DMAIER_AISE ETH_DMAIER_AISE_Msk /* Abnormal interrupt summary enable */

#define	ETH_DMAIER_ERIE_Pos (14U)

#define	ETH_DMAIER_ERIE_Msk (0x1UL << ETH_DMAIER_ERIE_Pos)

#define	ETH_DMAIER_ERIE ETH_DMAIER_ERIE_Msk /* Early receive interrupt enable */

#define	ETH_DMAIER_FBEIE_Pos (13U)

#define	ETH_DMAIER_FBEIE_Msk (0x1UL << ETH_DMAIER_FBEIE_Pos)

#define	ETH_DMAIER_FBEIE ETH_DMAIER_FBEIE_Msk /* Fatal bus error interrupt enable */

#define	ETH_DMAIER_ETIE_Pos (10U)

#define	ETH_DMAIER_ETIE_Msk (0x1UL << ETH_DMAIER_ETIE_Pos)

#define	ETH_DMAIER_ETIE ETH_DMAIER_ETIE_Msk /* Early transmit interrupt enable */

#define	ETH_DMAIER_RWTIE_Pos (9U)

#define	ETH_DMAIER_RWTIE_Msk (0x1UL << ETH_DMAIER_RWTIE_Pos)

#define	ETH_DMAIER_RWTIE ETH_DMAIER_RWTIE_Msk /* Receive watchdog timeout interrupt enable */

#define	ETH_DMAIER_RPSIE_Pos (8U)

#define	ETH_DMAIER_RPSIE_Msk (0x1UL << ETH_DMAIER_RPSIE_Pos)

#define	ETH_DMAIER_RPSIE ETH_DMAIER_RPSIE_Msk /* Receive process stopped interrupt enable */

#define	ETH_DMAIER_RBUIE_Pos (7U)

#define	ETH_DMAIER_RBUIE_Msk (0x1UL << ETH_DMAIER_RBUIE_Pos)

#define	ETH_DMAIER_RBUIE ETH_DMAIER_RBUIE_Msk /* Receive buffer unavailable interrupt enable */

#define	ETH_DMAIER_RIE_Pos (6U)

#define	ETH_DMAIER_RIE_Msk (0x1UL << ETH_DMAIER_RIE_Pos)

#define	ETH_DMAIER_RIE ETH_DMAIER_RIE_Msk /* Receive interrupt enable */

#define	ETH_DMAIER_TUIE_Pos (5U)

#define	ETH_DMAIER_TUIE_Msk (0x1UL << ETH_DMAIER_TUIE_Pos)

#define	ETH_DMAIER_TUIE ETH_DMAIER_TUIE_Msk /* Transmit Underflow interrupt enable */

#define	ETH_DMAIER_ROIE_Pos (4U)

#define	ETH_DMAIER_ROIE_Msk (0x1UL << ETH_DMAIER_ROIE_Pos)

#define	ETH_DMAIER_ROIE ETH_DMAIER_ROIE_Msk /* Receive Overflow interrupt enable */

#define	ETH_DMAIER_TJTIE_Pos (3U)

#define	ETH_DMAIER_TJTIE_Msk (0x1UL << ETH_DMAIER_TJTIE_Pos)

#define	ETH_DMAIER_TJTIE ETH_DMAIER_TJTIE_Msk /* Transmit jabber timeout interrupt enable */

#define	ETH_DMAIER_TBUIE_Pos (2U)

#define	ETH_DMAIER_TBUIE_Msk (0x1UL << ETH_DMAIER_TBUIE_Pos)

#define	ETH_DMAIER_TBUIE ETH_DMAIER_TBUIE_Msk /* Transmit buffer unavailable interrupt enable */

#define	ETH_DMAIER_TPSIE_Pos (1U)

#define	ETH_DMAIER_TPSIE_Msk (0x1UL << ETH_DMAIER_TPSIE_Pos)

#define	ETH_DMAIER_TPSIE ETH_DMAIER_TPSIE_Msk /* Transmit process stopped interrupt enable */

#define	ETH_DMAIER_TIE_Pos (0U)

#define	ETH_DMAIER_TIE_Msk (0x1UL << ETH_DMAIER_TIE_Pos)

#define	ETH_DMAIER_TIE ETH_DMAIER_TIE_Msk /* Transmit interrupt enable */

#define	ETH_DMAMFBOCR_OFOC_Pos (28U)

#define	ETH_DMAMFBOCR_OFOC_Msk (0x1UL << ETH_DMAMFBOCR_OFOC_Pos)

#define	ETH_DMAMFBOCR_OFOC ETH_DMAMFBOCR_OFOC_Msk /* Overflow bit for FIFO overflow counter */

#define	ETH_DMAMFBOCR_MFA_Pos (17U)

#define	ETH_DMAMFBOCR_MFA_Msk (0x7FFUL << ETH_DMAMFBOCR_MFA_Pos)

#define	ETH_DMAMFBOCR_MFA ETH_DMAMFBOCR_MFA_Msk /* Number of frames missed by the application */

#define	ETH_DMAMFBOCR_OMFC_Pos (16U)

#define	ETH_DMAMFBOCR_OMFC_Msk (0x1UL << ETH_DMAMFBOCR_OMFC_Pos)

#define	ETH_DMAMFBOCR_OMFC ETH_DMAMFBOCR_OMFC_Msk /* Overflow bit for missed frame counter */

#define	ETH_DMAMFBOCR_MFC_Pos (0U)

#define	ETH_DMAMFBOCR_MFC_Msk (0xFFFFUL << ETH_DMAMFBOCR_MFC_Pos)

#define	ETH_DMAMFBOCR_MFC ETH_DMAMFBOCR_MFC_Msk /* Number of frames missed by the controller */

#define	ETH_DMACHTDR_HTDAP_Pos (0U)

#define	ETH_DMACHTDR_HTDAP_Msk (0xFFFFFFFFUL << ETH_DMACHTDR_HTDAP_Pos)

#define	ETH_DMACHTDR_HTDAP ETH_DMACHTDR_HTDAP_Msk /* Host transmit descriptor address pointer */

#define	ETH_DMACHRDR_HRDAP_Pos (0U)

#define	ETH_DMACHRDR_HRDAP_Msk (0xFFFFFFFFUL << ETH_DMACHRDR_HRDAP_Pos)

#define	ETH_DMACHRDR_HRDAP ETH_DMACHRDR_HRDAP_Msk /* Host receive descriptor address pointer */

#define	ETH_DMACHTBAR_HTBAP_Pos (0U)

#define	ETH_DMACHTBAR_HTBAP_Msk (0xFFFFFFFFUL << ETH_DMACHTBAR_HTBAP_Pos)

#define	ETH_DMACHTBAR_HTBAP ETH_DMACHTBAR_HTBAP_Msk /* Host transmit buffer address pointer */

#define	ETH_DMACHRBAR_HRBAP_Pos (0U)

#define	ETH_DMACHRBAR_HRBAP_Msk (0xFFFFFFFFUL << ETH_DMACHRBAR_HRBAP_Pos)

#define	ETH_DMACHRBAR_HRBAP ETH_DMACHRBAR_HRBAP_Msk /* Host receive buffer address pointer */

#define	USB_OTG_GOTGCTL_SRQSCS_Pos (0U)

#define	USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos)

#define	USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk

#define	USB_OTG_GOTGCTL_SRQ_Pos (1U)

#define	USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos)

#define	USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk

#define	USB_OTG_GOTGCTL_HNGSCS_Pos (8U)

#define	USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos)

#define	USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk

#define	USB_OTG_GOTGCTL_HNPRQ_Pos (9U)

#define	USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos)

#define	USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk

#define	USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)

#define	USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos)

#define	USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk

#define	USB_OTG_GOTGCTL_DHNPEN_Pos (11U)

#define	USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos)

#define	USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk

#define	USB_OTG_GOTGCTL_CIDSTS_Pos (16U)

#define	USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos)

#define	USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk

#define	USB_OTG_GOTGCTL_DBCT_Pos (17U)

#define	USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos)

#define	USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk

#define	USB_OTG_GOTGCTL_ASVLD_Pos (18U)

#define	USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos)

#define	USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk

#define	USB_OTG_GOTGCTL_BSVLD_Pos (19U)

#define	USB_OTG_GOTGCTL_BSVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSVLD_Pos)

#define	USB_OTG_GOTGCTL_BSVLD USB_OTG_GOTGCTL_BSVLD_Msk

#define	USB_OTG_HCFG_FSLSPCS_Pos (0U)

#define	USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos)

#define	USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk

#define	USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos)

#define	USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos)

#define	USB_OTG_HCFG_FSLSS_Pos (2U)

#define	USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos)

#define	USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk

#define	USB_OTG_DCFG_DSPD_Pos (0U)

#define	USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos)

#define	USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk

#define	USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos)

#define	USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos)

#define	USB_OTG_DCFG_NZLSOHSK_Pos (2U)

#define	USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos)

#define	USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk

#define	USB_OTG_DCFG_DAD_Pos (4U)

#define	USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk

#define	USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos)

#define	USB_OTG_DCFG_PFIVL_Pos (11U)

#define	USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos)

#define	USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk

#define	USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos)

#define	USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos)

#define	USB_OTG_DCFG_PERSCHIVL_Pos (24U)

#define	USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos)

#define	USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk

#define	USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos)

#define	USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos)

#define	USB_OTG_PCGCR_STPPCLK_Pos (0U)

#define	USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos)

#define	USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk

#define	USB_OTG_PCGCR_GATEHCLK_Pos (1U)

#define	USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos)

#define	USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk

#define	USB_OTG_PCGCR_PHYSUSP_Pos (4U)

#define	USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos)

#define	USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk

#define	USB_OTG_GOTGINT_SEDET_Pos (2U)

#define	USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos)

#define	USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk

#define	USB_OTG_GOTGINT_SRSSCHG_Pos (8U)

#define	USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos)

#define	USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk

#define	USB_OTG_GOTGINT_HNSSCHG_Pos (9U)

#define	USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos)

#define	USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk

#define	USB_OTG_GOTGINT_HNGDET_Pos (17U)

#define	USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos)

#define	USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk

#define	USB_OTG_GOTGINT_ADTOCHG_Pos (18U)

#define	USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos)

#define	USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk

#define	USB_OTG_GOTGINT_DBCDNE_Pos (19U)

#define	USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos)

#define	USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk

#define	USB_OTG_DCTL_RWUSIG_Pos (0U)

#define	USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos)

#define	USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk

#define	USB_OTG_DCTL_SDIS_Pos (1U)

#define	USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos)

#define	USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk

#define	USB_OTG_DCTL_GINSTS_Pos (2U)

#define	USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos)

#define	USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk

#define	USB_OTG_DCTL_GONSTS_Pos (3U)

#define	USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos)

#define	USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk

#define	USB_OTG_DCTL_TCTL_Pos (4U)

#define	USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos)

#define	USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk

#define	USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos)

#define	USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos)

#define	USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos)

#define	USB_OTG_DCTL_SGINAK_Pos (7U)

#define	USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos)

#define	USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk

#define	USB_OTG_DCTL_CGINAK_Pos (8U)

#define	USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos)

#define	USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk

#define	USB_OTG_DCTL_SGONAK_Pos (9U)

#define	USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos)

#define	USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk

#define	USB_OTG_DCTL_CGONAK_Pos (10U)

#define	USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos)

#define	USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk

#define	USB_OTG_DCTL_POPRGDNE_Pos (11U)

#define	USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos)

#define	USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk

#define	USB_OTG_HFIR_FRIVL_Pos (0U)

#define	USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos)

#define	USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk

#define	USB_OTG_HFNUM_FRNUM_Pos (0U)

#define	USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos)

#define	USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk

#define	USB_OTG_HFNUM_FTREM_Pos (16U)

#define	USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos)

#define	USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk

#define	USB_OTG_DSTS_SUSPSTS_Pos (0U)

#define	USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos)

#define	USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk

#define	USB_OTG_DSTS_ENUMSPD_Pos (1U)

#define	USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)

#define	USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk

#define	USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)

#define	USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)

#define	USB_OTG_DSTS_EERR_Pos (3U)

#define	USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos)

#define	USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk

#define	USB_OTG_DSTS_FNSOF_Pos (8U)

#define	USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos)

#define	USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk

#define	USB_OTG_GAHBCFG_GINT_Pos (0U)

#define	USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos)

#define	USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk

#define	USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)

#define	USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

#define	USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk

#define	USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

#define	USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

#define	USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

#define	USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

#define	USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos)

#define	USB_OTG_GAHBCFG_DMAEN_Pos (5U)

#define	USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)

#define	USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk

#define	USB_OTG_GAHBCFG_TXFELVL_Pos (7U)

#define	USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos)

#define	USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk

#define	USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)

#define	USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos)

#define	USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk

#define	USB_OTG_GUSBCFG_TOCAL_Pos (0U)

#define	USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos)

#define	USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk

#define	USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos)

#define	USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos)

#define	USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos)

#define	USB_OTG_GUSBCFG_PHYSEL_Pos (6U)

#define	USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos)

#define	USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk

#define	USB_OTG_GUSBCFG_SRPCAP_Pos (8U)

#define	USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos)

#define	USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk

#define	USB_OTG_GUSBCFG_HNPCAP_Pos (9U)

#define	USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos)

#define	USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk

#define	USB_OTG_GUSBCFG_TRDT_Pos (10U)

#define	USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos)

#define	USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk

#define	USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos)

#define	USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos)

#define	USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos)

#define	USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos)

#define	USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)

#define	USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos)

#define	USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk

#define	USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)

#define	USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos)

#define	USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk

#define	USB_OTG_GUSBCFG_ULPIAR_Pos (18U)

#define	USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)

#define	USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk

#define	USB_OTG_GUSBCFG_ULPICSM_Pos (19U)

#define	USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos)

#define	USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk

#define	USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)

#define	USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos)

#define	USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk

#define	USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)

#define	USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos)

#define	USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk

#define	USB_OTG_GUSBCFG_TSDPS_Pos (22U)

#define	USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos)

#define	USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk

#define	USB_OTG_GUSBCFG_PCCI_Pos (23U)

#define	USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos)

#define	USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk

#define	USB_OTG_GUSBCFG_PTCI_Pos (24U)

#define	USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos)

#define	USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk

#define	USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)

#define	USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos)

#define	USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk

#define	USB_OTG_GUSBCFG_FHMOD_Pos (29U)

#define	USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos)

#define	USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk

#define	USB_OTG_GUSBCFG_FDMOD_Pos (30U)

#define	USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos)

#define	USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk

#define	USB_OTG_GUSBCFG_CTXPKT_Pos (31U)

#define	USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos)

#define	USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk

#define	USB_OTG_GRSTCTL_CSRST_Pos (0U)

#define	USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos)

#define	USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk

#define	USB_OTG_GRSTCTL_HSRST_Pos (1U)

#define	USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos)

#define	USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk

#define	USB_OTG_GRSTCTL_FCRST_Pos (2U)

#define	USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos)

#define	USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk

#define	USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)

#define	USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos)

#define	USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk

#define	USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)

#define	USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos)

#define	USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk

#define	USB_OTG_GRSTCTL_TXFNUM_Pos (6U)

#define	USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos)

#define	USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk

#define	USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

#define	USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

#define	USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

#define	USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

#define	USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos)

#define	USB_OTG_GRSTCTL_DMAREQ_Pos (30U)

#define	USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos)

#define	USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk

#define	USB_OTG_GRSTCTL_AHBIDL_Pos (31U)

#define	USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos)

#define	USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk

#define	USB_OTG_DIEPMSK_XFRCM_Pos (0U)

#define	USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos)

#define	USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk

#define	USB_OTG_DIEPMSK_EPDM_Pos (1U)

#define	USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos)

#define	USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk

#define	USB_OTG_DIEPMSK_TOM_Pos (3U)

#define	USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos)

#define	USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk

#define	USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)

#define	USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos)

#define	USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk

#define	USB_OTG_DIEPMSK_INEPNMM_Pos (5U)

#define	USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos)

#define	USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk

#define	USB_OTG_DIEPMSK_INEPNEM_Pos (6U)

#define	USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos)

#define	USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk

#define	USB_OTG_DIEPMSK_TXFURM_Pos (8U)

#define	USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos)

#define	USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk

#define	USB_OTG_DIEPMSK_BIM_Pos (9U)

#define	USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos)

#define	USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk

#define	USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)

#define	USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos)

#define	USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk

#define	USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)

#define	USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk

#define	USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)

#define	USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk

#define	USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos)

#define	USB_OTG_HAINT_HAINT_Pos (0U)

#define	USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos)

#define	USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk

#define	USB_OTG_DOEPMSK_XFRCM_Pos (0U)

#define	USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos)

#define	USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk

#define	USB_OTG_DOEPMSK_EPDM_Pos (1U)

#define	USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos)

#define	USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk

#define	USB_OTG_DOEPMSK_AHBERRM_Pos (2U)

#define	USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos)

#define	USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk

#define	USB_OTG_DOEPMSK_STUPM_Pos (3U)

#define	USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos)

#define	USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk

#define	USB_OTG_DOEPMSK_OTEPDM_Pos (4U)

#define	USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos)

#define	USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk

#define	USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)

#define	USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos)

#define	USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk

#define	USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)

#define	USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos)

#define	USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk

#define	USB_OTG_DOEPMSK_OPEM_Pos (8U)

#define	USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos)

#define	USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk

#define	USB_OTG_DOEPMSK_BOIM_Pos (9U)

#define	USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos)

#define	USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk

#define	USB_OTG_DOEPMSK_BERRM_Pos (12U)

#define	USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos)

#define	USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk

#define	USB_OTG_DOEPMSK_NAKM_Pos (13U)

#define	USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos)

#define	USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk

#define	USB_OTG_DOEPMSK_NYETM_Pos (14U)

#define	USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos)

#define	USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk

#define	USB_OTG_GINTSTS_CMOD_Pos (0U)

#define	USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos)

#define	USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk

#define	USB_OTG_GINTSTS_MMIS_Pos (1U)

#define	USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos)

#define	USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk

#define	USB_OTG_GINTSTS_OTGINT_Pos (2U)

#define	USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos)

#define	USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk

#define	USB_OTG_GINTSTS_SOF_Pos (3U)

#define	USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos)

#define	USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk

#define	USB_OTG_GINTSTS_RXFLVL_Pos (4U)

#define	USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos)

#define	USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk

#define	USB_OTG_GINTSTS_NPTXFE_Pos (5U)

#define	USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos)

#define	USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk

#define	USB_OTG_GINTSTS_GINAKEFF_Pos (6U)

#define	USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos)

#define	USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk

#define	USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)

#define	USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos)

#define	USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk

#define	USB_OTG_GINTSTS_ESUSP_Pos (10U)

#define	USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos)

#define	USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk

#define	USB_OTG_GINTSTS_USBSUSP_Pos (11U)

#define	USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos)

#define	USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk

#define	USB_OTG_GINTSTS_USBRST_Pos (12U)

#define	USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos)

#define	USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk

#define	USB_OTG_GINTSTS_ENUMDNE_Pos (13U)

#define	USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos)

#define	USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk

#define	USB_OTG_GINTSTS_ISOODRP_Pos (14U)

#define	USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos)

#define	USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk

#define	USB_OTG_GINTSTS_EOPF_Pos (15U)

#define	USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos)

#define	USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk

#define	USB_OTG_GINTSTS_IEPINT_Pos (18U)

#define	USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos)

#define	USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk

#define	USB_OTG_GINTSTS_OEPINT_Pos (19U)

#define	USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos)

#define	USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk

#define	USB_OTG_GINTSTS_IISOIXFR_Pos (20U)

#define	USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos)

#define	USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk

#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)

#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos)

#define	USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk

#define	USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)

#define	USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos)

#define	USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk

#define	USB_OTG_GINTSTS_HPRTINT_Pos (24U)

#define	USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos)

#define	USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk

#define	USB_OTG_GINTSTS_HCINT_Pos (25U)

#define	USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos)

#define	USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk

#define	USB_OTG_GINTSTS_PTXFE_Pos (26U)

#define	USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos)

#define	USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk

#define	USB_OTG_GINTSTS_CIDSCHG_Pos (28U)

#define	USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos)

#define	USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk

#define	USB_OTG_GINTSTS_DISCINT_Pos (29U)

#define	USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos)

#define	USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk

#define	USB_OTG_GINTSTS_SRQINT_Pos (30U)

#define	USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos)

#define	USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk

#define	USB_OTG_GINTSTS_WKUINT_Pos (31U)

#define	USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos)

#define	USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk

#define	USB_OTG_GINTMSK_MMISM_Pos (1U)

#define	USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos)

#define	USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk

#define	USB_OTG_GINTMSK_OTGINT_Pos (2U)

#define	USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos)

#define	USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk

#define	USB_OTG_GINTMSK_SOFM_Pos (3U)

#define	USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos)

#define	USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk

#define	USB_OTG_GINTMSK_RXFLVLM_Pos (4U)

#define	USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos)

#define	USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk

#define	USB_OTG_GINTMSK_NPTXFEM_Pos (5U)

#define	USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos)

#define	USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk

#define	USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)

#define	USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos)

#define	USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk

#define	USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)

#define	USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos)

#define	USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk

#define	USB_OTG_GINTMSK_ESUSPM_Pos (10U)

#define	USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos)

#define	USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk

#define	USB_OTG_GINTMSK_USBSUSPM_Pos (11U)

#define	USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos)

#define	USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk

#define	USB_OTG_GINTMSK_USBRST_Pos (12U)

#define	USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos)

#define	USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk

#define	USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)

#define	USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos)

#define	USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk

#define	USB_OTG_GINTMSK_ISOODRPM_Pos (14U)

#define	USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos)

#define	USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk

#define	USB_OTG_GINTMSK_EOPFM_Pos (15U)

#define	USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos)

#define	USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk

#define	USB_OTG_GINTMSK_EPMISM_Pos (17U)

#define	USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos)

#define	USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk

#define	USB_OTG_GINTMSK_IEPINT_Pos (18U)

#define	USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos)

#define	USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk

#define	USB_OTG_GINTMSK_OEPINT_Pos (19U)

#define	USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos)

#define	USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk

#define	USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)

#define	USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos)

#define	USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk

#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)

#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos)

#define	USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk

#define	USB_OTG_GINTMSK_FSUSPM_Pos (22U)

#define	USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos)

#define	USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk

#define	USB_OTG_GINTMSK_PRTIM_Pos (24U)

#define	USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos)

#define	USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk

#define	USB_OTG_GINTMSK_HCIM_Pos (25U)

#define	USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos)

#define	USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk

#define	USB_OTG_GINTMSK_PTXFEM_Pos (26U)

#define	USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos)

#define	USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk

#define	USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)

#define	USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos)

#define	USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk

#define	USB_OTG_GINTMSK_DISCINT_Pos (29U)

#define	USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos)

#define	USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk

#define	USB_OTG_GINTMSK_SRQIM_Pos (30U)

#define	USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos)

#define	USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk

#define	USB_OTG_GINTMSK_WUIM_Pos (31U)

#define	USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos)

#define	USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk

#define	USB_OTG_DAINT_IEPINT_Pos (0U)

#define	USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos)

#define	USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk

#define	USB_OTG_DAINT_OEPINT_Pos (16U)

#define	USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos)

#define	USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk

#define	USB_OTG_HAINTMSK_HAINTM_Pos (0U)

#define	USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos)

#define	USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk

#define	USB_OTG_GRXSTSP_EPNUM_Pos (0U)

#define	USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)

#define	USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk

#define	USB_OTG_GRXSTSP_BCNT_Pos (4U)

#define	USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)

#define	USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk

#define	USB_OTG_GRXSTSP_DPID_Pos (15U)

#define	USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)

#define	USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk

#define	USB_OTG_GRXSTSP_PKTSTS_Pos (17U)

#define	USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos)

#define	USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk

#define	USB_OTG_DAINTMSK_IEPM_Pos (0U)

#define	USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos)

#define	USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk

#define	USB_OTG_DAINTMSK_OEPM_Pos (16U)

#define	USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos)

#define	USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk

#define	USB_OTG_GRXFSIZ_RXFD_Pos (0U)

#define	USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos)

#define	USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk

#define	USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)

#define	USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos)

#define	USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk

#define	USB_OTG_NPTXFSA_Pos (0U)

#define	USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos)

#define	USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk

#define	USB_OTG_NPTXFD_Pos (16U)

#define	USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos)

#define	USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk

#define	USB_OTG_TX0FSA_Pos (0U)

#define	USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos)

#define	USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk

#define	USB_OTG_TX0FD_Pos (16U)

#define	USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos)

#define	USB_OTG_TX0FD USB_OTG_TX0FD_Msk

#define	USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)

#define	USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos)

#define	USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk

#define	USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)

#define	USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk

#define	USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk

#define	USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk

#define	USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos)

#define	USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)

#define	USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos)

#define	USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk

#define	USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)

#define	USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos)

#define	USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk

#define	USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)

#define	USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk

#define	USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHREN_Pos (16U)

#define	USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos)

#define	USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk

#define	USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)

#define	USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk

#define	USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos)

#define	USB_OTG_DTHRCTL_ARPEN_Pos (27U)

#define	USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos)

#define	USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk

#define	USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)

#define	USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos)

#define	USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk

#define	USB_OTG_DEACHINT_IEP1INT_Pos (1U)

#define	USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos)

#define	USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk

#define	USB_OTG_DEACHINT_OEP1INT_Pos (17U)

#define	USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos)

#define	USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk

#define	USB_OTG_GCCFG_PWRDWN_Pos (16U)

#define	USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos)

#define	USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk

#define	USB_OTG_GCCFG_VBUSASEN_Pos (18U)

#define	USB_OTG_GCCFG_VBUSASEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSASEN_Pos)

#define	USB_OTG_GCCFG_VBUSASEN USB_OTG_GCCFG_VBUSASEN_Msk

#define	USB_OTG_GCCFG_VBUSBSEN_Pos (19U)

#define	USB_OTG_GCCFG_VBUSBSEN_Msk (0x1UL << USB_OTG_GCCFG_VBUSBSEN_Pos)

#define	USB_OTG_GCCFG_VBUSBSEN USB_OTG_GCCFG_VBUSBSEN_Msk

#define	USB_OTG_GCCFG_SOFOUTEN_Pos (20U)

#define	USB_OTG_GCCFG_SOFOUTEN_Msk (0x1UL << USB_OTG_GCCFG_SOFOUTEN_Pos)

#define	USB_OTG_GCCFG_SOFOUTEN USB_OTG_GCCFG_SOFOUTEN_Msk

#define	USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)

#define	USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos)

#define	USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk

#define	USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)

#define	USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos)

#define	USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk

#define	USB_OTG_CID_PRODUCT_ID_Pos (0U)

#define	USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos)

#define	USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk

#define	USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)

#define	USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos)

#define	USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk

#define	USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)

#define	USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos)

#define	USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk

#define	USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)

#define	USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos)

#define	USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk

#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)

#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos)

#define	USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk

#define	USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)

#define	USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos)

#define	USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk

#define	USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)

#define	USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos)

#define	USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk

#define	USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)

#define	USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos)

#define	USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk

#define	USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)

#define	USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos)

#define	USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk

#define	USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)

#define	USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos)

#define	USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk

#define	USB_OTG_HPRT_PCSTS_Pos (0U)

#define	USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos)

#define	USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk

#define	USB_OTG_HPRT_PCDET_Pos (1U)

#define	USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos)

#define	USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk

#define	USB_OTG_HPRT_PENA_Pos (2U)

#define	USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos)

#define	USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk

#define	USB_OTG_HPRT_PENCHNG_Pos (3U)

#define	USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos)

#define	USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk

#define	USB_OTG_HPRT_POCA_Pos (4U)

#define	USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos)

#define	USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk

#define	USB_OTG_HPRT_POCCHNG_Pos (5U)

#define	USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos)

#define	USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk

#define	USB_OTG_HPRT_PRES_Pos (6U)

#define	USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos)

#define	USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk

#define	USB_OTG_HPRT_PSUSP_Pos (7U)

#define	USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos)

#define	USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk

#define	USB_OTG_HPRT_PRST_Pos (8U)

#define	USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos)

#define	USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk

#define	USB_OTG_HPRT_PLSTS_Pos (10U)

#define	USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos)

#define	USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk

#define	USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos)

#define	USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos)

#define	USB_OTG_HPRT_PPWR_Pos (12U)

#define	USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos)

#define	USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk

#define	USB_OTG_HPRT_PTCTL_Pos (13U)

#define	USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos)

#define	USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk

#define	USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos)

#define	USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos)

#define	USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos)

#define	USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos)

#define	USB_OTG_HPRT_PSPD_Pos (17U)

#define	USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos)

#define	USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk

#define	USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos)

#define	USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos)

#define	USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)

#define	USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos)

#define	USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk

#define	USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)

#define	USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos)

#define	USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk

#define	USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)

#define	USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos)

#define	USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk

#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)

#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos)

#define	USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk

#define	USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)

#define	USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos)

#define	USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk

#define	USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)

#define	USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos)

#define	USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk

#define	USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)

#define	USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos)

#define	USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk

#define	USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)

#define	USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos)

#define	USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk

#define	USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)

#define	USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos)

#define	USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk

#define	USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)

#define	USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos)

#define	USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk

#define	USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)

#define	USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos)

#define	USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk

#define	USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)

#define	USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos)

#define	USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk

#define	USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)

#define	USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos)

#define	USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk

#define	USB_OTG_DIEPCTL_MPSIZ_Pos (0U)

#define	USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos)

#define	USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk

#define	USB_OTG_DIEPCTL_USBAEP_Pos (15U)

#define	USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos)

#define	USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk

#define	USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)

#define	USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos)

#define	USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk

#define	USB_OTG_DIEPCTL_NAKSTS_Pos (17U)

#define	USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos)

#define	USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk

#define	USB_OTG_DIEPCTL_EPTYP_Pos (18U)

#define	USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos)

#define	USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk

#define	USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos)

#define	USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos)

#define	USB_OTG_DIEPCTL_STALL_Pos (21U)

#define	USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos)

#define	USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk

#define	USB_OTG_DIEPCTL_TXFNUM_Pos (22U)

#define	USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos)

#define	USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk

#define	USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

#define	USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

#define	USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

#define	USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos)

#define	USB_OTG_DIEPCTL_CNAK_Pos (26U)

#define	USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos)

#define	USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk

#define	USB_OTG_DIEPCTL_SNAK_Pos (27U)

#define	USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos)

#define	USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk

#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)

#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos)

#define	USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk

#define	USB_OTG_DIEPCTL_SODDFRM_Pos (29U)

#define	USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos)

#define	USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk

#define	USB_OTG_DIEPCTL_EPDIS_Pos (30U)

#define	USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos)

#define	USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk

#define	USB_OTG_DIEPCTL_EPENA_Pos (31U)

#define	USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos)

#define	USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk

#define	USB_OTG_HCCHAR_MPSIZ_Pos (0U)

#define	USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos)

#define	USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk

#define	USB_OTG_HCCHAR_EPNUM_Pos (11U)

#define	USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos)

#define	USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk

#define	USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos)

#define	USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos)

#define	USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos)

#define	USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos)

#define	USB_OTG_HCCHAR_EPDIR_Pos (15U)

#define	USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos)

#define	USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk

#define	USB_OTG_HCCHAR_LSDEV_Pos (17U)

#define	USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos)

#define	USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk

#define	USB_OTG_HCCHAR_EPTYP_Pos (18U)

#define	USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos)

#define	USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk

#define	USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos)

#define	USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos)

#define	USB_OTG_HCCHAR_MC_Pos (20U)

#define	USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos)

#define	USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk

#define	USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos)

#define	USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos)

#define	USB_OTG_HCCHAR_DAD_Pos (22U)

#define	USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk

#define	USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos)

#define	USB_OTG_HCCHAR_ODDFRM_Pos (29U)

#define	USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos)

#define	USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk

#define	USB_OTG_HCCHAR_CHDIS_Pos (30U)

#define	USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos)

#define	USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk

#define	USB_OTG_HCCHAR_CHENA_Pos (31U)

#define	USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos)

#define	USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk

#define	USB_OTG_HCSPLT_PRTADDR_Pos (0U)

#define	USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk

#define	USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_Pos (7U)

#define	USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk

#define	USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos)

#define	USB_OTG_HCSPLT_XACTPOS_Pos (14U)

#define	USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos)

#define	USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk

#define	USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos)

#define	USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos)

#define	USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)

#define	USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos)

#define	USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk

#define	USB_OTG_HCSPLT_SPLITEN_Pos (31U)

#define	USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos)

#define	USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk

#define	USB_OTG_HCINT_XFRC_Pos (0U)

#define	USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos)

#define	USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk

#define	USB_OTG_HCINT_CHH_Pos (1U)

#define	USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos)

#define	USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk

#define	USB_OTG_HCINT_AHBERR_Pos (2U)

#define	USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos)

#define	USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk

#define	USB_OTG_HCINT_STALL_Pos (3U)

#define	USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos)

#define	USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk

#define	USB_OTG_HCINT_NAK_Pos (4U)

#define	USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos)

#define	USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk

#define	USB_OTG_HCINT_ACK_Pos (5U)

#define	USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos)

#define	USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk

#define	USB_OTG_HCINT_NYET_Pos (6U)

#define	USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos)

#define	USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk

#define	USB_OTG_HCINT_TXERR_Pos (7U)

#define	USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos)

#define	USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk

#define	USB_OTG_HCINT_BBERR_Pos (8U)

#define	USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos)

#define	USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk

#define	USB_OTG_HCINT_FRMOR_Pos (9U)

#define	USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos)

#define	USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk

#define	USB_OTG_HCINT_DTERR_Pos (10U)

#define	USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos)

#define	USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk

#define	USB_OTG_DIEPINT_XFRC_Pos (0U)

#define	USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos)

#define	USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk

#define	USB_OTG_DIEPINT_EPDISD_Pos (1U)

#define	USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos)

#define	USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk

#define	USB_OTG_DIEPINT_AHBERR_Pos (2U)

#define	USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)

#define	USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk

#define	USB_OTG_DIEPINT_TOC_Pos (3U)

#define	USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos)

#define	USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk

#define	USB_OTG_DIEPINT_ITTXFE_Pos (4U)

#define	USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos)

#define	USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk

#define	USB_OTG_DIEPINT_INEPNM_Pos (5U)

#define	USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos)

#define	USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk

#define	USB_OTG_DIEPINT_INEPNE_Pos (6U)

#define	USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos)

#define	USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk

#define	USB_OTG_DIEPINT_TXFE_Pos (7U)

#define	USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)

#define	USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk

#define	USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)

#define	USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos)

#define	USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk

#define	USB_OTG_DIEPINT_BNA_Pos (9U)

#define	USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos)

#define	USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk

#define	USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)

#define	USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos)

#define	USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk

#define	USB_OTG_DIEPINT_BERR_Pos (12U)

#define	USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos)

#define	USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk

#define	USB_OTG_DIEPINT_NAK_Pos (13U)

#define	USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos)

#define	USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk

#define	USB_OTG_HCINTMSK_XFRCM_Pos (0U)

#define	USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos)

#define	USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk

#define	USB_OTG_HCINTMSK_CHHM_Pos (1U)

#define	USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos)

#define	USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk

#define	USB_OTG_HCINTMSK_AHBERR_Pos (2U)

#define	USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos)

#define	USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk

#define	USB_OTG_HCINTMSK_STALLM_Pos (3U)

#define	USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos)

#define	USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk

#define	USB_OTG_HCINTMSK_NAKM_Pos (4U)

#define	USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos)

#define	USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk

#define	USB_OTG_HCINTMSK_ACKM_Pos (5U)

#define	USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos)

#define	USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk

#define	USB_OTG_HCINTMSK_NYET_Pos (6U)

#define	USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos)

#define	USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk

#define	USB_OTG_HCINTMSK_TXERRM_Pos (7U)

#define	USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos)

#define	USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk

#define	USB_OTG_HCINTMSK_BBERRM_Pos (8U)

#define	USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos)

#define	USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk

#define	USB_OTG_HCINTMSK_FRMORM_Pos (9U)

#define	USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos)

#define	USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk

#define	USB_OTG_HCINTMSK_DTERRM_Pos (10U)

#define	USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos)

#define	USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk

#define	USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)

#define	USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos)

#define	USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk

#define	USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)

#define	USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos)

#define	USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk

#define	USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)

#define	USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos)

#define	USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk

#define	USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)

#define	USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos)

#define	USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk

#define	USB_OTG_HCTSIZ_PKTCNT_Pos (19U)

#define	USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos)

#define	USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk

#define	USB_OTG_HCTSIZ_DOPING_Pos (31U)

#define	USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos)

#define	USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk

#define	USB_OTG_HCTSIZ_DPID_Pos (29U)

#define	USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos)

#define	USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk

#define	USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos)

#define	USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos)

#define	USB_OTG_DIEPDMA_DMAADDR_Pos (0U)

#define	USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)

#define	USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk

#define	USB_OTG_HCDMA_DMAADDR_Pos (0U)

#define	USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos)

#define	USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk

#define	USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)

#define	USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos)

#define	USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk

#define	USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)

#define	USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos)

#define	USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk

#define	USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)

#define	USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos)

#define	USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk

#define	USB_OTG_DOEPCTL_MPSIZ_Pos (0U)

#define	USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos)

#define	USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /!< Maximum packet size /

#define	USB_OTG_DOEPCTL_USBAEP_Pos (15U)

#define	USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos)

#define	USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk

#define	USB_OTG_DOEPCTL_NAKSTS_Pos (17U)

#define	USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos)

#define	USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk

#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)

#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos)

#define	USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk

#define	USB_OTG_DOEPCTL_SODDFRM_Pos (29U)

#define	USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos)

#define	USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk

#define	USB_OTG_DOEPCTL_EPTYP_Pos (18U)

#define	USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos)

#define	USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk

#define	USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos)

#define	USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos)

#define	USB_OTG_DOEPCTL_SNPM_Pos (20U)

#define	USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos)

#define	USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk

#define	USB_OTG_DOEPCTL_STALL_Pos (21U)

#define	USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos)

#define	USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk

#define	USB_OTG_DOEPCTL_CNAK_Pos (26U)

#define	USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos)

#define	USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk

#define	USB_OTG_DOEPCTL_SNAK_Pos (27U)

#define	USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos)

#define	USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk

#define	USB_OTG_DOEPCTL_EPDIS_Pos (30U)

#define	USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos)

#define	USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk

#define	USB_OTG_DOEPCTL_EPENA_Pos (31U)

#define	USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos)

#define	USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk

#define	USB_OTG_DOEPINT_XFRC_Pos (0U)

#define	USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos)

#define	USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk

#define	USB_OTG_DOEPINT_EPDISD_Pos (1U)

#define	USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos)

#define	USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk

#define	USB_OTG_DOEPINT_AHBERR_Pos (2U)

#define	USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)

#define	USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk

#define	USB_OTG_DOEPINT_STUP_Pos (3U)

#define	USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos)

#define	USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk

#define	USB_OTG_DOEPINT_OTEPDIS_Pos (4U)

#define	USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos)

#define	USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk

#define	USB_OTG_DOEPINT_OTEPSPR_Pos (5U)

#define	USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)

#define	USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk

#define	USB_OTG_DOEPINT_B2BSTUP_Pos (6U)

#define	USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos)

#define	USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk

#define	USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)

#define	USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)

#define	USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk

#define	USB_OTG_DOEPINT_NAK_Pos (13U)

#define	USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos)

#define	USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk

#define	USB_OTG_DOEPINT_NYET_Pos (14U)

#define	USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos)

#define	USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk

#define	USB_OTG_DOEPINT_STPKTRX_Pos (15U)

#define	USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)

#define	USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk

#define	USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)

#define	USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos)

#define	USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk

#define	USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)

#define	USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos)

#define	USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk

#define	USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)

#define	USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)

#define	USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk

#define	USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)

#define	USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos)

#define	USB_OTG_PCGCCTL_STOPCLK_Pos (0U)

#define	USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)

#define	USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk

#define	USB_OTG_PCGCCTL_GATECLK_Pos (1U)

#define	USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)

#define	USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk

#define	USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)

#define	USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)

#define	USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk

#define	USB_OTG_CHNUM_Pos (0U)

#define	USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos)

#define	USB_OTG_CHNUM USB_OTG_CHNUM_Msk

#define	USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos)

#define	USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos)

#define	USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos)

#define	USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos)

#define	USB_OTG_BCNT_Pos (4U)

#define	USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos)

#define	USB_OTG_BCNT USB_OTG_BCNT_Msk

#define	USB_OTG_DPID_Pos (15U)

#define	USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos)

#define	USB_OTG_DPID USB_OTG_DPID_Msk

#define	USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos)

#define	USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos)

#define	USB_OTG_PKTSTS_Pos (17U)

#define	USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos)

#define	USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk

#define	USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos)

#define	USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos)

#define	USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos)

#define	USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos)

#define	USB_OTG_EPNUM_Pos (0U)

#define	USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos)

#define	USB_OTG_EPNUM USB_OTG_EPNUM_Msk

#define	USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos)

#define	USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos)

#define	USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos)

#define	USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos)

#define	USB_OTG_FRMNUM_Pos (21U)

#define	USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos)

#define	USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk

#define	USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos)

#define	USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos)

#define	USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos)

#define	USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos)

#define	IS_ADC_ALL_INSTANCE(INSTANCE)

#define	IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)

#define	IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

#define	IS_ADC_DMA_CAPABILITY_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

#define	IS_CAN_ALL_INSTANCE(INSTANCE)

#define	IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

#define	IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

#define	IS_DMA_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)

#define	IS_I2C_ALL_INSTANCE(INSTANCE)

#define	IS_SMBUS_ALL_INSTANCE IS_I2C_ALL_INSTANCE

#define	IS_I2S_ALL_INSTANCE(INSTANCE)

#define	IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)

#define	IS_SPI_ALL_INSTANCE(INSTANCE)

#define	IS_TIM_INSTANCE(INSTANCE)

#define	IS_TIM_ADVANCED_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_CC1_INSTANCE(INSTANCE)

#define	IS_TIM_CC2_INSTANCE(INSTANCE)

#define	IS_TIM_CC3_INSTANCE(INSTANCE)

#define	IS_TIM_CC4_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)

#define	IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)

#define	IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)

#define	IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)

#define	IS_TIM_XOR_INSTANCE(INSTANCE)

#define	IS_TIM_MASTER_INSTANCE(INSTANCE)

#define	IS_TIM_SLAVE_INSTANCE(INSTANCE)

#define	IS_TIM_DMABURST_INSTANCE(INSTANCE)

#define	IS_TIM_BREAK_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL)

#define	IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL)

#define	IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)

#define	IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)

#define	IS_TIM_DMA_INSTANCE(INSTANCE)

#define	IS_TIM_DMA_CC_INSTANCE(INSTANCE)

#define	IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) ((INSTANCE) == TIM1)

#define	IS_TIM_ETR_INSTANCE(INSTANCE)

#define	IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)

#define	IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) 0U

#define	IS_USART_INSTANCE(INSTANCE)

#define	IS_UART_INSTANCE(INSTANCE)

#define	IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)

#define	IS_UART_LIN_INSTANCE(INSTANCE)

#define	IS_UART_HWFLOW_INSTANCE(INSTANCE)

#define	IS_SMARTCARD_INSTANCE(INSTANCE)

#define	IS_IRDA_INSTANCE(INSTANCE)

#define	IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)

#define	IS_UART_DMA_INSTANCE(INSTANCE)

#define	IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)

#define	IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)

#define	IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

#define	IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_FS)

#define	IS_ETH_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ETH)

#define	RCC_HSE_MIN 3000000U

#define	RCC_HSE_MAX 25000000U

#define	RCC_MAX_FREQUENCY 72000000U

#define	ADC1_IRQn ADC1_2_IRQn

#define	USB_LP_IRQn CAN1_RX0_IRQn

#define	USB_LP_CAN1_RX0_IRQn CAN1_RX0_IRQn

#define	USB_HP_IRQn CAN1_TX_IRQn

#define	USB_HP_CAN1_TX_IRQn CAN1_TX_IRQn

#define	DMA2_Channel4_5_IRQn DMA2_Channel4_IRQn

#define	USBWakeUp_IRQn OTG_FS_WKUP_IRQn

#define	CEC_IRQn OTG_FS_WKUP_IRQn

#define	TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn

#define	TIM1_BRK_TIM15_IRQn TIM1_BRK_IRQn

#define	TIM9_IRQn TIM1_BRK_IRQn

#define	TIM11_IRQn TIM1_TRG_COM_IRQn

#define	TIM1_TRG_COM_TIM17_IRQn TIM1_TRG_COM_IRQn

#define	TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn

#define	TIM1_UP_TIM16_IRQn TIM1_UP_IRQn

#define	TIM1_UP_TIM10_IRQn TIM1_UP_IRQn

#define	TIM10_IRQn TIM1_UP_IRQn

#define	TIM6_DAC_IRQn TIM6_IRQn

#define	ADC1_IRQHandler ADC1_2_IRQHandler

#define	USB_LP_IRQHandler CAN1_RX0_IRQHandler

#define	USB_LP_CAN1_RX0_IRQHandler CAN1_RX0_IRQHandler

#define	USB_HP_IRQHandler CAN1_TX_IRQHandler

#define	USB_HP_CAN1_TX_IRQHandler CAN1_TX_IRQHandler

#define	DMA2_Channel4_5_IRQHandler DMA2_Channel4_IRQHandler

#define	USBWakeUp_IRQHandler OTG_FS_WKUP_IRQHandler

#define	CEC_IRQHandler OTG_FS_WKUP_IRQHandler

#define	TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler

#define	TIM1_BRK_TIM15_IRQHandler TIM1_BRK_IRQHandler

#define	TIM9_IRQHandler TIM1_BRK_IRQHandler

#define	TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

#define	TIM1_TRG_COM_TIM17_IRQHandler TIM1_TRG_COM_IRQHandler

#define	TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler

#define	TIM1_UP_TIM16_IRQHandler TIM1_UP_IRQHandler

#define	TIM1_UP_TIM10_IRQHandler TIM1_UP_IRQHandler

#define	TIM10_IRQHandler TIM1_UP_IRQHandler

#define	TIM6_DAC_IRQHandler TIM6_IRQHandler

Enumerations
enum	IRQn_Type { NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , EXTI9_5_IRQn = 23 , TIM1_BRK_TIM15_IRQn = 24 , TIM1_UP_TIM16_IRQn = 25 , TIM1_TRG_COM_TIM17_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , CEC_IRQn = 42 , TIM6_DAC_IRQn = 54 , TIM7_IRQn = 55 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , EXTI9_5_IRQn = 23 , TIM1_BRK_TIM15_IRQn = 24 , TIM1_UP_TIM16_IRQn = 25 , TIM1_TRG_COM_TIM17_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , CEC_IRQn = 42 , TIM12_IRQn = 43 , TIM13_IRQn = 44 , TIM14_IRQn = 45 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_DAC_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_5_IRQn = 59 , DMA2_Channel4_IRQn = 59 , DMA2_Channel5_IRQn = 60 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , EXTI9_5_IRQn = 23 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , SPI1_IRQn = 35 , USART1_IRQn = 37 , USART2_IRQn = 38 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , EXTI9_5_IRQn = 23 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , EXTI9_5_IRQn = 23 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , FSMC_IRQn = 48 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_5_IRQn = 59 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , EXTI9_5_IRQn = 23 , TIM9_IRQn = 24 , TIM10_IRQn = 25 , TIM11_IRQn = 26 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , TIM12_IRQn = 43 , TIM13_IRQn = 44 , TIM14_IRQn = 45 , FSMC_IRQn = 48 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_5_IRQn = 59 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , USB_HP_IRQn = 19 , USB_LP_IRQn = 20 , EXTI9_5_IRQn = 23 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , SPI1_IRQn = 35 , USART1_IRQn = 37 , USART2_IRQn = 38 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , USBWakeUp_IRQn = 42 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_IRQn = 18 , USB_HP_IRQn = 19 , USB_LP_IRQn = 20 , EXTI9_5_IRQn = 23 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , USBWakeUp_IRQn = 42 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , USB_HP_CAN1_TX_IRQn = 19 , USB_LP_CAN1_RX0_IRQn = 20 , CAN1_RX1_IRQn = 21 , CAN1_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_IRQn = 24 , TIM1_UP_IRQn = 25 , TIM1_TRG_COM_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , SPI1_IRQn = 35 , USART1_IRQn = 37 , USART2_IRQn = 38 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , USBWakeUp_IRQn = 42 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , USB_HP_CAN1_TX_IRQn = 19 , USB_LP_CAN1_RX0_IRQn = 20 , CAN1_RX1_IRQn = 21 , CAN1_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_IRQn = 24 , TIM1_UP_IRQn = 25 , TIM1_TRG_COM_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , USBWakeUp_IRQn = 42 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , USB_HP_CAN1_TX_IRQn = 19 , USB_LP_CAN1_RX0_IRQn = 20 , CAN1_RX1_IRQn = 21 , CAN1_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_IRQn = 24 , TIM1_UP_IRQn = 25 , TIM1_TRG_COM_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , USBWakeUp_IRQn = 42 , TIM8_BRK_IRQn = 43 , TIM8_UP_IRQn = 44 , TIM8_TRG_COM_IRQn = 45 , TIM8_CC_IRQn = 46 , ADC3_IRQn = 47 , FSMC_IRQn = 48 , SDIO_IRQn = 49 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_5_IRQn = 59 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , USB_HP_CAN1_TX_IRQn = 19 , USB_LP_CAN1_RX0_IRQn = 20 , CAN1_RX1_IRQn = 21 , CAN1_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_TIM9_IRQn = 24 , TIM1_UP_TIM10_IRQn = 25 , TIM1_TRG_COM_TIM11_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , USBWakeUp_IRQn = 42 , TIM8_BRK_TIM12_IRQn = 43 , TIM8_UP_TIM13_IRQn = 44 , TIM8_TRG_COM_TIM14_IRQn = 45 , TIM8_CC_IRQn = 46 , ADC3_IRQn = 47 , FSMC_IRQn = 48 , SDIO_IRQn = 49 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_5_IRQn = 59 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , CAN1_TX_IRQn = 19 , CAN1_RX0_IRQn = 20 , CAN1_RX1_IRQn = 21 , CAN1_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_IRQn = 24 , TIM1_UP_IRQn = 25 , TIM1_TRG_COM_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , OTG_FS_WKUP_IRQn = 42 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_IRQn = 59 , DMA2_Channel5_IRQn = 60 , CAN2_TX_IRQn = 63 , CAN2_RX0_IRQn = 64 , CAN2_RX1_IRQn = 65 , CAN2_SCE_IRQn = 66 , OTG_FS_IRQn = 67 , NonMaskableInt_IRQn = -14 , HardFault_IRQn = -13 , MemoryManagement_IRQn = -12 , BusFault_IRQn = -11 , UsageFault_IRQn = -10 , SVCall_IRQn = -5 , DebugMonitor_IRQn = -4 , PendSV_IRQn = -2 , SysTick_IRQn = -1 , WWDG_IRQn = 0 , PVD_IRQn = 1 , TAMPER_IRQn = 2 , RTC_IRQn = 3 , FLASH_IRQn = 4 , RCC_IRQn = 5 , EXTI0_IRQn = 6 , EXTI1_IRQn = 7 , EXTI2_IRQn = 8 , EXTI3_IRQn = 9 , EXTI4_IRQn = 10 , DMA1_Channel1_IRQn = 11 , DMA1_Channel2_IRQn = 12 , DMA1_Channel3_IRQn = 13 , DMA1_Channel4_IRQn = 14 , DMA1_Channel5_IRQn = 15 , DMA1_Channel6_IRQn = 16 , DMA1_Channel7_IRQn = 17 , ADC1_2_IRQn = 18 , CAN1_TX_IRQn = 19 , CAN1_RX0_IRQn = 20 , CAN1_RX1_IRQn = 21 , CAN1_SCE_IRQn = 22 , EXTI9_5_IRQn = 23 , TIM1_BRK_IRQn = 24 , TIM1_UP_IRQn = 25 , TIM1_TRG_COM_IRQn = 26 , TIM1_CC_IRQn = 27 , TIM2_IRQn = 28 , TIM3_IRQn = 29 , TIM4_IRQn = 30 , I2C1_EV_IRQn = 31 , I2C1_ER_IRQn = 32 , I2C2_EV_IRQn = 33 , I2C2_ER_IRQn = 34 , SPI1_IRQn = 35 , SPI2_IRQn = 36 , USART1_IRQn = 37 , USART2_IRQn = 38 , USART3_IRQn = 39 , EXTI15_10_IRQn = 40 , RTC_Alarm_IRQn = 41 , OTG_FS_WKUP_IRQn = 42 , TIM5_IRQn = 50 , SPI3_IRQn = 51 , UART4_IRQn = 52 , UART5_IRQn = 53 , TIM6_IRQn = 54 , TIM7_IRQn = 55 , DMA2_Channel1_IRQn = 56 , DMA2_Channel2_IRQn = 57 , DMA2_Channel3_IRQn = 58 , DMA2_Channel4_IRQn = 59 , DMA2_Channel5_IRQn = 60 , ETH_IRQn = 61 , ETH_WKUP_IRQn = 62 , CAN2_TX_IRQn = 63 , CAN2_RX0_IRQn = 64 , CAN2_RX1_IRQn = 65 , CAN2_SCE_IRQn = 66 , OTG_FS_IRQn = 67 }
	STM32F10x Interrupt Number Definition, according to the selected device in Library_configuration_section. More...

Detailed Description

CMSIS Cortex-M3 Device Peripheral Access Layer Header File. This file contains all the peripheral register's definitions, bits definitions and memory mapping for STM32F1xx devices.

Author: MCD Application Team

This file contains:

Data structures and the address mapping for all peripherals
Peripheral's registers declarations and bits definition
Macros to access peripheral�s registers hardware

Attention

This software component is licensed by ST under BSD 3-Clause license, the "License"; You may not use this file except in compliance with the License. You may obtain a copy of the License at: opensource.org/licenses/BSD-3-Clause

Data Structures

Macros

Enumerations

Detailed Description

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